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Differential D109264

[GlobalISel] Add G_ROTL and G_ROTR to right_identity_zero
ClosedPublic

Authored by paquette on Sep 3 2021, 6:04 PM.

Details

Reviewers
aemerson
arsenm
jroelofs
Commits
rGac4896e2f372: [GlobalISel] Add G_ROTL and G_ROTR to right_identity_zero
Summary

Similar to DAGCombiner::visitRotate.

rotr x, 0 -> x
rotl x, 0 -> x

This makes rotl_bitwidth_cst in postlegalizercombiner-rotate.mir reduce down to a COPY. Modify the checkline to make sure that only rotate_out_of_range runs there.

Diff Detail

Revision Contents

PathSize
llvm/
include/
llvm/
Target/
GlobalISel/
2 lines
test/
CodeGen/
AArch64/
GlobalISel/
3 lines
36 lines

Diff 371385

llvm/include/llvm/Target/GlobalISel/Combine.td

Show First 20 Lines • Show All 275 Lines • ▼ Show 20 Lines (match (wip_match_opcode G_SELECT):$root,
[{ return Helper.matchConstantSelectCmp(*${root}, ${matchinfo}); }]), [{ return Helper.matchConstantSelectCmp(*${root}, ${matchinfo}); }]),
(apply [{ return Helper.replaceSingleDefInstWithOperand(*${root}, ${matchinfo}); }]) (apply [{ return Helper.replaceSingleDefInstWithOperand(*${root}, ${matchinfo}); }])
>; >;
// Fold x op 0 -> x // Fold x op 0 -> x
def right_identity_zero: GICombineRule< def right_identity_zero: GICombineRule<
(defs root:$root), (defs root:$root),
(match (wip_match_opcode G_SUB, G_ADD, G_OR, G_XOR, G_SHL, G_ASHR, G_LSHR, (match (wip_match_opcode G_SUB, G_ADD, G_OR, G_XOR, G_SHL, G_ASHR, G_LSHR,
G_PTR_ADD):$root, G_PTR_ADD, G_ROTL, G_ROTR):$root,
[{ return Helper.matchConstantOp(${root}->getOperand(2), 0); }]), [{ return Helper.matchConstantOp(${root}->getOperand(2), 0); }]),
(apply [{ return Helper.replaceSingleDefInstWithOperand(*${root}, 1); }]) (apply [{ return Helper.replaceSingleDefInstWithOperand(*${root}, 1); }])
>; >;
// Fold x op 1 -> x // Fold x op 1 -> x
def right_identity_one: GICombineRule< def right_identity_one: GICombineRule<
(defs root:$root), (defs root:$root),
(match (wip_match_opcode G_MUL):$root, (match (wip_match_opcode G_MUL):$root,
▲ Show 20 Lines • Show All 452 Lines • Show Last 20 Lines

llvm/test/CodeGen/AArch64/GlobalISel/postlegalizercombiner-rotate.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple aarch64 -run-pass=aarch64-postlegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s # RUN: llc -mtriple aarch64 -run-pass=aarch64-postlegalizer-combiner --aarch64postlegalizercombinerhelper-only-enable-rule="rotate_out_of_range" -verify-machineinstrs %s -o - | FileCheck %s
# REQUIRES: asserts
# Check that we simplify the constant rotate amount to be in range. # Check that we simplify the constant rotate amount to be in range.
--- ---
name: rotl name: rotl
alignment: 4 alignment: 4
legalized: true legalized: true
tracksRegLiveness: true tracksRegLiveness: true
liveins: liveins:
▲ Show 20 Lines • Show All 94 Lines • Show Last 20 Lines

llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-trivial-arith.mir

Show First 20 Lines • Show All 319 Lines • ▼ Show 20 Lines bb.1.entry:
; CHECK: %x:_(p0) = COPY $x0 ; CHECK: %x:_(p0) = COPY $x0
; CHECK: $x0 = COPY %x(p0) ; CHECK: $x0 = COPY %x(p0)
; CHECK: RET_ReallyLR implicit $x0 ; CHECK: RET_ReallyLR implicit $x0
%x:_(p0) = COPY $x0 %x:_(p0) = COPY $x0
%cst:_(s64) = G_CONSTANT i64 0 %cst:_(s64) = G_CONSTANT i64 0
%op:_(p0) = G_PTR_ADD %x(p0), %cst %op:_(p0) = G_PTR_ADD %x(p0), %cst
$x0 = COPY %op(p0) $x0 = COPY %op(p0)
RET_ReallyLR implicit $x0 RET_ReallyLR implicit $x0
...
---
name: right_identity_rotl
tracksRegLiveness: true
body: |
bb.0:
liveins: $w0, $w1
; CHECK-LABEL: name: right_identity_rotl
; CHECK: liveins: $w0, $w1
; CHECK: %copy:_(s32) = COPY $w0
; CHECK: $w0 = COPY %copy(s32)
; CHECK: RET_ReallyLR implicit $w0
%copy:_(s32) = COPY $w0
%zero:_(s32) = G_CONSTANT i32 0
%rot:_(s32) = G_ROTL %copy(s32), %zero(s32)
$w0 = COPY %rot(s32)
RET_ReallyLR implicit $w0
...
jroelofsUnsubmitted
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extra ...

jroelofs: extra `...`
...
---
name: right_identity_rotr
tracksRegLiveness: true
body: |
bb.0:
liveins: $w0, $w1
; CHECK-LABEL: name: right_identity_rotr
; CHECK: liveins: $w0, $w1
; CHECK: %copy:_(s32) = COPY $w0
; CHECK: $w0 = COPY %copy(s32)
; CHECK: RET_ReallyLR implicit $w0
%copy:_(s32) = COPY $w0
%zero:_(s32) = G_CONSTANT i32 0
%rot:_(s32) = G_ROTR %copy(s32), %zero(s32)
$w0 = COPY %rot(s32)
RET_ReallyLR implicit $w0
...