[ARM][CMSE] Clear the secure fp-registers when using softfp abi.

[labrinea]

Summary

When expanding the non-secure call instruction we are emiting code to clear the secure floating-point registers only if the targeted architecture has floating-point support. The potential problem is when the source code containing non-secure calls are built with -mfloat-abi=soft but some other part of the system has been built with -mfloat-abi=softfp (soft and softfp are compatible as they use the same procedure calling standard). In this case floating-point registers could leak to non-secure state as the non-secure won't have cleared them assuming no floating-point has been used.

[chill]

Looks reasonable. Could we, please, add a comment which explains why it's correct to emit vlldm/vllsm (e.g. "they behave as NOPs") and various other instrucvtion that access FP regfisters (e.g. "we are passing parameters in FP-regs anyway")?

[labrinea]

Added an assertion for when fpregs are passed or returned, and a comment about vlstm/vlldm being NOP in the absence of FPU.

[chill]

LGTM, cheers!

llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp

ARMExpandPseudo::CMSEClearFPRegsV81(MachineBasicBlock &MBB,
   return MBB;
 }
 
 void ARMExpandPseudo::CMSESaveClearFPRegs(
     MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, DebugLoc &DL,
     const LivePhysRegs &LiveRegs, SmallVectorImpl<unsigned> &ScratchRegs) {
   if (STI->hasV8_1MMainlineOps())
     CMSESaveClearFPRegsV81(MBB, MBBI, DL, LiveRegs);
-  else
+  else if (STI->hasV8MMainlineOps())
     CMSESaveClearFPRegsV8(MBB, MBBI, DL, LiveRegs, ScratchRegs);
 }
 
 // Save and clear FP registers if present
 void ARMExpandPseudo::CMSESaveClearFPRegsV8(
     MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, DebugLoc &DL,
     const LivePhysRegs &LiveRegs, SmallVectorImpl<unsigned> &ScratchRegs) {
-  if (!STI->hasFPRegs())
-    return;
 
   // Store an available register for FPSCR clearing
   assert(!ScratchRegs.empty());
   unsigned SpareReg = ScratchRegs.front();
 
   // save space on stack for VLSTM
   BuildMI(MBB, MBBI, DL, TII->get(ARM::tSUBspi), ARM::SP)
       .addReg(ARM::SP)
if (Op.isReg() && Op.isUse()) {
           NonclearedFPRegs.push_back(Reg);
         }
       }
     }
   }
 
   bool passesFPReg = (!NonclearedFPRegs.empty() || !ClearedFPRegs.empty());
 
-  // Lazy store all fp registers to the stack
+  if (passesFPReg)
+    assert(STI->hasFPRegs() && "Subtarget needs fpregs");
+
+  // Lazy store all fp registers to the stack.
+  // This executes as NOP in the absence of floating-point support.
   MachineInstrBuilder VLSTM = BuildMI(MBB, MBBI, DL, TII->get(ARM::VLSTM))
                                   .addReg(ARM::SP)
                                   .add(predOps(ARMCC::AL));
   for (auto R : {ARM::VPR, ARM::FPSCR, ARM::FPSCR_NZCV, ARM::Q0, ARM::Q1,
                  ARM::Q2, ARM::Q3, ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7})
     VLSTM.addReg(R, RegState::Implicit |
                         (LiveRegs.contains(R) ? 0 : RegState::Undef));
 

 }
 
 // Restore FP registers if present
 void ARMExpandPseudo::CMSERestoreFPRegs(
     MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, DebugLoc &DL,
     SmallVectorImpl<unsigned> &AvailableRegs) {
   if (STI->hasV8_1MMainlineOps())
     CMSERestoreFPRegsV81(MBB, MBBI, DL, AvailableRegs);
-  else
+  else if (STI->hasV8MMainlineOps())
     CMSERestoreFPRegsV8(MBB, MBBI, DL, AvailableRegs);
 }
 
 void ARMExpandPseudo::CMSERestoreFPRegsV8(
     MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, DebugLoc &DL,
     SmallVectorImpl<unsigned> &AvailableRegs) {
-  if (!STI->hasFPRegs())
-    return;
 
   // Use AvailableRegs to store the fp regs
   std::vector<std::tuple<unsigned, unsigned, unsigned>> ClearedFPRegs;
   std::vector<unsigned> NonclearedFPRegs;
   for (const MachineOperand &Op : MBBI->operands()) {
     if (Op.isReg() && Op.isDef()) {
       unsigned Reg = Op.getReg();
       assert(!ARM::DPRRegClass.contains(Reg) ||
if (Op.isReg() && Op.isDef()) {
               .add(predOps(ARMCC::AL));
         } else {
           NonclearedFPRegs.push_back(Reg);
         }
       }
     }
   }
 
+  bool returnsFPReg = (!NonclearedFPRegs.empty() || !ClearedFPRegs.empty());
+
+  if (returnsFPReg)
+    assert(STI->hasFPRegs() && "Subtarget needs fpregs");
+
   // Push FP regs that cannot be restored via normal registers on the stack
   for (unsigned Reg : NonclearedFPRegs) {
     if (ARM::DPR_VFP2RegClass.contains(Reg))
       BuildMI(MBB, MBBI, DL, TII->get(ARM::VSTRD), Reg)
           .addReg(ARM::SP)
           .addImm((Reg - ARM::D0) * 2)
           .add(predOps(ARMCC::AL));
     else if (ARM::SPRRegClass.contains(Reg))
       BuildMI(MBB, MBBI, DL, TII->get(ARM::VSTRS), Reg)
           .addReg(ARM::SP)
           .addImm(Reg - ARM::S0)
           .add(predOps(ARMCC::AL));
   }
 
-  // Lazy load fp regs from stack
+  // Lazy load fp regs from stack.
+  // This executes as NOP in the absence of floating-point support.
   BuildMI(MBB, MBBI, DL, TII->get(ARM::VLLDM))
       .addReg(ARM::SP)
       .add(predOps(ARMCC::AL));
 
   // Restore all FP registers via normal registers
   for (const auto &Regs : ClearedFPRegs) {
     unsigned Reg, SaveReg1, SaveReg2;
     std::tie(Reg, SaveReg1, SaveReg2) = Regs;

llvm/test/CodeGen/ARM/cmse-clear.ll

 ;
 ; CHECK-8M-SOFT-LABEL: ns_call:
 ; CHECK-8M-SOFT:       @ %bb.0: @ %entry
 ; CHECK-8M-SOFT-NEXT:    push {r7, lr}
 ; CHECK-8M-SOFT-NEXT:    mov r1, r0
 ; CHECK-8M-SOFT-NEXT:    movs r0, #10
 ; CHECK-8M-SOFT-NEXT:    push.w {r4, r5, r6, r7, r8, r9, r10, r11}
 ; CHECK-8M-SOFT-NEXT:    bic r1, r1, #1
-; CHECK-8M-SOFT-NEXT:    msr apsr_nzcvqg, r1
+; CHECK-8M-SOFT-NEXT:    sub sp, #136
+; CHECK-8M-SOFT-NEXT:    vlstm sp
 ; CHECK-8M-SOFT-NEXT:    mov r2, r1
 ; CHECK-8M-SOFT-NEXT:    mov r3, r1
 ; CHECK-8M-SOFT-NEXT:    mov r4, r1
 ; CHECK-8M-SOFT-NEXT:    mov r5, r1
 ; CHECK-8M-SOFT-NEXT:    mov r6, r1
 ; CHECK-8M-SOFT-NEXT:    mov r7, r1
 ; CHECK-8M-SOFT-NEXT:    mov r8, r1
 ; CHECK-8M-SOFT-NEXT:    mov r9, r1
 ; CHECK-8M-SOFT-NEXT:    mov r10, r1
 ; CHECK-8M-SOFT-NEXT:    mov r11, r1
 ; CHECK-8M-SOFT-NEXT:    mov r12, r1
+; CHECK-8M-SOFT-NEXT:    msr apsr_nzcvqg, r1
 ; CHECK-8M-SOFT-NEXT:    blxns r1
+; CHECK-8M-SOFT-NEXT:    vlldm sp
+; CHECK-8M-SOFT-NEXT:    add sp, #136
 ; CHECK-8M-SOFT-NEXT:    pop.w {r4, r5, r6, r7, r8, r9, r10, r11}
 ; CHECK-8M-SOFT-NEXT:    pop {r7, pc}
 ;
 ; CHECK-8M-SOFTFP-LABEL: ns_call:
 ; CHECK-8M-SOFTFP:       @ %bb.0: @ %entry
 ; CHECK-8M-SOFTFP-NEXT:    push {r7, lr}
 ; CHECK-8M-SOFTFP-NEXT:    mov r1, r0
 ; CHECK-8M-SOFTFP-NEXT:    movs r0, #10

 ;
 ; CHECK-8M-SOFT-LABEL: ns_tail_call:
 ; CHECK-8M-SOFT:       @ %bb.0: @ %entry
 ; CHECK-8M-SOFT-NEXT:    push {r7, lr}
 ; CHECK-8M-SOFT-NEXT:    mov r1, r0
 ; CHECK-8M-SOFT-NEXT:    movs r0, #10
 ; CHECK-8M-SOFT-NEXT:    push.w {r4, r5, r6, r7, r8, r9, r10, r11}
 ; CHECK-8M-SOFT-NEXT:    bic r1, r1, #1
-; CHECK-8M-SOFT-NEXT:    msr apsr_nzcvqg, r1
+; CHECK-8M-SOFT-NEXT:    sub sp, #136
+; CHECK-8M-SOFT-NEXT:    vlstm sp
 ; CHECK-8M-SOFT-NEXT:    mov r2, r1
 ; CHECK-8M-SOFT-NEXT:    mov r3, r1
 ; CHECK-8M-SOFT-NEXT:    mov r4, r1
 ; CHECK-8M-SOFT-NEXT:    mov r5, r1
 ; CHECK-8M-SOFT-NEXT:    mov r6, r1
 ; CHECK-8M-SOFT-NEXT:    mov r7, r1
 ; CHECK-8M-SOFT-NEXT:    mov r8, r1
 ; CHECK-8M-SOFT-NEXT:    mov r9, r1
 ; CHECK-8M-SOFT-NEXT:    mov r10, r1
 ; CHECK-8M-SOFT-NEXT:    mov r11, r1
 ; CHECK-8M-SOFT-NEXT:    mov r12, r1
+; CHECK-8M-SOFT-NEXT:    msr apsr_nzcvqg, r1
 ; CHECK-8M-SOFT-NEXT:    blxns r1
+; CHECK-8M-SOFT-NEXT:    vlldm sp
+; CHECK-8M-SOFT-NEXT:    add sp, #136
 ; CHECK-8M-SOFT-NEXT:    pop.w {r4, r5, r6, r7, r8, r9, r10, r11}
 ; CHECK-8M-SOFT-NEXT:    pop {r7, pc}
 ;
 ; CHECK-8M-SOFTFP-LABEL: ns_tail_call:
 ; CHECK-8M-SOFTFP:       @ %bb.0: @ %entry
 ; CHECK-8M-SOFTFP-NEXT:    push {r7, lr}
 ; CHECK-8M-SOFTFP-NEXT:    mov r1, r0
 ; CHECK-8M-SOFTFP-NEXT:    movs r0, #10

 ; CHECK-8M-SOFT-NEXT:    mov r4, r0
 ; CHECK-8M-SOFT-NEXT:    mov r12, r3
 ; CHECK-8M-SOFT-NEXT:    mov r0, r1
 ; CHECK-8M-SOFT-NEXT:    mov r1, r2
 ; CHECK-8M-SOFT-NEXT:    ldr r3, [sp, #8]
 ; CHECK-8M-SOFT-NEXT:    mov r2, r12
 ; CHECK-8M-SOFT-NEXT:    push.w {r4, r5, r6, r7, r8, r9, r10, r11}
 ; CHECK-8M-SOFT-NEXT:    bic r4, r4, #1
-; CHECK-8M-SOFT-NEXT:    msr apsr_nzcvqg, r4
+; CHECK-8M-SOFT-NEXT:    sub sp, #136
+; CHECK-8M-SOFT-NEXT:    vlstm sp
 ; CHECK-8M-SOFT-NEXT:    mov r5, r4
 ; CHECK-8M-SOFT-NEXT:    mov r6, r4
 ; CHECK-8M-SOFT-NEXT:    mov r7, r4
 ; CHECK-8M-SOFT-NEXT:    mov r8, r4
 ; CHECK-8M-SOFT-NEXT:    mov r9, r4
 ; CHECK-8M-SOFT-NEXT:    mov r10, r4
 ; CHECK-8M-SOFT-NEXT:    mov r11, r4
 ; CHECK-8M-SOFT-NEXT:    mov r12, r4
+; CHECK-8M-SOFT-NEXT:    msr apsr_nzcvqg, r4
 ; CHECK-8M-SOFT-NEXT:    blxns r4
+; CHECK-8M-SOFT-NEXT:    vlldm sp
+; CHECK-8M-SOFT-NEXT:    add sp, #136
 ; CHECK-8M-SOFT-NEXT:    pop.w {r4, r5, r6, r7, r8, r9, r10, r11}
 ; CHECK-8M-SOFT-NEXT:    mov r0, r4
 ; CHECK-8M-SOFT-NEXT:    pop {r4, pc}
 ;
 ; CHECK-8M-SOFTFP-LABEL: ns_tail_call_many_args:
 ; CHECK-8M-SOFTFP:       @ %bb.0:
 ; CHECK-8M-SOFTFP-NEXT:    push {r4, lr}
 ; CHECK-8M-SOFTFP-NEXT:    mov r4, r0

 ; CHECK-8B-NEXT:    pop {r4, r5, r6, r7}
 ; CHECK-8B-NEXT:    pop {r7, pc}
 ;
 ; CHECK-8M-SOFT-LABEL: ns_call_void:
 ; CHECK-8M-SOFT:       @ %bb.0: @ %entry
 ; CHECK-8M-SOFT-NEXT:    push {r7, lr}
 ; CHECK-8M-SOFT-NEXT:    push.w {r4, r5, r6, r7, r8, r9, r10, r11}
 ; CHECK-8M-SOFT-NEXT:    bic r1, r1, #1
-; CHECK-8M-SOFT-NEXT:    msr apsr_nzcvqg, r1
+; CHECK-8M-SOFT-NEXT:    sub sp, #136
+; CHECK-8M-SOFT-NEXT:    vlstm sp
 ; CHECK-8M-SOFT-NEXT:    mov r0, r1
 ; CHECK-8M-SOFT-NEXT:    mov r2, r1
 ; CHECK-8M-SOFT-NEXT:    mov r3, r1
 ; CHECK-8M-SOFT-NEXT:    mov r4, r1
 ; CHECK-8M-SOFT-NEXT:    mov r5, r1
 ; CHECK-8M-SOFT-NEXT:    mov r6, r1
 ; CHECK-8M-SOFT-NEXT:    mov r7, r1
 ; CHECK-8M-SOFT-NEXT:    mov r8, r1
 ; CHECK-8M-SOFT-NEXT:    mov r9, r1
 ; CHECK-8M-SOFT-NEXT:    mov r10, r1
 ; CHECK-8M-SOFT-NEXT:    mov r11, r1
 ; CHECK-8M-SOFT-NEXT:    mov r12, r1
+; CHECK-8M-SOFT-NEXT:    msr apsr_nzcvqg, r1
 ; CHECK-8M-SOFT-NEXT:    blxns r1
+; CHECK-8M-SOFT-NEXT:    vlldm sp
+; CHECK-8M-SOFT-NEXT:    add sp, #136
 ; CHECK-8M-SOFT-NEXT:    pop.w {r4, r5, r6, r7, r8, r9, r10, r11}
 ; CHECK-8M-SOFT-NEXT:    pop {r7, pc}
 ;
 ; CHECK-8M-SOFTFP-LABEL: ns_call_void:
 ; CHECK-8M-SOFTFP:       @ %bb.0: @ %entry
 ; CHECK-8M-SOFTFP-NEXT:    push {r7, lr}
 ; CHECK-8M-SOFTFP-NEXT:    push.w {r4, r5, r6, r7, r8, r9, r10, r11}
 ; CHECK-8M-SOFTFP-NEXT:    bic r1, r1, #1

llvm/test/CodeGen/ARM/cmse.ll

 ; CHECK-8B-NEXT:    msr apsr, lr
 ; CHECK-8B-NEXT:    bxns lr
 ;
 ; CHECK-8M-LABEL: func1:
 ; CHECK-8M:       @ %bb.0: @ %entry
 ; CHECK-8M-NEXT:    push {r7, lr}
 ; CHECK-8M-NEXT:    push.w {r4, r5, r6, r7, r8, r9, r10, r11}
 ; CHECK-8M-NEXT:    bic r0, r0, #1
-; CHECK-8M-NEXT:    msr apsr_nzcvq, r0
+; CHECK-8M-NEXT:    sub sp, #136
+; CHECK-8M-NEXT:    vlstm sp
 ; CHECK-8M-NEXT:    mov r1, r0
 ; CHECK-8M-NEXT:    mov r2, r0
 ; CHECK-8M-NEXT:    mov r3, r0
 ; CHECK-8M-NEXT:    mov r4, r0
 ; CHECK-8M-NEXT:    mov r5, r0
 ; CHECK-8M-NEXT:    mov r6, r0
 ; CHECK-8M-NEXT:    mov r7, r0
 ; CHECK-8M-NEXT:    mov r8, r0
 ; CHECK-8M-NEXT:    mov r9, r0
 ; CHECK-8M-NEXT:    mov r10, r0
 ; CHECK-8M-NEXT:    mov r11, r0
 ; CHECK-8M-NEXT:    mov r12, r0
+; CHECK-8M-NEXT:    msr apsr_nzcvq, r0
 ; CHECK-8M-NEXT:    blxns r0
+; CHECK-8M-NEXT:    vlldm sp
+; CHECK-8M-NEXT:    add sp, #136
 ; CHECK-8M-NEXT:    pop.w {r4, r5, r6, r7, r8, r9, r10, r11}
 ; CHECK-8M-NEXT:    pop.w {r7, lr}
 ; CHECK-8M-NEXT:    mov r0, lr
 ; CHECK-8M-NEXT:    mov r1, lr
 ; CHECK-8M-NEXT:    mov r2, lr
 ; CHECK-8M-NEXT:    mov r3, lr
 ; CHECK-8M-NEXT:    mov r12, lr
 ; CHECK-8M-NEXT:    msr apsr_nzcvq, lr

 ; CHECK-8B-NEXT:    pop {r4, r5, r6, r7}
 ; CHECK-8B-NEXT:    pop {r7, pc}
 ;
 ; CHECK-8M-LABEL: func2:
 ; CHECK-8M:       @ %bb.0: @ %entry
 ; CHECK-8M-NEXT:    push {r7, lr}
 ; CHECK-8M-NEXT:    push.w {r4, r5, r6, r7, r8, r9, r10, r11}
 ; CHECK-8M-NEXT:    bic r0, r0, #1
-; CHECK-8M-NEXT:    msr apsr_nzcvq, r0
+; CHECK-8M-NEXT:    sub sp, #136
+; CHECK-8M-NEXT:    vlstm sp
 ; CHECK-8M-NEXT:    mov r1, r0
 ; CHECK-8M-NEXT:    mov r2, r0
 ; CHECK-8M-NEXT:    mov r3, r0
 ; CHECK-8M-NEXT:    mov r4, r0
 ; CHECK-8M-NEXT:    mov r5, r0
 ; CHECK-8M-NEXT:    mov r6, r0
 ; CHECK-8M-NEXT:    mov r7, r0
 ; CHECK-8M-NEXT:    mov r8, r0
 ; CHECK-8M-NEXT:    mov r9, r0
 ; CHECK-8M-NEXT:    mov r10, r0
 ; CHECK-8M-NEXT:    mov r11, r0
 ; CHECK-8M-NEXT:    mov r12, r0
+; CHECK-8M-NEXT:    msr apsr_nzcvq, r0
 ; CHECK-8M-NEXT:    blxns r0
+; CHECK-8M-NEXT:    vlldm sp
+; CHECK-8M-NEXT:    add sp, #136
 ; CHECK-8M-NEXT:    pop.w {r4, r5, r6, r7, r8, r9, r10, r11}
 ; CHECK-8M-NEXT:    pop {r7, pc}
 ;
 ; CHECK-81M-LABEL: func2:
 ; CHECK-81M:       @ %bb.0: @ %entry
 ; CHECK-81M-NEXT:    push {r7, lr}
 ; CHECK-81M-NEXT:    push.w {r4, r5, r6, r7, r8, r9, r10, r11}
 ; CHECK-81M-NEXT:    bic r0, r0, #1