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[AArch64] Fold an sqadd of a sqdmull at lane 0 into an sqdmlal
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Authored by samtebbs on Aug 31 2021, 8:36 AM.

Details

Summary

This patch folds a sqadd (i32, vector_extract (sqdmull v4i16, v4i16, 0)) into a sqdmlal. We already generate an sqdmlal for lanes greater than 0, so this patch emits an sqdmlal of the same format but for a lane of 0, and is necessary as the existing pattern doesn't match.

Diff Detail

Event Timeline

samtebbs created this revision.Aug 31 2021, 8:36 AM
samtebbs requested review of this revision.Aug 31 2021, 8:36 AM
Herald added a project: Restricted Project. · View Herald TranscriptAug 31 2021, 8:36 AM
dmgreen added inline comments.Sep 1 2021, 3:11 PM
llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
1205

There should probably be other types to this? Not just v4i16.
And it doesn't look like it should be in the SVE file.
From looking around, it appears most of the other patterns are in SIMDIndexedLongSQDMLXSDTied.

But if this is from a scalar intrinsic, should it be producing a scalar sqdmlal?

samtebbs abandoned this revision.May 25 2022, 7:56 AM
Herald added a project: Restricted Project. · View Herald TranscriptMay 25 2022, 7:56 AM