Fix typo in comments

llvm/include/llvm/DebugInfo/CodeView/CodeViewRegisters.def

 #endif // defined(CV_REGISTERS_ALL) || defined(CV_REGISTERS_X86)
 
 #if defined(CV_REGISTERS_ALL) || defined(CV_REGISTERS_ARM)
 
 // ARM registers
 
 CV_REGISTER(ARM_NOREG, 0)
 
-// General purpose 32-bit integer regisers
+// General purpose 32-bit integer registers
 
 CV_REGISTER(ARM_R0, 10)
 CV_REGISTER(ARM_R1, 11)
 CV_REGISTER(ARM_R2, 12)
 CV_REGISTER(ARM_R3, 13)
 CV_REGISTER(ARM_R4, 14)
 CV_REGISTER(ARM_R5, 15)
 CV_REGISTER(ARM_R6, 16)

llvm/include/llvm/Target/TargetOptions.h

public:
     /// NoSignedZerosFPMath - This flag is enabled when the
     /// -enable-no-signed-zeros-fp-math is specified on the command line. This
     /// specifies that optimizations are allowed to treat the sign of a zero
     /// argument or result as insignificant.
     unsigned NoSignedZerosFPMath : 1;
 
     /// EnableAIXExtendedAltivecABI - This flag returns true when -vec-extabi is
     /// specified. The code generator is then able to use both volatile and
-    /// nonvolitle vector regisers. When false, the code generator only uses
+    /// nonvolitle vector registers. When false, the code generator only uses
     /// volatile vector registers which is the default setting on AIX.
     unsigned EnableAIXExtendedAltivecABI : 1;
 
     /// HonorSignDependentRoundingFPMath - This returns true when the
     /// -enable-sign-dependent-rounding-fp-math is specified.  If this returns
     /// false (the default), the code generator is allowed to assume that the
     /// rounding behavior is the default (round-to-zero for all floating point
     /// to integer conversions, and round-to-nearest for all other arithmetic

llvm/lib/Target/PowerPC/PPCInstrInfo.cpp

if (ACC - PPC::ACC0 != UACC - PPC::UACC0) {
       // FIXME: This can easily be improved to look up to the top of the MBB
       // to see if the inputs are XXLOR's. If they are and SrcReg is killed,
       // we can just re-target any such XXLOR's to DstVSR + offset.
       for (int VecNo = 0; VecNo < 4; VecNo++)
         BuildMI(MBB, MI, DL, get(PPC::XXLOR), DstVSR + VecNo)
             .addReg(SrcVSR + VecNo)
             .addReg(SrcVSR + VecNo);
     }
-    // BUILD_UACC is expanded to 4 copies of the underlying vsx regisers.
+    // BUILD_UACC is expanded to 4 copies of the underlying vsx registers.
     // So after building the 4 copies, we can replace the BUILD_UACC instruction
     // with a NOP.
     LLVM_FALLTHROUGH;
   }
   case PPC::KILL_PAIR: {
     MI.setDesc(get(PPC::UNENCODED_NOP));
     MI.RemoveOperand(1);
     MI.RemoveOperand(0);