[TableGen] Allow target specific flags for RegisterClass

[cdevadas]

Summary

Analogous to the TSFlags for machine instructions, this
patch introduces a variable for target specific flags in
TargetRegisterClass that acts as configurable bitfields
for register classes.

[craig.topper]

Can you provide an example of why this is a useful thing to have?

[cdevadas]

In D108767#2967495, @craig.topper wrote:

Can you provide an example of why this is a useful thing to have?

For AMDGPU we have different vector registers (VGPRs and AGPRs). There are multiple register classes for them individually and now a superset that combines both A & V registers (AV_32RegClass, for instance).
Currently, the isVGPR() and isAGPR() helper functions that query a specific register class isn't efficient. They are quite slow.
Having the TSFlags and a single bit for each vector register type will make the query just a quick bitwise operation.

[rampitec]

In D108767#2967564, @cdevadas wrote:

In D108767#2967495, @craig.topper wrote:

Can you provide an example of why this is a useful thing to have?

For AMDGPU we have different vector registers (VGPRs and AGPRs). There are multiple register classes for them individually and now a superset that combines both A & V registers (AV_32RegClass, for instance).
Currently, the isVGPR() and isAGPR() helper functions that query a specific register class isn't efficient. They are quite slow.
Having the TSFlags and a single bit for each vector register type will make the query just a quick bitwise operation.

That would be a nice speedup. The change looks good at least to me.

[cdevadas]

Here is a use case for RC TSFlags D108815

[cdevadas]

Ping

[craig.topper]

LGTM

llvm/include/llvm/CodeGen/TargetRegisterInfo.h

public:
   // Instance variables filled by tablegen, do not use!
   const MCRegisterClass *MC;
   const uint32_t *SubClassMask;
   const uint16_t *SuperRegIndices;
   const LaneBitmask LaneMask;
   /// Classes with a higher priority value are assigned first by register
   /// allocators using a greedy heuristic. The value is in the range [0,63].
   const uint8_t AllocationPriority;
+  /// Configurable target specific flags.
+  const uint8_t TSFlags;
   /// Whether the class supports two (or more) disjunct subregister indices.
   const bool HasDisjunctSubRegs;
   /// Whether a combination of subregisters can cover every register in the
   /// class. See also the CoveredBySubRegs description in Target.td.
   const bool CoveredBySubRegs;
   const sc_iterator SuperClasses;
   ArrayRef<MCPhysReg> (*OrderFunc)(const MachineFunction&);
 

llvm/include/llvm/Target/Target.td

class RegisterClass<string namespace, list<ValueType> regTypes, int alignment,
   string DiagnosticType = "";
 
   // A diagnostic message to emit when an invalid value is provided for this
   // register class when it is being used an an assembly operand. If this is
   // non-empty, an anonymous diagnostic type enum value will be generated, and
   // the assembly matcher will provide a function to map from diagnostic types
   // to message strings.
   string DiagnosticString = "";
+
+  // Target-specific flags. This becomes the TSFlags field in TargetRegisterClass.
+  bits<8> TSFlags = 0;
 }
 
 // The memberList in a RegisterClass is a dag of set operations. TableGen
 // evaluates these set operations and expand them into register lists. These
 // are the most common operation, see test/TableGen/SetTheory.td for more
 // examples of what is possible:
 //
 // (add R0, R1, R2) - Set Union. Each argument can be an individual register, a

llvm/test/TableGen/RegisterInfoEmitter-tsflags.td

+// RUN: llvm-tblgen -gen-register-info -I %p/../../include -I %p/Common %s | FileCheck %s
+
+// Configure and test TSFlags for a target.
+include "llvm/Target/Target.td"
+
+let Namespace = "MyTarget" in {
+  def R : Register<"r">;
+  def D : Register<"d">;
+  def S : Register<"s">;
+}
+
+class MyClass <int size, list<ValueType> types, dag regList>
+  : RegisterClass <"MyTarget", types, size, regList> {
+  // Define the target bitfields.
+  field bit A = 0;
+  field bits<2> B = 0;
+
+  // Associate the defined bitfields to unique bit positions in TSFlags.
+  let TSFlags{0} = A;
+  let TSFlags{2-1} = B;
+}
+
+// Default value for TSFlags.
+def MyRegs : MyClass<32, [i32], (add R)>;
+
+def SRegs : MyClass<32, [i32], (add S)> {
+  let A = 1;
+}
+
+def DRegs : MyClass<32, [i32], (add D)>{
+  let B = 3;
+}
+
+def SDRegs : MyClass<32, [i32], (add D, S)>{
+  let A = 1;
+  let B = 3;
+}
+
+def MyTarget : Target;
+
+// CHECK:  extern const TargetRegisterClass SDRegsRegClass = {
+// CHECK:  0x07, /* TSFlags */
+// CHECK:  extern const TargetRegisterClass DRegsRegClass = {
+// CHECK:  0x06, /* TSFlags */
+// CHECK:  extern const TargetRegisterClass MyRegsRegClass = {
+// CHECK:  0x00, /* TSFlags */
+// CHECK:  extern const TargetRegisterClass SRegsRegClass = {
+// CHECK:  0x01, /* TSFlags */

llvm/utils/TableGen/CodeGenRegisters.h

public:
     unsigned EnumValue;
     StringRef Namespace;
     SmallVector<ValueTypeByHwMode, 4> VTs;
     RegSizeInfoByHwMode RSI;
     int CopyCost;
     bool Allocatable;
     StringRef AltOrderSelect;
     uint8_t AllocationPriority;
+    uint8_t TSFlags;
     /// Contains the combination of the lane masks of all subregisters.
     LaneBitmask LaneMask;
     /// True if there are at least 2 subregisters which do not interfere.
     bool HasDisjunctSubRegs;
     bool CoveredBySubRegs;
     /// A register class is artificial if all its members are artificial.
     bool Artificial;
     /// Generate register pressure set for this register class and any class

llvm/utils/TableGen/CodeGenRegisters.cpp

 
 static void sortAndUniqueRegisters(CodeGenRegister::Vec &M) {
   llvm::sort(M, deref<std::less<>>());
   M.erase(std::unique(M.begin(), M.end(), deref<std::equal_to<>>()), M.end());
 }
 
 CodeGenRegisterClass::CodeGenRegisterClass(CodeGenRegBank &RegBank, Record *R)
     : TheDef(R), Name(std::string(R->getName())),
-      TopoSigs(RegBank.getNumTopoSigs()), EnumValue(-1) {
+      TopoSigs(RegBank.getNumTopoSigs()), EnumValue(-1), TSFlags(0) {
   GeneratePressureSet = R->getValueAsBit("GeneratePressureSet");
   std::vector<Record*> TypeList = R->getValueAsListOfDefs("RegTypes");
   if (TypeList.empty())
     PrintFatalError(R->getLoc(), "RegTypes list must not be empty!");
   for (unsigned i = 0, e = TypeList.size(); i != e; ++i) {
     Record *Type = TypeList[i];
     if (!Type->isSubClassOf("ValueType"))
       PrintFatalError(R->getLoc(),
CodeGenRegisterClass::CodeGenRegisterClass(CodeGenRegBank &RegBank, Record *R)
 
   CopyCost = R->getValueAsInt("CopyCost");
   Allocatable = R->getValueAsBit("isAllocatable");
   AltOrderSelect = R->getValueAsString("AltOrderSelect");
   int AllocationPriority = R->getValueAsInt("AllocationPriority");
   if (AllocationPriority < 0 || AllocationPriority > 63)
     PrintFatalError(R->getLoc(), "AllocationPriority out of range [0,63]");
   this->AllocationPriority = AllocationPriority;
+
+  BitsInit *TSF = R->getValueAsBitsInit("TSFlags");
+  for (unsigned I = 0, E = TSF->getNumBits(); I != E; ++I) {
+    BitInit *Bit = cast<BitInit>(TSF->getBit(I));
+    TSFlags |= uint8_t(Bit->getValue()) << I;
+  }
 }
 
 // Create an inferred register class that was missing from the .td files.
 // Most properties will be inherited from the closest super-class after the
 // class structure has been computed.
 CodeGenRegisterClass::CodeGenRegisterClass(CodeGenRegBank &RegBank,
                                            StringRef Name, Key Props)
     : Members(*Props.Members), TheDef(nullptr), Name(std::string(Name)),
       TopoSigs(RegBank.getNumTopoSigs()), EnumValue(-1), RSI(Props.RSI),
-      CopyCost(0), Allocatable(true), AllocationPriority(0) {
+      CopyCost(0), Allocatable(true), AllocationPriority(0), TSFlags(0) {
   Artificial = true;
   GeneratePressureSet = false;
   for (const auto R : Members) {
     TopoSigs.set(R->getTopoSig());
     Artificial &= R->Artificial;
   }
 }
 
void CodeGenRegisterClass::inheritProperties(CodeGenRegBank &RegBank) {
   VTs = Super.VTs;
   CopyCost = Super.CopyCost;
   // Check for allocatable superclasses.
   Allocatable = any_of(SuperClasses, [&](const CodeGenRegisterClass *S) {
     return S->Allocatable;
   });
   AltOrderSelect = Super.AltOrderSelect;
   AllocationPriority = Super.AllocationPriority;
+  TSFlags = Super.TSFlags;
   GeneratePressureSet |= Super.GeneratePressureSet;
 
   // Copy all allocation orders, filter out foreign registers from the larger
   // super-class.
   Orders.resize(Super.Orders.size());
   for (unsigned i = 0, ie = Super.Orders.size(); i != ie; ++i)
     for (unsigned j = 0, je = Super.Orders[i].size(); j != je; ++j)
       if (contains(RegBank.getReg(Super.Orders[i][j])))

llvm/utils/TableGen/RegisterInfoEmitter.cpp

if (!RegisterClasses.empty()) {
     for (const auto &RC : RegisterClasses) {
       OS << "  extern const TargetRegisterClass " << RC.getName()
          << "RegClass = {\n    " << '&' << Target.getName()
          << "MCRegisterClasses[" << RC.getName() << "RegClassID],\n    "
          << RC.getName() << "SubClassMask,\n    SuperRegIdxSeqs + "
          << SuperRegIdxSeqs.get(SuperRegIdxLists[RC.EnumValue]) << ",\n    ";
       printMask(OS, RC.LaneMask);
       OS << ",\n    " << (unsigned)RC.AllocationPriority << ",\n    "
+         << format("0x%02x", RC.TSFlags) << ", /* TSFlags */\n    "
          << (RC.HasDisjunctSubRegs?"true":"false")
          << ", /* HasDisjunctSubRegs */\n    "
          << (RC.CoveredBySubRegs?"true":"false")
          << ", /* CoveredBySubRegs */\n    ";
       if (RC.getSuperClasses().empty())
         OS << "NullRegClasses,\n    ";
       else
         OS << RC.getName() << "Superclasses,\n    ";