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Differential D108664

[asan] Re-land "Implemented intrinsic for the custom calling convention similar used by HWASan for X86." with a fix.
AbandonedPublic

Authored by kstoimenov on Aug 24 2021, 2:24 PM.

Details

Reviewers
vitalybuka
Summary

This is a re-land of D107850 after fixing 2 issues:

  • link problem was fixed by D108662
  • Bazel build failure by using older syntax for AsanMemaccessTuple

Diff Detail

Event Timeline

kstoimenov created this revision.Aug 24 2021, 2:24 PM
Herald added subscribers: pengfei, hiraditya. · View Herald TranscriptAug 24 2021, 2:24 PM
kstoimenov requested review of this revision.Aug 24 2021, 2:24 PM
Herald added a project: Restricted Project. · View Herald TranscriptAug 24 2021, 2:24 PM
Herald added subscribers: llvm-commits, jdoerfert. · View Herald Transcript
kstoimenov added a child revision: D107850: [asan] Implemented intrinsic for the custom calling convention similar used by HWASan for X86..Aug 24 2021, 2:26 PM
kstoimenov removed a child revision: D107850: [asan] Implemented intrinsic for the custom calling convention similar used by HWASan for X86..
kstoimenov added a parent revision: D107850: [asan] Implemented intrinsic for the custom calling convention similar used by HWASan for X86..
kstoimenov retitled this revision from [asan] Roll D107850 forward with a fix: Implemented intrinsic for the custom calling convention similar used by HWASan for X86. to [asan] Re-land "Implemented intrinsic for the custom calling convention similar used by HWASan for X86." with a fix. .Aug 24 2021, 2:39 PM
kstoimenov edited the summary of this revision. (Show Details)
kstoimenov added a reviewer: vitalybuka.
kstoimenov added a subscriber: myhsu.
Harbormaster completed remote builds in B121049: Diff 368468.Aug 24 2021, 2:58 PM
kstoimenov updated this revision to Diff 368490.Aug 24 2021, 4:06 PM
kstoimenov retitled this revision from [asan] Re-land "Implemented intrinsic for the custom calling convention similar used by HWASan for X86." with a fix. to [asan] Re-land "Implemented intrinsic for the custom calling convention similar used by HWASan for X86." with a fix..

Update after pull.

Harbormaster completed remote builds in B121064: Diff 368490.Aug 24 2021, 4:34 PM
vitalybuka added a comment.EditedAug 24 2021, 5:28 PM

usually after revert we reopen existing review (also if you revers patches for someone else)
Then
arc diff HEAD^ --update D107850

kstoimenov abandoned this revision.Aug 24 2021, 5:34 PM
kstoimenov removed a parent revision: D107850: [asan] Implemented intrinsic for the custom calling convention similar used by HWASan for X86..Aug 25 2021, 9:14 AM

Revision Contents

PathSize
llvm/
include/
llvm/
IR/
7 lines
Transforms/
Instrumentation/
10 lines
lib/
Target/
X86/
18 lines
2 lines
13 lines
243 lines
6 lines
Transforms/
Instrumentation/
23 lines
test/
CodeGen/
X86/
243 lines
253 lines

Diff 368490

llvm/include/llvm/IR/Intrinsics.td

Show First 20 Lines • Show All 1,333 Lines • ▼ Show 20 Lines
// This instruction has no actual effect, though it is treated by the optimizer // This instruction has no actual effect, though it is treated by the optimizer
// has having opaque side effects. This may be inserted into loops to ensure // has having opaque side effects. This may be inserted into loops to ensure
// that they are not removed even if they turn out to be empty, for languages // that they are not removed even if they turn out to be empty, for languages
// which specify that infinite loops must be preserved. // which specify that infinite loops must be preserved.
def int_sideeffect : DefaultAttrsIntrinsic<[], [], [IntrInaccessibleMemOnly, IntrWillReturn]>; def int_sideeffect : DefaultAttrsIntrinsic<[], [], [IntrInaccessibleMemOnly, IntrWillReturn]>;
// The pseudoprobe intrinsic works as a place holder to the block it probes. // The pseudoprobe intrinsic works as a place holder to the block it probes.
// Like the sideeffect intrinsic defined above, this intrinsic is treated by the // Like the sideeffect intrinsic defined above, this intrinsic is treated by the
// optimizer as having opaque side effects so that it won't be get rid of or moved // optimizer as having opaque side effects so that it won't be get rid of or moved
// out of the block it probes. // out of the block it probes.
def int_pseudoprobe : Intrinsic<[], [llvm_i64_ty, llvm_i64_ty, llvm_i32_ty, llvm_i64_ty], def int_pseudoprobe : Intrinsic<[], [llvm_i64_ty, llvm_i64_ty, llvm_i32_ty, llvm_i64_ty],
[IntrInaccessibleMemOnly, IntrWillReturn]>; [IntrInaccessibleMemOnly, IntrWillReturn]>;
// Arithmetic fence intrinsic. // Arithmetic fence intrinsic.
def int_arithmetic_fence : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>], [IntrNoMem]>; def int_arithmetic_fence : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>], [IntrNoMem]>;
// Intrinsics to support half precision floating point format // Intrinsics to support half precision floating point format
▲ Show 20 Lines • Show All 280 Lines • ▼ Show 20 Lines
// Create a branch funnel that implements an indirect call to a limited set of // Create a branch funnel that implements an indirect call to a limited set of
// callees. This needs to be a musttail call. // callees. This needs to be a musttail call.
def int_icall_branch_funnel : DefaultAttrsIntrinsic<[], [llvm_vararg_ty], []>; def int_icall_branch_funnel : DefaultAttrsIntrinsic<[], [llvm_vararg_ty], []>;
def int_load_relative: DefaultAttrsIntrinsic<[llvm_ptr_ty], [llvm_ptr_ty, llvm_anyint_ty], def int_load_relative: DefaultAttrsIntrinsic<[llvm_ptr_ty], [llvm_ptr_ty, llvm_anyint_ty],
[IntrReadMem, IntrArgMemOnly]>; [IntrReadMem, IntrArgMemOnly]>;
def int_asan_check_memaccess :
Intrinsic<[],[llvm_ptr_ty, llvm_i32_ty], [ImmArg<ArgIndex<1>>]>;
def int_hwasan_check_memaccess : def int_hwasan_check_memaccess :
Intrinsic<[], [llvm_ptr_ty, llvm_ptr_ty, llvm_i32_ty], Intrinsic<[], [llvm_ptr_ty, llvm_ptr_ty, llvm_i32_ty],
[ImmArg<ArgIndex<2>>]>; [ImmArg<ArgIndex<2>>]>;
def int_hwasan_check_memaccess_shortgranules : def int_hwasan_check_memaccess_shortgranules :
Intrinsic<[], [llvm_ptr_ty, llvm_ptr_ty, llvm_i32_ty], Intrinsic<[], [llvm_ptr_ty, llvm_ptr_ty, llvm_i32_ty],
[ImmArg<ArgIndex<2>>]>; [ImmArg<ArgIndex<2>>]>;
// Xray intrinsics // Xray intrinsics
▲ Show 20 Lines • Show All 215 Lines • Show Last 20 Lines

llvm/include/llvm/Transforms/Instrumentation/AddressSanitizer.h

Show First 20 Lines • Show All 149 Lines • ▼ Show 20 LinesFunctionPass *createAddressSanitizerFunctionPass(
bool UseAfterScope = false, bool UseAfterScope = false,
AsanDetectStackUseAfterReturnMode UseAfterReturn = AsanDetectStackUseAfterReturnMode UseAfterReturn =
AsanDetectStackUseAfterReturnMode::Runtime); AsanDetectStackUseAfterReturnMode::Runtime);
ModulePass *createModuleAddressSanitizerLegacyPassPass( ModulePass *createModuleAddressSanitizerLegacyPassPass(
bool CompileKernel = false, bool Recover = false, bool UseGlobalsGC = true, bool CompileKernel = false, bool Recover = false, bool UseGlobalsGC = true,
bool UseOdrIndicator = true, bool UseOdrIndicator = true,
AsanDtorKind DestructorKind = AsanDtorKind::Global); AsanDtorKind DestructorKind = AsanDtorKind::Global);
struct ASanAccessInfo {
const int32_t Packed;
const uint8_t AccessSizeIndex;
const bool IsWrite;
const bool CompileKernel;
explicit ASanAccessInfo(int32_t Packed);
ASanAccessInfo(bool IsWrite, bool CompileKernel, uint8_t AccessSizeIndex);
};
} // namespace llvm } // namespace llvm
#endif #endif

llvm/lib/Target/X86/X86AsmPrinter.h

Show All 17 Linesnamespace {
class X86MCInstLower; class X86MCInstLower;
} }
namespace llvm { namespace llvm {
class MCCodeEmitter; class MCCodeEmitter;
class MCStreamer; class MCStreamer;
class X86Subtarget; class X86Subtarget;
class TargetMachine; class TargetMachine;
struct ASanAccessInfo;
class LLVM_LIBRARY_VISIBILITY X86AsmPrinter : public AsmPrinter { class LLVM_LIBRARY_VISIBILITY X86AsmPrinter : public AsmPrinter {
const X86Subtarget *Subtarget = nullptr; const X86Subtarget *Subtarget = nullptr;
StackMaps SM; StackMaps SM;
FaultMaps FM; FaultMaps FM;
std::unique_ptr<MCCodeEmitter> CodeEmitter; std::unique_ptr<MCCodeEmitter> CodeEmitter;
bool EmitFPOData = false; bool EmitFPOData = false;
bool NeedsRetpoline = false; bool NeedsRetpoline = false;
▲ Show 20 Lines • Show All 59 Lines • ▼ Show 20 Linesclass LLVM_LIBRARY_VISIBILITY X86AsmPrinter : public AsmPrinter {
void LowerPATCHABLE_RET(const MachineInstr &MI, X86MCInstLower &MCIL); void LowerPATCHABLE_RET(const MachineInstr &MI, X86MCInstLower &MCIL);
void LowerPATCHABLE_TAIL_CALL(const MachineInstr &MI, X86MCInstLower &MCIL); void LowerPATCHABLE_TAIL_CALL(const MachineInstr &MI, X86MCInstLower &MCIL);
void LowerPATCHABLE_EVENT_CALL(const MachineInstr &MI, X86MCInstLower &MCIL); void LowerPATCHABLE_EVENT_CALL(const MachineInstr &MI, X86MCInstLower &MCIL);
void LowerPATCHABLE_TYPED_EVENT_CALL(const MachineInstr &MI, void LowerPATCHABLE_TYPED_EVENT_CALL(const MachineInstr &MI,
X86MCInstLower &MCIL); X86MCInstLower &MCIL);
void LowerFENTRY_CALL(const MachineInstr &MI, X86MCInstLower &MCIL); void LowerFENTRY_CALL(const MachineInstr &MI, X86MCInstLower &MCIL);
// Address sanitizer specific lowering for X86.
void LowerASAN_CHECK_MEMACCESS(const MachineInstr &MI);
Lint: Pre-merge checks
Inline Actions

clang-tidy: warning: invalid case style for function 'LowerASAN_CHECK_MEMACCESS' [readability-identifier-naming]
not useful

Lint: Pre-merge checks: clang-tidy: warning: invalid case style for function 'LowerASAN_CHECK_MEMACCESS' [readability…
void emitAsanMemaccessSymbols(Module &M);
void emitAsanMemaccessPartial(Module &M, unsigned Reg,
const ASanAccessInfo &AccessInfo,
MCSubtargetInfo &STI);
void emitAsanMemaccessFull(Module &M, unsigned Reg,
const ASanAccessInfo &AccessInfo,
MCSubtargetInfo &STI);
void emitAsanReportError(Module &M, unsigned Reg,
const ASanAccessInfo &AccessInfo,
MCSubtargetInfo &STI);
typedef std::tuple<unsigned /*Reg*/, uint32_t /*AccessInfo*/>
AsanMemaccessTuple;
std::map<AsanMemaccessTuple, MCSymbol *> AsanMemaccessSymbols;
// Choose between emitting .seh_ directives and .cv_fpo_ directives. // Choose between emitting .seh_ directives and .cv_fpo_ directives.
void EmitSEHInstruction(const MachineInstr *MI); void EmitSEHInstruction(const MachineInstr *MI);
void PrintSymbolOperand(const MachineOperand &MO, raw_ostream &O) override; void PrintSymbolOperand(const MachineOperand &MO, raw_ostream &O) override;
void PrintOperand(const MachineInstr *MI, unsigned OpNo, raw_ostream &O); void PrintOperand(const MachineInstr *MI, unsigned OpNo, raw_ostream &O);
void PrintModifiedOperand(const MachineInstr *MI, unsigned OpNo, void PrintModifiedOperand(const MachineInstr *MI, unsigned OpNo,
raw_ostream &O, const char *Modifier); raw_ostream &O, const char *Modifier);
void PrintPCRelImm(const MachineInstr *MI, unsigned OpNo, raw_ostream &O); void PrintPCRelImm(const MachineInstr *MI, unsigned OpNo, raw_ostream &O);
▲ Show 20 Lines • Show All 47 Lines • Show Last 20 Lines

llvm/lib/Target/X86/X86AsmPrinter.cpp

Show First 20 Lines • Show All 747 Lines • ▼ Show 20 Lines if (!Stubs.empty()) {
Stubs.clear(); Stubs.clear();
OutStreamer.AddBlankLine(); OutStreamer.AddBlankLine();
} }
} }
void X86AsmPrinter::emitEndOfAsmFile(Module &M) { void X86AsmPrinter::emitEndOfAsmFile(Module &M) {
const Triple &TT = TM.getTargetTriple(); const Triple &TT = TM.getTargetTriple();
emitAsanMemaccessSymbols(M);
if (TT.isOSBinFormatMachO()) { if (TT.isOSBinFormatMachO()) {
// Mach-O uses non-lazy symbol stubs to encode per-TU information into // Mach-O uses non-lazy symbol stubs to encode per-TU information into
// global table for symbol lookup. // global table for symbol lookup.
emitNonLazyStubs(MMI, *OutStreamer); emitNonLazyStubs(MMI, *OutStreamer);
// Emit stack and fault map information. // Emit stack and fault map information.
emitStackMaps(SM); emitStackMaps(SM);
FM.serializeToFaultMapSection(); FM.serializeToFaultMapSection();
▲ Show 20 Lines • Show All 44 Lines • Show Last 20 Lines

llvm/lib/Target/X86/X86InstrCompiler.td

Show First 20 Lines • Show All 255 Lines • ▼ Show 20 Lines def SEH_PushFrame : I<0, Pseudo, (outs), (ins i1imm:$mode),
"#SEH_PushFrame $mode", []>; "#SEH_PushFrame $mode", []>;
def SEH_EndPrologue : I<0, Pseudo, (outs), (ins), def SEH_EndPrologue : I<0, Pseudo, (outs), (ins),
"#SEH_EndPrologue", []>; "#SEH_EndPrologue", []>;
def SEH_Epilogue : I<0, Pseudo, (outs), (ins), def SEH_Epilogue : I<0, Pseudo, (outs), (ins),
"#SEH_Epilogue", []>; "#SEH_Epilogue", []>;
} }
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Pseudo instructions used by address sanitizer.
//===----------------------------------------------------------------------===//
let
Defs = [R8, EFLAGS] in {
def ASAN_CHECK_MEMACCESS : PseudoI<
(outs), (ins GR64NoR8:$addr, i32imm:$accessinfo),
[(int_asan_check_memaccess GR64NoR8:$addr, (i32 timm:$accessinfo))]>,
Sched<[]>;
}
//===----------------------------------------------------------------------===//
// Pseudo instructions used by segmented stacks. // Pseudo instructions used by segmented stacks.
// //
// This is lowered into a RET instruction by MCInstLower. We need // This is lowered into a RET instruction by MCInstLower. We need
// this so that we don't have to have a MachineBasicBlock which ends // this so that we don't have to have a MachineBasicBlock which ends
// with a RET and also has successors. // with a RET and also has successors.
let isPseudo = 1, SchedRW = [WriteJumpLd] in { let isPseudo = 1, SchedRW = [WriteJumpLd] in {
def MORESTACK_RET: I<0, Pseudo, (outs), (ins), "", []>; def MORESTACK_RET: I<0, Pseudo, (outs), (ins), "", []>;
▲ Show 20 Lines • Show All 683 Lines • ▼ Show 20 Lines def NAME#16 : I<opc, MRMSrcMem, (outs GR16:$dst),
GR16:$dst, GR16:$dst,
(!cast<PatFrag>(frag # "_16") addr:$ptr, GR16:$val))]>, (!cast<PatFrag>(frag # "_16") addr:$ptr, GR16:$val))]>,
OpSize16; OpSize16;
def NAME#32 : I<opc, MRMSrcMem, (outs GR32:$dst), def NAME#32 : I<opc, MRMSrcMem, (outs GR32:$dst),
(ins GR32:$val, i32mem:$ptr), (ins GR32:$val, i32mem:$ptr),
!strconcat(mnemonic, "{l}\t{$val, $ptr|$ptr, $val}"), !strconcat(mnemonic, "{l}\t{$val, $ptr|$ptr, $val}"),
[(set [(set
GR32:$dst, GR32:$dst,
(!cast<PatFrag>(frag # "_32") addr:$ptr, GR32:$val))]>, (!cast<PatFrag>(frag # "_32") addr:$ptr, GR32:$val))]>,
OpSize32; OpSize32;
def NAME#64 : RI<opc, MRMSrcMem, (outs GR64:$dst), def NAME#64 : RI<opc, MRMSrcMem, (outs GR64:$dst),
(ins GR64:$val, i64mem:$ptr), (ins GR64:$val, i64mem:$ptr),
!strconcat(mnemonic, "{q}\t{$val, $ptr|$ptr, $val}"), !strconcat(mnemonic, "{q}\t{$val, $ptr|$ptr, $val}"),
[(set [(set
GR64:$dst, GR64:$dst,
(!cast<PatFrag>(frag # "_64") addr:$ptr, GR64:$val))]>; (!cast<PatFrag>(frag # "_64") addr:$ptr, GR64:$val))]>;
} }
▲ Show 20 Lines • Show All 1,226 Lines • Show Last 20 Lines

llvm/lib/Target/X86/X86MCInstLower.cpp

Show All 37 Lines
#include "llvm/MC/MCFixup.h" #include "llvm/MC/MCFixup.h"
#include "llvm/MC/MCInst.h" #include "llvm/MC/MCInst.h"
#include "llvm/MC/MCInstBuilder.h" #include "llvm/MC/MCInstBuilder.h"
#include "llvm/MC/MCSection.h" #include "llvm/MC/MCSection.h"
#include "llvm/MC/MCSectionELF.h" #include "llvm/MC/MCSectionELF.h"
#include "llvm/MC/MCStreamer.h" #include "llvm/MC/MCStreamer.h"
#include "llvm/MC/MCSymbol.h" #include "llvm/MC/MCSymbol.h"
#include "llvm/MC/MCSymbolELF.h" #include "llvm/MC/MCSymbolELF.h"
#include "llvm/Support/TargetRegistry.h"
#include "llvm/Target/TargetLoweringObjectFile.h" #include "llvm/Target/TargetLoweringObjectFile.h"
#include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetMachine.h"
#include "llvm/Transforms/Instrumentation/AddressSanitizer.h"
#include "llvm/Transforms/Instrumentation/AddressSanitizerCommon.h"
using namespace llvm; using namespace llvm;
namespace { namespace {
/// X86MCInstLower - This class is used to lower an MachineInstr into an MCInst. /// X86MCInstLower - This class is used to lower an MachineInstr into an MCInst.
class X86MCInstLower { class X86MCInstLower {
MCContext &Ctx; MCContext &Ctx;
▲ Show 20 Lines • Show All 1,262 Lines • ▼ Show 20 Linesvoid X86AsmPrinter::LowerFENTRY_CALL(const MachineInstr &MI,
const MCSymbolRefExpr *Op = const MCSymbolRefExpr *Op =
MCSymbolRefExpr::create(fentry, MCSymbolRefExpr::VK_None, Ctx); MCSymbolRefExpr::create(fentry, MCSymbolRefExpr::VK_None, Ctx);
EmitAndCountInstruction( EmitAndCountInstruction(
MCInstBuilder(Is64Bits ? X86::CALL64pcrel32 : X86::CALLpcrel32) MCInstBuilder(Is64Bits ? X86::CALL64pcrel32 : X86::CALLpcrel32)
.addExpr(Op)); .addExpr(Op));
} }
void X86AsmPrinter::LowerASAN_CHECK_MEMACCESS(const MachineInstr &MI) {
// FIXME: Make this work on non-ELF.
if (!TM.getTargetTriple().isOSBinFormatELF()) {
report_fatal_error("llvm.asan.check.memaccess only supported on ELF");
return;
}
unsigned Reg = MI.getOperand(0).getReg().id();
ASanAccessInfo AccessInfo(MI.getOperand(1).getImm());
MCSymbol *&Sym =
AsanMemaccessSymbols[AsanMemaccessTuple(Reg, AccessInfo.Packed)];
if (!Sym) {
std::string Name = AccessInfo.IsWrite ? "store" : "load";
std::string SymName = "__asan_check_" + Name +
utostr(1 << AccessInfo.AccessSizeIndex) + "_rn" +
utostr(Reg);
Sym = OutContext.getOrCreateSymbol(SymName);
}
EmitAndCountInstruction(
MCInstBuilder(X86::CALL64pcrel32)
.addExpr(MCSymbolRefExpr::create(Sym, OutContext)));
}
void X86AsmPrinter::emitAsanMemaccessPartial(Module &M, unsigned Reg,
const ASanAccessInfo &AccessInfo,
MCSubtargetInfo &STI) {
assert(AccessInfo.AccessSizeIndex == 0 || AccessInfo.AccessSizeIndex == 1 ||
AccessInfo.AccessSizeIndex == 2);
assert(Reg != X86::R8);
uint64_t ShadowBase;
int MappingScale;
bool OrShadowOffset;
getAddressSanitizerParams(
Triple(M.getTargetTriple()), M.getDataLayout().getPointerSizeInBits(),
AccessInfo.CompileKernel, &ShadowBase, &MappingScale, &OrShadowOffset);
OutStreamer->emitInstruction(
MCInstBuilder(X86::MOV64rr).addReg(X86::R8).addReg(X86::NoRegister + Reg),
STI);
OutStreamer->emitInstruction(MCInstBuilder(X86::SHR64ri)
.addReg(X86::R8)
.addReg(X86::NoRegister)
.addImm(MappingScale),
STI);
if (OrShadowOffset) {
OutStreamer->emitInstruction(MCInstBuilder(X86::OR64ri32)
.addReg(X86::NoRegister)
.addReg(X86::R8)
.addImm(ShadowBase),
STI);
OutStreamer->emitInstruction(MCInstBuilder(X86::MOV8rm)
.addReg(X86::R8B)
.addReg(X86::R8)
.addImm(1)
.addReg(X86::NoRegister)
.addImm(0)
.addReg(X86::NoRegister),
STI);
OutStreamer->emitInstruction(
MCInstBuilder(X86::TEST8rr).addReg(X86::R8B).addReg(X86::R8B), STI);
} else {
OutStreamer->emitInstruction(MCInstBuilder(X86::MOVSX32rm8)
.addReg(X86::R8D)
.addReg(X86::R8)
.addImm(1)
.addReg(X86::NoRegister)
.addImm(ShadowBase)
.addReg(X86::NoRegister),
STI);
OutStreamer->emitInstruction(
MCInstBuilder(X86::TEST32rr).addReg(X86::R8D).addReg(X86::R8D), STI);
}
MCSymbol *AdditionalCheck = OutContext.createTempSymbol();
OutStreamer->emitInstruction(
MCInstBuilder(X86::JCC_1)
.addExpr(MCSymbolRefExpr::create(AdditionalCheck, OutContext))
.addImm(X86::COND_NE),
STI);
MCSymbol *ReturnSym = OutContext.createTempSymbol();
OutStreamer->emitLabel(ReturnSym);
OutStreamer->emitInstruction(MCInstBuilder(getRetOpcode(*Subtarget)), STI);
// Shadow byte is non-zero so we need to perform additional checks.
OutStreamer->emitLabel(AdditionalCheck);
OutStreamer->emitInstruction(MCInstBuilder(X86::PUSH64r).addReg(X86::RCX),
STI);
OutStreamer->emitInstruction(MCInstBuilder(X86::MOV64rr)
.addReg(X86::RCX)
.addReg(X86::NoRegister + Reg),
STI);
const size_t Granularity = 1ULL << MappingScale;
OutStreamer->emitInstruction(MCInstBuilder(X86::AND32ri8)
.addReg(X86::NoRegister)
.addReg(X86::ECX)
.addImm(Granularity - 1),
STI);
if (AccessInfo.AccessSizeIndex == 1) {
OutStreamer->emitInstruction(MCInstBuilder(X86::ADD32ri8)
.addReg(X86::NoRegister)
.addReg(X86::ECX)
.addImm(1),
STI);
} else if (AccessInfo.AccessSizeIndex == 2) {
OutStreamer->emitInstruction(MCInstBuilder(X86::ADD32ri8)
.addReg(X86::NoRegister)
.addReg(X86::ECX)
.addImm(3),
STI);
}
OutStreamer->emitInstruction(
MCInstBuilder(X86::CMP32rr).addReg(X86::ECX).addReg(X86::R8D).addImm(1),
STI);
OutStreamer->emitInstruction(MCInstBuilder(X86::POP64r).addReg(X86::RCX),
STI);
OutStreamer->emitInstruction(
MCInstBuilder(X86::JCC_1)
.addExpr(MCSymbolRefExpr::create(ReturnSym, OutContext))
.addImm(X86::COND_L),
STI);
emitAsanReportError(M, Reg, AccessInfo, STI);
}
void X86AsmPrinter::emitAsanMemaccessFull(Module &M, unsigned Reg,
const ASanAccessInfo &AccessInfo,
MCSubtargetInfo &STI) {
assert(AccessInfo.AccessSizeIndex == 3 || AccessInfo.AccessSizeIndex == 4);
assert(Reg != X86::R8);
uint64_t ShadowBase;
int MappingScale;
bool OrShadowOffset;
getAddressSanitizerParams(
Triple(M.getTargetTriple()), M.getDataLayout().getPointerSizeInBits(),
AccessInfo.CompileKernel, &ShadowBase, &MappingScale, &OrShadowOffset);
OutStreamer->emitInstruction(
MCInstBuilder(X86::MOV64rr).addReg(X86::R8).addReg(X86::NoRegister + Reg),
STI);
OutStreamer->emitInstruction(MCInstBuilder(X86::SHR64ri)
.addReg(X86::R8)
.addReg(X86::R8)
.addImm(MappingScale),
STI);
if (OrShadowOffset) {
OutStreamer->emitInstruction(MCInstBuilder(X86::OR64ri32)
.addReg(X86::R8)
.addReg(X86::R8)
.addImm(ShadowBase),
STI);
auto OpCode = AccessInfo.AccessSizeIndex == 3 ? X86::CMP8mi : X86::CMP16mi8;
OutStreamer->emitInstruction(MCInstBuilder(OpCode)
.addReg(X86::R8)
.addImm(1)
.addReg(X86::NoRegister)
.addImm(0)
.addReg(X86::NoRegister)
.addImm(0),
STI);
} else {
auto OpCode = AccessInfo.AccessSizeIndex == 3 ? X86::CMP8mi : X86::CMP16mi8;
OutStreamer->emitInstruction(MCInstBuilder(OpCode)
.addReg(X86::R8)
.addImm(1)
.addReg(X86::NoRegister)
.addImm(ShadowBase)
.addReg(X86::NoRegister)
.addImm(0),
STI);
}
MCSymbol *ReportCode = OutContext.createTempSymbol();
OutStreamer->emitInstruction(
MCInstBuilder(X86::JCC_1)
.addExpr(MCSymbolRefExpr::create(ReportCode, OutContext))
.addImm(X86::COND_NE),
STI);
MCSymbol *ReturnSym = OutContext.createTempSymbol();
OutStreamer->emitLabel(ReturnSym);
OutStreamer->emitInstruction(MCInstBuilder(getRetOpcode(*Subtarget)), STI);
OutStreamer->emitLabel(ReportCode);
emitAsanReportError(M, Reg, AccessInfo, STI);
}
void X86AsmPrinter::emitAsanReportError(Module &M, unsigned Reg,
const ASanAccessInfo &AccessInfo,
MCSubtargetInfo &STI) {
std::string Name = AccessInfo.IsWrite ? "store" : "load";
MCSymbol *ReportError = OutContext.getOrCreateSymbol(
"__asan_report_" + Name + utostr(1 << AccessInfo.AccessSizeIndex));
OutStreamer->emitInstruction(MCInstBuilder(X86::MOV64rr)
.addReg(X86::RDI)
.addReg(X86::NoRegister + Reg),
STI);
OutStreamer->emitInstruction(
MCInstBuilder(X86::JMP_1)
.addExpr(MCSymbolRefExpr::create(ReportError, OutContext)),
STI);
}
void X86AsmPrinter::emitAsanMemaccessSymbols(Module &M) {
if (AsanMemaccessSymbols.empty())
return;
const Triple &TT = TM.getTargetTriple();
assert(TT.isOSBinFormatELF());
std::unique_ptr<MCSubtargetInfo> STI(
TM.getTarget().createMCSubtargetInfo(TT.str(), "", ""));
assert(STI && "Unable to create subtarget info");
for (auto &P : AsanMemaccessSymbols) {
MCSymbol *Sym = P.second;
OutStreamer->SwitchSection(OutContext.getELFSection(
".text.hot", ELF::SHT_PROGBITS,
ELF::SHF_EXECINSTR | ELF::SHF_ALLOC | ELF::SHF_GROUP, 0, Sym->getName(),
/*IsComdat=*/true));
OutStreamer->emitSymbolAttribute(Sym, MCSA_ELF_TypeFunction);
OutStreamer->emitSymbolAttribute(Sym, MCSA_Weak);
OutStreamer->emitSymbolAttribute(Sym, MCSA_Hidden);
OutStreamer->emitLabel(Sym);
unsigned Reg = std::get<0>(P.first);
ASanAccessInfo AccessInfo(std::get<1>(P.first));
if (AccessInfo.AccessSizeIndex < 3) {
emitAsanMemaccessPartial(M, Reg, AccessInfo, *STI);
} else {
emitAsanMemaccessFull(M, Reg, AccessInfo, *STI);
}
}
}
void X86AsmPrinter::LowerPATCHABLE_OP(const MachineInstr &MI, void X86AsmPrinter::LowerPATCHABLE_OP(const MachineInstr &MI,
X86MCInstLower &MCIL) { X86MCInstLower &MCIL) {
// PATCHABLE_OP minsize, opcode, operands // PATCHABLE_OP minsize, opcode, operands
NoAutoPaddingScope NoPadScope(*OutStreamer); NoAutoPaddingScope NoPadScope(*OutStreamer);
unsigned MinSize = MI.getOperand(0).getImm(); unsigned MinSize = MI.getOperand(0).getImm();
unsigned Opcode = MI.getOperand(1).getImm(); unsigned Opcode = MI.getOperand(1).getImm();
▲ Show 20 Lines • Show All 1,224 Lines • ▼ Show 20 Linesvoid X86AsmPrinter::emitInstruction(const MachineInstr *MI) {
case TargetOpcode::PATCHABLE_TYPED_EVENT_CALL: case TargetOpcode::PATCHABLE_TYPED_EVENT_CALL:
return LowerPATCHABLE_TYPED_EVENT_CALL(*MI, MCInstLowering); return LowerPATCHABLE_TYPED_EVENT_CALL(*MI, MCInstLowering);
case X86::MORESTACK_RET: case X86::MORESTACK_RET:
EmitAndCountInstruction(MCInstBuilder(getRetOpcode(*Subtarget))); EmitAndCountInstruction(MCInstBuilder(getRetOpcode(*Subtarget)));
return; return;
case X86::ASAN_CHECK_MEMACCESS:
return LowerASAN_CHECK_MEMACCESS(*MI);
case X86::MORESTACK_RET_RESTORE_R10: case X86::MORESTACK_RET_RESTORE_R10:
// Return, then restore R10. // Return, then restore R10.
EmitAndCountInstruction(MCInstBuilder(getRetOpcode(*Subtarget))); EmitAndCountInstruction(MCInstBuilder(getRetOpcode(*Subtarget)));
EmitAndCountInstruction( EmitAndCountInstruction(
MCInstBuilder(X86::MOV64rr).addReg(X86::R10).addReg(X86::RAX)); MCInstBuilder(X86::MOV64rr).addReg(X86::R10).addReg(X86::RAX));
return; return;
case X86::SEH_PushReg: case X86::SEH_PushReg:
▲ Show 20 Lines • Show All 58 Lines • Show Last 20 Lines

llvm/lib/Target/X86/X86RegisterInfo.td

Show First 20 Lines • Show All 430 Lines • ▼ Show 20 Lines
// RIP isn't really a register and it can't be used anywhere except in an // RIP isn't really a register and it can't be used anywhere except in an
// address, but it doesn't cause trouble. // address, but it doesn't cause trouble.
// FIXME: it *does* cause trouble - CheckBaseRegAndIndexReg() has extra // FIXME: it *does* cause trouble - CheckBaseRegAndIndexReg() has extra
// tests because of the inclusion of RIP in this register class. // tests because of the inclusion of RIP in this register class.
def GR64 : RegisterClass<"X86", [i64], 64, def GR64 : RegisterClass<"X86", [i64], 64,
(add RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11, (add RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
RBX, R14, R15, R12, R13, RBP, RSP, RIP)>; RBX, R14, R15, R12, R13, RBP, RSP, RIP)>;
// GR64 - 64-bit GPRs without R8 and RIP. Could be used when emitting code for
// intrinsics, which use implict input registers.
def GR64NoR8 : RegisterClass<"X86", [i64], 64,
(add RAX, RCX, RDX, RSI, RDI, R9, R10, R11,
RBX, R14, R15, R12, R13, RBP, RSP)>;
// Segment registers for use by MOV instructions (and others) that have a // Segment registers for use by MOV instructions (and others) that have a
// segment register as one operand. Always contain a 16-bit segment // segment register as one operand. Always contain a 16-bit segment
// descriptor. // descriptor.
def SEGMENT_REG : RegisterClass<"X86", [i16], 16, (add CS, DS, SS, ES, FS, GS)>; def SEGMENT_REG : RegisterClass<"X86", [i16], 16, (add CS, DS, SS, ES, FS, GS)>;
// Debug registers. // Debug registers.
def DEBUG_REG : RegisterClass<"X86", [i32], 32, (sequence "DR%u", 0, 15)>; def DEBUG_REG : RegisterClass<"X86", [i32], 32, (sequence "DR%u", 0, 15)>;
▲ Show 20 Lines • Show All 197 Lines • Show Last 20 Lines

llvm/lib/Transforms/Instrumentation/AddressSanitizer.cpp

Show First 20 Lines • Show All 172 Lines • ▼ Show 20 Lines
const char kAMDGPUAddressSharedName[] = "llvm.amdgcn.is.shared"; const char kAMDGPUAddressSharedName[] = "llvm.amdgcn.is.shared";
const char kAMDGPUAddressPrivateName[] = "llvm.amdgcn.is.private"; const char kAMDGPUAddressPrivateName[] = "llvm.amdgcn.is.private";
// Accesses sizes are powers of two: 1, 2, 4, 8, 16. // Accesses sizes are powers of two: 1, 2, 4, 8, 16.
static const size_t kNumberOfAccessSizes = 5; static const size_t kNumberOfAccessSizes = 5;
static const unsigned kAllocaRzSize = 32; static const unsigned kAllocaRzSize = 32;
// ASanAccessInfo implementation constants.
constexpr size_t kCompileKernelShift = 0;
Lint: Pre-merge checks
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clang-tidy: warning: invalid case style for variable 'kCompileKernelShift' [readability-identifier-naming]
not useful

Lint: Pre-merge checks: clang-tidy: warning: invalid case style for variable 'kCompileKernelShift' [readability…
constexpr size_t kCompileKernelMask = 0x1;
Lint: Pre-merge checks
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clang-tidy: warning: invalid case style for variable 'kCompileKernelMask' [readability-identifier-naming]
not useful

Lint: Pre-merge checks: clang-tidy: warning: invalid case style for variable 'kCompileKernelMask' [readability…
constexpr size_t kAccessSizeIndexShift = 1;
Lint: Pre-merge checks
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clang-tidy: warning: invalid case style for variable 'kAccessSizeIndexShift' [readability-identifier-naming]
not useful

Lint: Pre-merge checks: clang-tidy: warning: invalid case style for variable 'kAccessSizeIndexShift' [readability…
constexpr size_t kAccessSizeIndexMask = 0xf;
Lint: Pre-merge checks
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clang-tidy: warning: invalid case style for variable 'kAccessSizeIndexMask' [readability-identifier-naming]
not useful

Lint: Pre-merge checks: clang-tidy: warning: invalid case style for variable 'kAccessSizeIndexMask' [readability…
constexpr size_t kIsWriteShift = 5;
Lint: Pre-merge checks
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clang-tidy: warning: invalid case style for variable 'kIsWriteShift' [readability-identifier-naming]
not useful

Lint: Pre-merge checks: clang-tidy: warning: invalid case style for variable 'kIsWriteShift' [readability-identifier…
constexpr size_t kIsWriteMask = 0x1;
Lint: Pre-merge checks
Inline Actions

clang-tidy: warning: invalid case style for variable 'kIsWriteMask' [readability-identifier-naming]
not useful

Lint: Pre-merge checks: clang-tidy: warning: invalid case style for variable 'kIsWriteMask' [readability-identifier…
// Command-line flags. // Command-line flags.
static cl::opt<bool> ClEnableKasan( static cl::opt<bool> ClEnableKasan(
"asan-kernel", cl::desc("Enable KernelAddressSanitizer instrumentation"), "asan-kernel", cl::desc("Enable KernelAddressSanitizer instrumentation"),
cl::Hidden, cl::init(false)); cl::Hidden, cl::init(false));
static cl::opt<bool> ClRecover( static cl::opt<bool> ClRecover(
"asan-recover", "asan-recover",
▲ Show 20 Lines • Show All 378 Lines • ▼ Show 20 Lines
void getAddressSanitizerParams(const Triple &TargetTriple, int LongSize, void getAddressSanitizerParams(const Triple &TargetTriple, int LongSize,
bool IsKasan, uint64_t *ShadowBase, bool IsKasan, uint64_t *ShadowBase,
int *MappingScale, bool *OrShadowOffset) { int *MappingScale, bool *OrShadowOffset) {
auto Mapping = getShadowMapping(TargetTriple, LongSize, IsKasan); auto Mapping = getShadowMapping(TargetTriple, LongSize, IsKasan);
*ShadowBase = Mapping.Offset; *ShadowBase = Mapping.Offset;
*MappingScale = Mapping.Scale; *MappingScale = Mapping.Scale;
*OrShadowOffset = Mapping.OrShadowOffset; *OrShadowOffset = Mapping.OrShadowOffset;
} }
ASanAccessInfo::ASanAccessInfo(int32_t Packed)
: Packed(Packed),
AccessSizeIndex((Packed >> kAccessSizeIndexShift) & kAccessSizeIndexMask),
IsWrite((Packed >> kIsWriteShift) & kIsWriteMask),
CompileKernel((Packed >> kCompileKernelShift) & kCompileKernelMask) {}
ASanAccessInfo::ASanAccessInfo(bool IsWrite, bool CompileKernel,
uint8_t AccessSizeIndex)
: Packed((IsWrite << kIsWriteShift) +
(CompileKernel << kCompileKernelShift) +
(AccessSizeIndex << kAccessSizeIndexShift)),
AccessSizeIndex(AccessSizeIndex), IsWrite(IsWrite),
CompileKernel(CompileKernel) {}
} // namespace llvm } // namespace llvm
static uint64_t getRedzoneSizeForScale(int MappingScale) { static uint64_t getRedzoneSizeForScale(int MappingScale) {
// Redzone used for stack and globals is at least 32 bytes. // Redzone used for stack and globals is at least 32 bytes.
// For scales 6 and 7, the redzone has to be 64 and 128 bytes respectively. // For scales 6 and 7, the redzone has to be 64 and 128 bytes respectively.
return std::max(32U, 1U << MappingScale); return std::max(32U, 1U << MappingScale);
} }
▲ Show 20 Lines • Show All 3,025 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/asan-check-memaccess-add.ll

  • This file was added.
; RUN: llc < %s | FileCheck %s
target triple = "x86_64-unknown-linux-gnu"
define void @load1(i8* nocapture readonly %x) {
; CHECK: callq __asan_check_load1_rn[[RN1:.*]]
; CHECK: callq __asan_check_store1_rn[[RN1]]
; CHECK-NEXT: retq
call void @llvm.asan.check.memaccess(i8* %x, i32 0)
call void @llvm.asan.check.memaccess(i8* %x, i32 32)
ret void
}
define void @load2(i16* nocapture readonly %x) {
; CHECK: callq __asan_check_load2_rn[[RN2:.*]]
; CHECK: callq __asan_check_store2_rn[[RN2]]
; CHECK-NEXT: retq
%1 = ptrtoint i16* %x to i64
%2 = bitcast i16* %x to i8*
call void @llvm.asan.check.memaccess(i8* %2, i32 2)
call void @llvm.asan.check.memaccess(i8* %2, i32 34)
ret void
}
define void @load4(i32* nocapture readonly %x) {
; CHECK: callq __asan_check_load4_rn[[RN4:.*]]
; CHECK: callq __asan_check_store4_rn[[RN4]]
; CHECK-NEXT: retq
%1 = ptrtoint i32* %x to i64
%2 = bitcast i32* %x to i8*
call void @llvm.asan.check.memaccess(i8* %2, i32 4)
call void @llvm.asan.check.memaccess(i8* %2, i32 36)
ret void
}
define void @load8(i64* nocapture readonly %x) {
; CHECK: callq __asan_check_load8_rn[[RN8:.*]]
; CHECK: callq __asan_check_store8_rn[[RN8]]
; CHECK-NEXT: retq
%1 = ptrtoint i64* %x to i64
%2 = bitcast i64* %x to i8*
call void @llvm.asan.check.memaccess(i8* %2, i32 6)
call void @llvm.asan.check.memaccess(i8* %2, i32 38)
ret void
}
define void @load16(i128* nocapture readonly %x) {
; CHECK: callq __asan_check_load16_rn[[RN16:.*]]
; CHECK: callq __asan_check_store16_rn[[RN16]]
; CHECK-NEXT: retq
%1 = ptrtoint i128* %x to i64
%2 = bitcast i128* %x to i8*
call void @llvm.asan.check.memaccess(i8* %2, i32 8)
call void @llvm.asan.check.memaccess(i8* %2, i32 40)
ret void
}
; CHECK: .type __asan_check_load1_rn[[RN1]],@function
; CHECK-NEXT: .weak __asan_check_load1_rn[[RN1]]
; CHECK-NEXT: .hidden __asan_check_load1_rn[[RN1]]
; CHECK-NEXT: __asan_check_load1_rn[[RN1]]:
; CHECK-NEXT: movq [[REG:.*]], %r8
; CHECK-NEXT: shrq $3, %r8
; CHECK-NEXT: movsbl 2147450880(%r8), %r8d
; CHECK-NEXT: testl %r8d, %r8d
; CHECK-NEXT: jne [[EXTRA:.*]]
; CHECK-NEXT: [[RET:.*]]:
; CHECK-NEXT: retq
; CHECK-NEXT: [[EXTRA]]:
; CHECK-NEXT: pushq %rcx
; CHECK-NEXT: movq [[REG]], %rcx
; CHECK-NEXT: andl $7, %ecx
; CHECK-NEXT: cmpl %r8d, %ecx
; CHECK-NEXT: popq %rcx
; CHECK-NEXT: jl [[RET]]
; CHECK-NEXT: movq [[REG:.*]], %rdi
; CHECK-NEXT: jmp __asan_report_load1
; CHECK: .type __asan_check_load2_rn[[RN2]],@function
; CHECK-NEXT: .weak __asan_check_load2_rn[[RN2]]
; CHECK-NEXT: .hidden __asan_check_load2_rn[[RN2]]
; CHECK-NEXT: __asan_check_load2_rn[[RN2]]:
; CHECK-NEXT: movq [[REG:.*]], %r8
; CHECK-NEXT: shrq $3, %r8
; CHECK-NEXT: movsbl 2147450880(%r8), %r8d
; CHECK-NEXT: testl %r8d, %r8d
; CHECK-NEXT: jne [[EXTRA:.*]]
; CHECK-NEXT: [[RET:.*]]:
; CHECK-NEXT: retq
; CHECK-NEXT: [[EXTRA]]:
; CHECK-NEXT: pushq %rcx
; CHECK-NEXT: movq [[REG]], %rcx
; CHECK-NEXT: andl $7, %ecx
; CHECK-NEXT: addl $1, %ecx
; CHECK-NEXT: cmpl %r8d, %ecx
; CHECK-NEXT: popq %rcx
; CHECK-NEXT: jl [[RET]]
; CHECK-NEXT: movq [[REG:.*]], %rdi
; CHECK-NEXT: jmp __asan_report_load2
; CHECK: .type __asan_check_load4_rn[[RN4]],@function
; CHECK-NEXT: .weak __asan_check_load4_rn[[RN4]]
; CHECK-NEXT: .hidden __asan_check_load4_rn[[RN4]]
; CHECK-NEXT: __asan_check_load4_rn[[RN4]]:
; CHECK-NEXT: movq [[REG:.*]], %r8
; CHECK-NEXT: shrq $3, %r8
; CHECK-NEXT: movsbl 2147450880(%r8), %r8d
; CHECK-NEXT: testl %r8d, %r8d
; CHECK-NEXT: jne [[EXTRA:.*]]
; CHECK-NEXT: [[RET:.*]]:
; CHECK-NEXT: retq
; CHECK-NEXT: [[EXTRA]]:
; CHECK-NEXT: pushq %rcx
; CHECK-NEXT: movq [[REG]], %rcx
; CHECK-NEXT: andl $7, %ecx
; CHECK-NEXT: addl $3, %ecx
; CHECK-NEXT: cmpl %r8d, %ecx
; CHECK-NEXT: popq %rcx
; CHECK-NEXT: jl [[RET]]
; CHECK-NEXT: movq [[REG:.*]], %rdi
; CHECK-NEXT: jmp __asan_report_load4
; CHECK: .type __asan_check_load8_rn[[RN8]],@function
; CHECK-NEXT: .weak __asan_check_load8_rn[[RN8]]
; CHECK-NEXT: .hidden __asan_check_load8_rn[[RN8]]
; CHECK-NEXT: __asan_check_load8_rn[[RN8]]:
; CHECK-NEXT: movq [[REG:.*]], %r8
; CHECK-NEXT: shrq $3, %r8
; CHECK-NEXT: cmpb $0, 2147450880(%r8)
; CHECK-NEXT: jne [[FAIL:.*]]
; CHECK-NEXT: [[RET:.*]]:
; CHECK-NEXT: retq
; CHECK-NEXT: [[FAIL]]:
; CHECK-NEXT: movq [[REG:.*]], %rdi
; CHECK-NEXT: jmp __asan_report_load8
; CHECK: .type __asan_check_load16_rn[[RN16]],@function
; CHECK-NEXT: .weak __asan_check_load16_rn[[RN16]]
; CHECK-NEXT: .hidden __asan_check_load16_rn[[RN16]]
; CHECK-NEXT: __asan_check_load16_rn[[RN16]]:
; CHECK-NEXT: movq [[REG:.*]], %r8
; CHECK-NEXT: shrq $3, %r8
; CHECK-NEXT: cmpw $0, 2147450880(%r8)
; CHECK-NEXT: jne [[FAIL:.*]]
; CHECK-NEXT: [[RET:.*]]:
; CHECK-NEXT: retq
; CHECK-NEXT: [[FAIL]]:
; CHECK-NEXT: movq [[REG:.*]], %rdi
; CHECK-NEXT: jmp __asan_report_load16
; CHECK: .type __asan_check_store1_rn[[RN1]],@function
; CHECK-NEXT: .weak __asan_check_store1_rn[[RN1]]
; CHECK-NEXT: .hidden __asan_check_store1_rn[[RN1]]
; CHECK-NEXT: __asan_check_store1_rn[[RN1]]:
; CHECK-NEXT: movq [[REG:.*]], %r8
; CHECK-NEXT: shrq $3, %r8
; CHECK-NEXT: movsbl 2147450880(%r8), %r8d
; CHECK-NEXT: testl %r8d, %r8d
; CHECK-NEXT: jne [[EXTRA:.*]]
; CHECK-NEXT: [[RET:.*]]:
; CHECK-NEXT: retq
; CHECK-NEXT: [[EXTRA]]:
; CHECK-NEXT: pushq %rcx
; CHECK-NEXT: movq [[REG]], %rcx
; CHECK-NEXT: andl $7, %ecx
; CHECK-NEXT: cmpl %r8d, %ecx
; CHECK-NEXT: popq %rcx
; CHECK-NEXT: jl [[RET]]
; CHECK-NEXT: movq [[REG:.*]], %rdi
; CHECK-NEXT: jmp __asan_report_store1
; CHECK: .type __asan_check_store2_rn[[RN2]],@function
; CHECK-NEXT: .weak __asan_check_store2_rn[[RN2]]
; CHECK-NEXT: .hidden __asan_check_store2_rn[[RN2]]
; CHECK-NEXT: __asan_check_store2_rn[[RN2]]:
; CHECK-NEXT: movq [[REG:.*]], %r8
; CHECK-NEXT: shrq $3, %r8
; CHECK-NEXT: movsbl 2147450880(%r8), %r8d
; CHECK-NEXT: testl %r8d, %r8d
; CHECK-NEXT: jne [[EXTRA:.*]]
; CHECK-NEXT: [[RET:.*]]:
; CHECK-NEXT: retq
; CHECK-NEXT: [[EXTRA]]:
; CHECK-NEXT: pushq %rcx
; CHECK-NEXT: movq [[REG]], %rcx
; CHECK-NEXT: andl $7, %ecx
; CHECK-NEXT: addl $1, %ecx
; CHECK-NEXT: cmpl %r8d, %ecx
; CHECK-NEXT: popq %rcx
; CHECK-NEXT: jl [[RET]]
; CHECK-NEXT: movq [[REG:.*]], %rdi
; CHECK-NEXT: jmp __asan_report_store2
; CHECK: .type __asan_check_store4_rn[[RN4]],@function
; CHECK-NEXT: .weak __asan_check_store4_rn[[RN4]]
; CHECK-NEXT: .hidden __asan_check_store4_rn[[RN4]]
; CHECK-NEXT: __asan_check_store4_rn[[RN4]]:
; CHECK-NEXT: movq [[REG:.*]], %r8
; CHECK-NEXT: shrq $3, %r8
; CHECK-NEXT: movsbl 2147450880(%r8), %r8d
; CHECK-NEXT: testl %r8d, %r8d
; CHECK-NEXT: jne [[EXTRA:.*]]
; CHECK-NEXT: [[RET:.*]]:
; CHECK-NEXT: retq
; CHECK-NEXT: [[EXTRA]]:
; CHECK-NEXT: pushq %rcx
; CHECK-NEXT: movq [[REG]], %rcx
; CHECK-NEXT: andl $7, %ecx
; CHECK-NEXT: addl $3, %ecx
; CHECK-NEXT: cmpl %r8d, %ecx
; CHECK-NEXT: popq %rcx
; CHECK-NEXT: jl [[RET]]
; CHECK-NEXT: movq [[REG:.*]], %rdi
; CHECK-NEXT: jmp __asan_report_store4
; CHECK: .type __asan_check_store8_rn[[RN8]],@function
; CHECK-NEXT: .weak __asan_check_store8_rn[[RN8]]
; CHECK-NEXT: .hidden __asan_check_store8_rn[[RN8]]
; CHECK-NEXT: __asan_check_store8_rn[[RN8]]:
; CHECK-NEXT: movq [[REG:.*]], %r8
; CHECK-NEXT: shrq $3, %r8
; CHECK-NEXT: cmpb $0, 2147450880(%r8)
; CHECK-NEXT: jne [[FAIL:.*]]
; CHECK-NEXT: [[RET:.*]]:
; CHECK-NEXT: retq
; CHECK-NEXT: [[FAIL]]:
; CHECK-NEXT: movq [[REG:.*]], %rdi
; CHECK-NEXT: jmp __asan_report_store8
; CHECK: .type __asan_check_store16_rn[[RN16]],@function
; CHECK-NEXT: .weak __asan_check_store16_rn[[RN16]]
; CHECK-NEXT: .hidden __asan_check_store16_rn[[RN16]]
; CHECK-NEXT: __asan_check_store16_rn[[RN16]]:
; CHECK-NEXT: movq [[REG:.*]], %r8
; CHECK-NEXT: shrq $3, %r8
; CHECK-NEXT: cmpw $0, 2147450880(%r8)
; CHECK-NEXT: jne [[FAIL:.*]]
; CHECK-NEXT: [[RET:.*]]:
; CHECK-NEXT: retq
; CHECK-NEXT: [[FAIL]]:
; CHECK-NEXT: movq [[REG:.*]], %rdi
; CHECK-NEXT: jmp __asan_report_store16
declare void @llvm.asan.check.memaccess(i8*, i32 immarg)

llvm/test/CodeGen/X86/asan-check-memaccess-or.ll

  • This file was added.
; RUN: llc < %s | FileCheck %s
target triple = "x86_64-pc-win"
define void @load1(i8* nocapture readonly %x) {
; CHECK: callq __asan_check_load1_rn[[RN1:.*]]
; CHECK: callq __asan_check_store1_rn[[RN1]]
; CHECK-NEXT: retq
call void @llvm.asan.check.memaccess(i8* %x, i32 0)
call void @llvm.asan.check.memaccess(i8* %x, i32 32)
ret void
}
define void @load2(i16* nocapture readonly %x) {
; CHECK: callq __asan_check_load2_rn[[RN2:.*]]
; CHECK: callq __asan_check_store2_rn[[RN2]]
; CHECK-NEXT: retq
%1 = ptrtoint i16* %x to i64
%2 = bitcast i16* %x to i8*
call void @llvm.asan.check.memaccess(i8* %2, i32 2)
call void @llvm.asan.check.memaccess(i8* %2, i32 34)
ret void
}
define void @load4(i32* nocapture readonly %x) {
; CHECK: callq __asan_check_load4_rn[[RN4:.*]]
; CHECK: callq __asan_check_store4_rn[[RN4]]
; CHECK-NEXT: retq
%1 = ptrtoint i32* %x to i64
%2 = bitcast i32* %x to i8*
call void @llvm.asan.check.memaccess(i8* %2, i32 4)
call void @llvm.asan.check.memaccess(i8* %2, i32 36)
ret void
}
define void @load8(i64* nocapture readonly %x) {
; CHECK: callq __asan_check_load8_rn[[RN8:.*]]
; CHECK: callq __asan_check_store8_rn[[RN8]]
; CHECK-NEXT: retq
%1 = ptrtoint i64* %x to i64
%2 = bitcast i64* %x to i8*
call void @llvm.asan.check.memaccess(i8* %2, i32 6)
call void @llvm.asan.check.memaccess(i8* %2, i32 38)
ret void
}
define void @load16(i128* nocapture readonly %x) {
; CHECK: callq __asan_check_load16_rn[[RN16:.*]]
; CHECK: callq __asan_check_store16_rn[[RN16]]
; CHECK-NEXT: retq
%1 = ptrtoint i128* %x to i64
%2 = bitcast i128* %x to i8*
call void @llvm.asan.check.memaccess(i8* %2, i32 8)
call void @llvm.asan.check.memaccess(i8* %2, i32 40)
ret void
}
; CHECK: .type __asan_check_load1_rn[[RN1]],@function
; CHECK-NEXT: .weak __asan_check_load1_rn[[RN1]]
; CHECK-NEXT: .hidden __asan_check_load1_rn[[RN1]]
; CHECK-NEXT: __asan_check_load1_rn[[RN1]]:
; CHECK-NEXT: movq [[REG:.*]], %r8
; CHECK-NEXT: shrq $3, %r8
; CHECK-NEXT: orq $17592186044416, %r8{{.*}}
; CHECK-NEXT: movb (%r8), %r8b
; CHECK-NEXT: testb %r8b, %r8b
; CHECK-NEXT: jne [[EXTRA:.*]]
; CHECK-NEXT: [[RET:.*]]:
; CHECK-NEXT: retq
; CHECK-NEXT: [[EXTRA]]:
; CHECK-NEXT: pushq %rcx
; CHECK-NEXT: movq [[REG]], %rcx
; CHECK-NEXT: andl $7, %ecx
; CHECK-NEXT: cmpl %r8d, %ecx
; CHECK-NEXT: popq %rcx
; CHECK-NEXT: jl [[RET]]
; CHECK-NEXT: movq [[REG:.*]], %rdi
; CHECK-NEXT: jmp __asan_report_load1
; CHECK: .type __asan_check_load2_rn[[RN2]],@function
; CHECK-NEXT: .weak __asan_check_load2_rn[[RN2]]
; CHECK-NEXT: .hidden __asan_check_load2_rn[[RN2]]
; CHECK-NEXT: __asan_check_load2_rn[[RN2]]:
; CHECK-NEXT: movq [[REG:.*]], %r8
; CHECK-NEXT: shrq $3, %r8
; CHECK-NEXT: orq $17592186044416, %r8{{.*}}
; CHECK-NEXT: movb (%r8), %r8b
; CHECK-NEXT: testb %r8b, %r8b
; CHECK-NEXT: jne [[EXTRA:.*]]
; CHECK-NEXT: [[RET:.*]]:
; CHECK-NEXT: retq
; CHECK-NEXT: [[EXTRA]]:
; CHECK-NEXT: pushq %rcx
; CHECK-NEXT: movq [[REG]], %rcx
; CHECK-NEXT: andl $7, %ecx
; CHECK-NEXT: addl $1, %ecx
; CHECK-NEXT: cmpl %r8d, %ecx
; CHECK-NEXT: popq %rcx
; CHECK-NEXT: jl [[RET]]
; CHECK-NEXT: movq [[REG:.*]], %rdi
; CHECK-NEXT: jmp __asan_report_load2
; CHECK: .type __asan_check_load4_rn[[RN4]],@function
; CHECK-NEXT: .weak __asan_check_load4_rn[[RN4]]
; CHECK-NEXT: .hidden __asan_check_load4_rn[[RN4]]
; CHECK-NEXT: __asan_check_load4_rn[[RN4]]:
; CHECK-NEXT: movq [[REG:.*]], %r8
; CHECK-NEXT: shrq $3, %r8
; CHECK-NEXT: orq $17592186044416, %r8{{.*}}
; CHECK-NEXT: movb (%r8), %r8b
; CHECK-NEXT: testb %r8b, %r8b
; CHECK-NEXT: jne [[EXTRA:.*]]
; CHECK-NEXT: [[RET:.*]]:
; CHECK-NEXT: retq
; CHECK-NEXT: [[EXTRA]]:
; CHECK-NEXT: pushq %rcx
; CHECK-NEXT: movq [[REG]], %rcx
; CHECK-NEXT: andl $7, %ecx
; CHECK-NEXT: addl $3, %ecx
; CHECK-NEXT: cmpl %r8d, %ecx
; CHECK-NEXT: popq %rcx
; CHECK-NEXT: jl [[RET]]
; CHECK-NEXT: movq [[REG:.*]], %rdi
; CHECK-NEXT: jmp __asan_report_load4
; CHECK: .type __asan_check_load8_rn[[RN8]],@function
; CHECK-NEXT: .weak __asan_check_load8_rn[[RN8]]
; CHECK-NEXT: .hidden __asan_check_load8_rn[[RN8]]
; CHECK-NEXT: __asan_check_load8_rn[[RN8]]:
; CHECK-NEXT: movq [[REG:.*]], %r8
; CHECK-NEXT: shrq $3, %r8
; CHECK-NEXT: orq $17592186044416, %r8{{.*}}
; CHECK-NEXT: cmpb $0, (%r8)
; CHECK-NEXT: jne [[FAIL:.*]]
; CHECK-NEXT: [[RET:.*]]:
; CHECK-NEXT: retq
; CHECK-NEXT: [[FAIL]]:
; CHECK-NEXT: movq [[REG:.*]], %rdi
; CHECK-NEXT: jmp __asan_report_load8
; CHECK: .type __asan_check_load16_rn[[RN16]],@function
; CHECK-NEXT: .weak __asan_check_load16_rn[[RN16]]
; CHECK-NEXT: .hidden __asan_check_load16_rn[[RN16]]
; CHECK-NEXT: __asan_check_load16_rn[[RN16]]:
; CHECK-NEXT: movq [[REG:.*]], %r8
; CHECK-NEXT: shrq $3, %r8
; CHECK-NEXT: orq $17592186044416, %r8{{.*}}
; CHECK-NEXT: cmpw $0, (%r8)
; CHECK-NEXT: jne [[FAIL:.*]]
; CHECK-NEXT: [[RET:.*]]:
; CHECK-NEXT: retq
; CHECK-NEXT: [[FAIL]]:
; CHECK-NEXT: movq [[REG:.*]], %rdi
; CHECK-NEXT: jmp __asan_report_load16
; CHECK: .type __asan_check_store1_rn[[RN1]],@function
; CHECK-NEXT: .weak __asan_check_store1_rn[[RN1]]
; CHECK-NEXT: .hidden __asan_check_store1_rn[[RN1]]
; CHECK-NEXT: __asan_check_store1_rn[[RN1]]:
; CHECK-NEXT: movq [[REG:.*]], %r8
; CHECK-NEXT: shrq $3, %r8
; CHECK-NEXT: orq $17592186044416, %r8
; CHECK-NEXT: movb (%r8), %r8b
; CHECK-NEXT: testb %r8b, %r8b
; CHECK-NEXT: jne [[EXTRA:.*]]
; CHECK-NEXT: [[RET:.*]]:
; CHECK-NEXT: retq
; CHECK-NEXT: [[EXTRA]]:
; CHECK-NEXT: pushq %rcx
; CHECK-NEXT: movq [[REG]], %rcx
; CHECK-NEXT: andl $7, %ecx
; CHECK-NEXT: cmpl %r8d, %ecx
; CHECK-NEXT: popq %rcx
; CHECK-NEXT: jl [[RET]]
; CHECK-NEXT: movq [[REG:.*]], %rdi
; CHECK-NEXT: jmp __asan_report_store1
; CHECK: .type __asan_check_store2_rn[[RN2]],@function
; CHECK-NEXT: .weak __asan_check_store2_rn[[RN2]]
; CHECK-NEXT: .hidden __asan_check_store2_rn[[RN2]]
; CHECK-NEXT: __asan_check_store2_rn[[RN2]]:
; CHECK-NEXT: movq [[REG:.*]], %r8
; CHECK-NEXT: shrq $3, %r8
; CHECK-NEXT: orq $17592186044416, %r8
; CHECK-NEXT: movb (%r8), %r8b
; CHECK-NEXT: testb %r8b, %r8b
; CHECK-NEXT: jne [[EXTRA:.*]]
; CHECK-NEXT: [[RET:.*]]:
; CHECK-NEXT: retq
; CHECK-NEXT: [[EXTRA]]:
; CHECK-NEXT: pushq %rcx
; CHECK-NEXT: movq [[REG]], %rcx
; CHECK-NEXT: andl $7, %ecx
; CHECK-NEXT: addl $1, %ecx
; CHECK-NEXT: cmpl %r8d, %ecx
; CHECK-NEXT: popq %rcx
; CHECK-NEXT: jl [[RET]]
; CHECK-NEXT: movq [[REG:.*]], %rdi
; CHECK-NEXT: jmp __asan_report_store2
; CHECK: .type __asan_check_store4_rn[[RN4]],@function
; CHECK-NEXT: .weak __asan_check_store4_rn[[RN4]]
; CHECK-NEXT: .hidden __asan_check_store4_rn[[RN4]]
; CHECK-NEXT: __asan_check_store4_rn[[RN4]]:
; CHECK-NEXT: movq [[REG:.*]], %r8
; CHECK-NEXT: shrq $3, %r8
; CHECK-NEXT: orq $17592186044416, %r8
; CHECK-NEXT: movb (%r8), %r8b
; CHECK-NEXT: testb %r8b, %r8b
; CHECK-NEXT: jne [[EXTRA:.*]]
; CHECK-NEXT: [[RET:.*]]:
; CHECK-NEXT: retq
; CHECK-NEXT: [[EXTRA]]:
; CHECK-NEXT: pushq %rcx
; CHECK-NEXT: movq [[REG]], %rcx
; CHECK-NEXT: andl $7, %ecx
; CHECK-NEXT: addl $3, %ecx
; CHECK-NEXT: cmpl %r8d, %ecx
; CHECK-NEXT: popq %rcx
; CHECK-NEXT: jl [[RET]]
; CHECK-NEXT: movq [[REG:.*]], %rdi
; CHECK-NEXT: jmp __asan_report_store4
; CHECK: .type __asan_check_store8_rn[[RN8]],@function
; CHECK-NEXT: .weak __asan_check_store8_rn[[RN8]]
; CHECK-NEXT: .hidden __asan_check_store8_rn[[RN8]]
; CHECK-NEXT: __asan_check_store8_rn[[RN8]]:
; CHECK-NEXT: movq [[REG:.*]], %r8
; CHECK-NEXT: shrq $3, %r8
; CHECK-NEXT: orq $17592186044416, %r8{{.*}}
; CHECK-NEXT: cmpb $0, (%r8)
; CHECK-NEXT: jne [[FAIL:.*]]
; CHECK-NEXT: [[RET:.*]]:
; CHECK-NEXT: retq
; CHECK-NEXT: [[FAIL]]:
; CHECK-NEXT: movq [[REG:.*]], %rdi
; CHECK-NEXT: jmp __asan_report_store8
; CHECK: .type __asan_check_store16_rn[[RN16]],@function
; CHECK-NEXT: .weak __asan_check_store16_rn[[RN16]]
; CHECK-NEXT: .hidden __asan_check_store16_rn[[RN16]]
; CHECK-NEXT: __asan_check_store16_rn[[RN16]]:
; CHECK-NEXT: movq [[REG:.*]], %r8
; CHECK-NEXT: shrq $3, %r8
; CHECK-NEXT: orq $17592186044416, %r8{{.*}}
; CHECK-NEXT: cmpw $0, (%r8)
; CHECK-NEXT: jne [[FAIL:.*]]
; CHECK-NEXT: [[RET:.*]]:
; CHECK-NEXT: retq
; CHECK-NEXT: [[FAIL]]:
; CHECK-NEXT: movq [[REG:.*]], %rdi
; CHECK-NEXT: jmp __asan_report_store16
declare void @llvm.asan.check.memaccess(i8*, i32 immarg)