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Differential D108660

[AArch64][GlobalISel] Legalize narrow scalar FP arithmetic
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Authored by paquette on Aug 24 2021, 1:28 PM.

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Reviewers
aemerson
jroelofs
Commits
rGef8707574bbc: [AArch64][GlobalISel] Legalize narrow scalar FP arithmetic
Summary

Widen narrow fp arithmetic ops (e.g. G_FADD). When we don't have full FP16 support, widen to s32. Otherwise widen to s16.

https://godbolt.org/z/TbT9Pqa7e

Diff Detail

Event Timeline

paquette created this revision.Aug 24 2021, 1:28 PM
Herald added subscribers: hiraditya, kristof.beyls, rovka. · View Herald TranscriptAug 24 2021, 1:28 PM
paquette requested review of this revision.Aug 24 2021, 1:28 PM
Herald added a project: Restricted Project. · View Herald TranscriptAug 24 2021, 1:28 PM
paquette edited the summary of this revision. (Show Details)Aug 24 2021, 1:29 PM
jroelofs accepted this revision.Aug 24 2021, 1:47 PM
This revision is now accepted and ready to land.Aug 24 2021, 1:47 PM
This revision was landed with ongoing or failed builds.Aug 24 2021, 1:54 PM
Closed by commit rGef8707574bbc: [AArch64][GlobalISel] Legalize narrow scalar FP arithmetic (authored by paquette). · Explain Why
This revision was automatically updated to reflect the committed changes.
paquette added a commit: rGef8707574bbc: [AArch64][GlobalISel] Legalize narrow scalar FP arithmetic.
Harbormaster completed remote builds in B121039: Diff 368447.Aug 24 2021, 2:20 PM

Revision Contents

PathSize
llvm/
lib/
Target/
AArch64/
GISel/
3 lines
test/
CodeGen/
AArch64/
GlobalISel/
156 lines

Diff 368458

llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp

Show First 20 Lines • Show All 188 Lines • ▼ Show 20 LinesAArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
getActionDefinitionsBuilder( getActionDefinitionsBuilder(
{G_SADDE, G_SSUBE, G_UADDE, G_USUBE, G_SADDO, G_SSUBO, G_UADDO, G_USUBO}) {G_SADDE, G_SSUBE, G_UADDE, G_USUBE, G_SADDO, G_SSUBO, G_UADDO, G_USUBO})
.legalFor({{s32, s1}, {s64, s1}}) .legalFor({{s32, s1}, {s64, s1}})
.clampScalar(0, s32, s64) .clampScalar(0, s32, s64)
.widenScalarToNextPow2(0); .widenScalarToNextPow2(0);
getActionDefinitionsBuilder({G_FADD, G_FSUB, G_FMUL, G_FDIV, G_FNEG}) getActionDefinitionsBuilder({G_FADD, G_FSUB, G_FMUL, G_FDIV, G_FNEG})
.legalFor({s32, s64, v2s64, v4s32, v2s32}) .legalFor({MinFPScalar, s32, s64, v2s64, v4s32, v2s32})
.clampScalar(0, MinFPScalar, s64)
.clampNumElements(0, v2s32, v4s32) .clampNumElements(0, v2s32, v4s32)
.clampNumElements(0, v2s64, v2s64); .clampNumElements(0, v2s64, v2s64);
getActionDefinitionsBuilder(G_FREM).libcallFor({s32, s64}); getActionDefinitionsBuilder(G_FREM).libcallFor({s32, s64});
getActionDefinitionsBuilder({G_FCEIL, G_FABS, G_FSQRT, G_FFLOOR, G_FRINT, getActionDefinitionsBuilder({G_FCEIL, G_FABS, G_FSQRT, G_FFLOOR, G_FRINT,
G_FMA, G_INTRINSIC_TRUNC, G_INTRINSIC_ROUND, G_FMA, G_INTRINSIC_TRUNC, G_INTRINSIC_ROUND,
G_FNEARBYINT, G_INTRINSIC_LRINT}) G_FNEARBYINT, G_INTRINSIC_LRINT})
▲ Show 20 Lines • Show All 1,140 Lines • Show Last 20 Lines

llvm/test/CodeGen/AArch64/GlobalISel/legalize-fp-arith-fp16.mir

  • This file was added.
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple aarch64-unknown-unknown -verify-machineinstrs -run-pass=legalizer %s -o - | FileCheck %s --check-prefix=NO-FP16
# RUN: llc -mtriple aarch64-unknown-unknown -verify-machineinstrs -mattr=+fullfp16 -run-pass=legalizer %s -o - | FileCheck %s --check-prefix=FP16
...
---
name: fadd
tracksRegLiveness: true
body: |
bb.0:
liveins: $h0, $h1
; NO-FP16-LABEL: name: fadd
; NO-FP16: liveins: $h0, $h1
; NO-FP16: %x:_(s16) = COPY $h0
; NO-FP16: %y:_(s16) = COPY $h1
; NO-FP16: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT %x(s16)
; NO-FP16: [[FPEXT1:%[0-9]+]]:_(s32) = G_FPEXT %y(s16)
; NO-FP16: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[FPEXT]], [[FPEXT1]]
; NO-FP16: %op:_(s16) = G_FPTRUNC [[FADD]](s32)
; NO-FP16: $h0 = COPY %op(s16)
; NO-FP16: RET_ReallyLR implicit $h0
; FP16-LABEL: name: fadd
; FP16: liveins: $h0, $h1
; FP16: %x:_(s16) = COPY $h0
; FP16: %y:_(s16) = COPY $h1
; FP16: %op:_(s16) = G_FADD %x, %y
; FP16: $h0 = COPY %op(s16)
; FP16: RET_ReallyLR implicit $h0
%x:_(s16) = COPY $h0
%y:_(s16) = COPY $h1
%op:_(s16) = G_FADD %x, %y
$h0 = COPY %op(s16)
RET_ReallyLR implicit $h0
...
---
name: fsub
tracksRegLiveness: true
body: |
bb.0:
liveins: $h0, $h1
; NO-FP16-LABEL: name: fsub
; NO-FP16: liveins: $h0, $h1
; NO-FP16: %x:_(s16) = COPY $h0
; NO-FP16: %y:_(s16) = COPY $h1
; NO-FP16: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT %x(s16)
; NO-FP16: [[FPEXT1:%[0-9]+]]:_(s32) = G_FPEXT %y(s16)
; NO-FP16: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[FPEXT]], [[FPEXT1]]
; NO-FP16: %op:_(s16) = G_FPTRUNC [[FSUB]](s32)
; NO-FP16: $h0 = COPY %op(s16)
; NO-FP16: RET_ReallyLR implicit $h0
; FP16-LABEL: name: fsub
; FP16: liveins: $h0, $h1
; FP16: %x:_(s16) = COPY $h0
; FP16: %y:_(s16) = COPY $h1
; FP16: %op:_(s16) = G_FSUB %x, %y
; FP16: $h0 = COPY %op(s16)
; FP16: RET_ReallyLR implicit $h0
%x:_(s16) = COPY $h0
%y:_(s16) = COPY $h1
%op:_(s16) = G_FSUB %x, %y
$h0 = COPY %op(s16)
RET_ReallyLR implicit $h0
...
---
name: fmul
tracksRegLiveness: true
body: |
bb.0:
liveins: $h0, $h1
; NO-FP16-LABEL: name: fmul
; NO-FP16: liveins: $h0, $h1
; NO-FP16: %x:_(s16) = COPY $h0
; NO-FP16: %y:_(s16) = COPY $h1
; NO-FP16: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT %x(s16)
; NO-FP16: [[FPEXT1:%[0-9]+]]:_(s32) = G_FPEXT %y(s16)
; NO-FP16: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[FPEXT]], [[FPEXT1]]
; NO-FP16: %op:_(s16) = G_FPTRUNC [[FMUL]](s32)
; NO-FP16: $h0 = COPY %op(s16)
; NO-FP16: RET_ReallyLR implicit $h0
; FP16-LABEL: name: fmul
; FP16: liveins: $h0, $h1
; FP16: %x:_(s16) = COPY $h0
; FP16: %y:_(s16) = COPY $h1
; FP16: %op:_(s16) = G_FMUL %x, %y
; FP16: $h0 = COPY %op(s16)
; FP16: RET_ReallyLR implicit $h0
%x:_(s16) = COPY $h0
%y:_(s16) = COPY $h1
%op:_(s16) = G_FMUL %x, %y
$h0 = COPY %op(s16)
RET_ReallyLR implicit $h0
...
---
name: fdiv
tracksRegLiveness: true
body: |
bb.0:
liveins: $h0, $h1
; NO-FP16-LABEL: name: fdiv
; NO-FP16: liveins: $h0, $h1
; NO-FP16: %x:_(s16) = COPY $h0
; NO-FP16: %y:_(s16) = COPY $h1
; NO-FP16: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT %x(s16)
; NO-FP16: [[FPEXT1:%[0-9]+]]:_(s32) = G_FPEXT %y(s16)
; NO-FP16: [[FDIV:%[0-9]+]]:_(s32) = G_FDIV [[FPEXT]], [[FPEXT1]]
; NO-FP16: %op:_(s16) = G_FPTRUNC [[FDIV]](s32)
; NO-FP16: $h0 = COPY %op(s16)
; NO-FP16: RET_ReallyLR implicit $h0
; FP16-LABEL: name: fdiv
; FP16: liveins: $h0, $h1
; FP16: %x:_(s16) = COPY $h0
; FP16: %y:_(s16) = COPY $h1
; FP16: %op:_(s16) = G_FDIV %x, %y
; FP16: $h0 = COPY %op(s16)
; FP16: RET_ReallyLR implicit $h0
%x:_(s16) = COPY $h0
%y:_(s16) = COPY $h1
%op:_(s16) = G_FDIV %x, %y
$h0 = COPY %op(s16)
RET_ReallyLR implicit $h0
...
---
name: fneg
tracksRegLiveness: true
body: |
bb.0:
liveins: $h0
; NO-FP16-LABEL: name: fneg
; NO-FP16: liveins: $h0
; NO-FP16: %x:_(s16) = COPY $h0
; NO-FP16: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT %x(s16)
; NO-FP16: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[FPEXT]]
; NO-FP16: %op:_(s16) = G_FPTRUNC [[FNEG]](s32)
; NO-FP16: $h0 = COPY %op(s16)
; NO-FP16: RET_ReallyLR implicit $h0
; FP16-LABEL: name: fneg
; FP16: liveins: $h0
; FP16: %x:_(s16) = COPY $h0
; FP16: %op:_(s16) = G_FNEG %x
; FP16: $h0 = COPY %op(s16)
; FP16: RET_ReallyLR implicit $h0
%x:_(s16) = COPY $h0
%op:_(s16) = G_FNEG %x
$h0 = COPY %op(s16)
RET_ReallyLR implicit $h0
...