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Differential D108563

[GlobalISel] Translate @llvm.llround.* -> G_LLROUND
ClosedPublic

Authored by paquette on Aug 23 2021, 9:18 AM.

Details

Reviewers
aemerson
arsenm
jroelofs
Commits
rG6760e2a7bcb2: [GlobalISel] Translate @llvm.llround.* -> G_LLROUND
Summary

Translate it using IRTranslator::translateSimpleIntrinsic.

Diff Detail

Event Timeline

paquette created this revision.Aug 23 2021, 9:18 AM
Herald added subscribers: hiraditya, rovka. · View Herald TranscriptAug 23 2021, 9:18 AM
paquette requested review of this revision.Aug 23 2021, 9:18 AM
Herald added a project: Restricted Project. · View Herald TranscriptAug 23 2021, 9:18 AM
Herald added a subscriber: wdng. · View Herald Transcript
jroelofs accepted this revision.Aug 23 2021, 9:18 AM
This revision is now accepted and ready to land.Aug 23 2021, 9:18 AM
paquette added a child revision: D108564: [AArch64][GlobalISel] Legalize G_LLROUND for s64 + s32.Aug 23 2021, 9:41 AM
This revision was landed with ongoing or failed builds.Aug 23 2021, 9:43 AM
Closed by commit rG6760e2a7bcb2: [GlobalISel] Translate @llvm.llround.* -> G_LLROUND (authored by paquette). · Explain Why
This revision was automatically updated to reflect the committed changes.
paquette added a commit: rG6760e2a7bcb2: [GlobalISel] Translate @llvm.llround.* -> G_LLROUND.
Harbormaster completed remote builds in B120807: Diff 368125.Aug 23 2021, 9:46 AM

Revision Contents

PathSize
llvm/
lib/
CodeGen/
GlobalISel/
2 lines
test/
CodeGen/
AArch64/
GlobalISel/
13 lines

Diff 368125

llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp

Show First 20 Lines • Show All 1,759 Lines • ▼ Show 20 Lines switch (ID) {
case Intrinsic::vector_reduce_smin: case Intrinsic::vector_reduce_smin:
return TargetOpcode::G_VECREDUCE_SMIN; return TargetOpcode::G_VECREDUCE_SMIN;
case Intrinsic::vector_reduce_umax: case Intrinsic::vector_reduce_umax:
return TargetOpcode::G_VECREDUCE_UMAX; return TargetOpcode::G_VECREDUCE_UMAX;
case Intrinsic::vector_reduce_umin: case Intrinsic::vector_reduce_umin:
return TargetOpcode::G_VECREDUCE_UMIN; return TargetOpcode::G_VECREDUCE_UMIN;
case Intrinsic::lround: case Intrinsic::lround:
return TargetOpcode::G_LROUND; return TargetOpcode::G_LROUND;
case Intrinsic::llround:
return TargetOpcode::G_LLROUND;
} }
return Intrinsic::not_intrinsic; return Intrinsic::not_intrinsic;
} }
bool IRTranslator::translateSimpleIntrinsic(const CallInst &CI, bool IRTranslator::translateSimpleIntrinsic(const CallInst &CI,
Intrinsic::ID ID, Intrinsic::ID ID,
MachineIRBuilder &MIRBuilder) { MachineIRBuilder &MIRBuilder) {
▲ Show 20 Lines • Show All 1,538 Lines • Show Last 20 Lines

llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll

Show First 20 Lines • Show All 2,464 Lines • ▼ Show 20 Linesdefine i64 @lround(float %x) {
; CHECK: liveins: $s0 ; CHECK: liveins: $s0
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $s0 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $s0
; CHECK: [[LROUND:%[0-9]+]]:_(s64) = G_LROUND [[COPY]](s32) ; CHECK: [[LROUND:%[0-9]+]]:_(s64) = G_LROUND [[COPY]](s32)
; CHECK: $x0 = COPY [[LROUND]](s64) ; CHECK: $x0 = COPY [[LROUND]](s64)
; CHECK: RET_ReallyLR implicit $x0 ; CHECK: RET_ReallyLR implicit $x0
%lround = tail call i64 @llvm.lround.i64.f32(float %x) %lround = tail call i64 @llvm.lround.i64.f32(float %x)
ret i64 %lround ret i64 %lround
} }
declare i64 @llvm.llround.i64.f32(float) nounwind readnone
define i64 @llround(float %x) {
; CHECK-LABEL: name: llround
; CHECK: bb.1 (%ir-block.0):
; CHECK: liveins: $s0
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $s0
; CHECK: [[LLROUND:%[0-9]+]]:_(s64) = G_LLROUND [[COPY]](s32)
; CHECK: $x0 = COPY [[LLROUND]](s64)
; CHECK: RET_ReallyLR implicit $x0
%lround = tail call i64 @llvm.llround.i64.f32(float %x)
ret i64 %lround
}