[GlobalISel] Add G_LLROUND

[paquette]

Summary

Basically the same as G_LROUND. Handles the llvm.llround family of intrinsics.

Also add a helper function to the MachineVerifier for checking if all of the (virtual register) operands of an instruction are scalars. Seems like a useful thing to have.

[jroelofs]

LGTM

llvm/docs/GlobalISel/GenericOpcode.rst

 
 Returns the operand rounded to the nearest integer not larger in magnitude than the operand.
 
 G_INTRINSIC_ROUND
 ^^^^^^^^^^^^^^^^^
 
 Returns the operand rounded to the nearest integer.
 
-G_LROUND
-^^^^^^^^
+G_LROUND, G_LLROUND
+^^^^^^^^^^^^^^^^^^^
 
 Returns the source operand rounded to the nearest integer with ties away from
 zero.
 
 See the LLVM LangRef entry on '``llvm.lround.*'`` for details on behaviour.
 
 .. code-block:: none
 
   %rounded_32:_(s32) = G_LROUND %round_me:_(s64)
-  %rounded_64:_(s64) = G_LROUND %round_me:_(s64)
+  %rounded_64:_(s64) = G_LLROUND %round_me:_(s64)
 
 Vector Specific Operations
 --------------------------
 
 G_CONCAT_VECTORS
 ^^^^^^^^^^^^^^^^
 
 Concatenate two vectors to form a longer vector.

llvm/include/llvm/Support/TargetOpcodes.def

 
 /// Generic unsigned integer maximum.
 HANDLE_TARGET_OPCODE(G_UMAX)
 
 /// Generic integer absolute value.
 HANDLE_TARGET_OPCODE(G_ABS)
 
 HANDLE_TARGET_OPCODE(G_LROUND)
+HANDLE_TARGET_OPCODE(G_LLROUND)
 
 /// Generic BRANCH instruction. This is an unconditional branch.
 HANDLE_TARGET_OPCODE(G_BR)
 
 /// Generic branch to jump table entry.
 HANDLE_TARGET_OPCODE(G_BRJT)
 
 /// Generic insertelement.

llvm/include/llvm/Target/GenericOpcodes.td

 }
 
 def G_LROUND: GenericInstruction {
   let OutOperandList = (outs type0:$dst);
   let InOperandList = (ins type1:$src);
   let hasSideEffects = false;
 }
 
+def G_LLROUND: GenericInstruction {
+  let OutOperandList = (outs type0:$dst);
+  let InOperandList = (ins type1:$src);
+  let hasSideEffects = false;
+}
+
 //------------------------------------------------------------------------------
 // Binary ops.
 //------------------------------------------------------------------------------
 
 // Generic addition.
 def G_ADD : GenericInstruction {
   let OutOperandList = (outs type0:$dst);
   let InOperandList = (ins type0:$src1, type0:$src2);

llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td

 def : GINodeEquiv<G_FMINNUM, fminnum>;
 def : GINodeEquiv<G_FMAXNUM, fmaxnum>;
 def : GINodeEquiv<G_FMINNUM_IEEE, fminnum_ieee>;
 def : GINodeEquiv<G_FMAXNUM_IEEE, fmaxnum_ieee>;
 def : GINodeEquiv<G_READCYCLECOUNTER, readcyclecounter>;
 def : GINodeEquiv<G_ROTR, rotr>;
 def : GINodeEquiv<G_ROTL, rotl>;
 def : GINodeEquiv<G_LROUND, lround>;
+def : GINodeEquiv<G_LLROUND, llround>;
 
 def : GINodeEquiv<G_STRICT_FADD, strict_fadd>;
 def : GINodeEquiv<G_STRICT_FSUB, strict_fsub>;
 def : GINodeEquiv<G_STRICT_FMUL, strict_fmul>;
 def : GINodeEquiv<G_STRICT_FDIV, strict_fdiv>;
 def : GINodeEquiv<G_STRICT_FREM, strict_frem>;
 def : GINodeEquiv<G_STRICT_FMA, strict_fma>;
 def : GINodeEquiv<G_STRICT_FSQRT, strict_fsqrt>;

llvm/lib/CodeGen/MachineVerifier.cpp

struct MachineVerifier {
     LiveIntervals *LiveInts;
     LiveStacks *LiveStks;
     SlotIndexes *Indexes;
 
     void visitMachineFunctionBefore();
     void visitMachineBasicBlockBefore(const MachineBasicBlock *MBB);
     void visitMachineBundleBefore(const MachineInstr *MI);
 
+    /// Verify that all of \p MI's virtual register operands are scalars.
+    /// \returns True if all virtual register operands are scalar. False
+    /// otherwise.
+    bool verifyAllRegOpsScalar(const MachineInstr &MI,
+                               const MachineRegisterInfo &MRI);
     bool verifyVectorElementMatch(LLT Ty0, LLT Ty1, const MachineInstr *MI);
     void verifyPreISelGenericInstruction(const MachineInstr *MI);
     void visitMachineInstrBefore(const MachineInstr *MI);
     void visitMachineOperand(const MachineOperand *MO, unsigned MONum);
     void visitMachineBundleAfter(const MachineInstr *MI);
     void visitMachineBasicBlockAfter(const MachineBasicBlock *MBB);
     void visitMachineFunctionAfter();
 
void MachineVerifier::verifyInlineAsm(const MachineInstr *MI) {
   // All trailing operands must be implicit registers.
   for (unsigned e = MI->getNumOperands(); OpNo < e; ++OpNo) {
     const MachineOperand &MO = MI->getOperand(OpNo);
     if (!MO.isReg() || !MO.isImplicit())
       report("Expected implicit register after groups", &MO, OpNo);
   }
 }
 
+bool MachineVerifier::verifyAllRegOpsScalar(const MachineInstr &MI,
+                                            const MachineRegisterInfo &MRI) {
+  if (none_of(MI.explicit_operands(), [&MRI](const MachineOperand &Op) {
+        if (!Op.isReg())
+          return false;
+        const auto Reg = Op.getReg();
+        if (Reg.isPhysical())
+          return false;
+        return !MRI.getType(Reg).isScalar();
+      }))
+    return true;
+  report("All register operands must have scalar types", &MI);
+  return false;
+}
+
 /// Check that types are consistent when two operands need to have the same
 /// number of vector elements.
 /// \return true if the types are valid.
 bool MachineVerifier::verifyVectorElementMatch(LLT Ty0, LLT Ty1,
                                                const MachineInstr *MI) {
   if (Ty0.isVector() != Ty1.isVector()) {
     report("operand types must be all-vector or all-scalar", MI);
     // Generally we try to report as many issues as possible at once, but in
case TargetOpcode::G_ROTL: {
     LLT Src2Ty = MRI->getType(MI->getOperand(2).getReg());
     if (Src1Ty.isVector() != Src2Ty.isVector()) {
       report("Rotate requires operands to be either all scalars or all vectors",
              MI);
       break;
     }
     break;
   }
-
+  case TargetOpcode::G_LLROUND:
   case TargetOpcode::G_LROUND: {
-    if (!MRI->getType(MI->getOperand(0).getReg()).isScalar() ||
-        !MRI->getType(MI->getOperand(1).getReg()).isScalar())
-      report("lround only supports scalars", MI);
+    verifyAllRegOpsScalar(*MI, *MRI);
     break;
   }
-
   default:
     break;
   }
 }
 
 void MachineVerifier::visitMachineInstrBefore(const MachineInstr *MI) {
   const MCInstrDesc &MCID = MI->getDesc();
   if (MI->getNumOperands() < MCID.getNumOperands()) {

llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir

 # DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
 # DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
 # DEBUG-NEXT: G_ABS (opcode {{[0-9]+}}): 1 type index, 0 imm indices
 # DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
 # DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
 # DEBUG-NEXT: G_LROUND (opcode {{[0-9]+}}): 2 type indices, 0 imm indices
 # DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined
 # DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined
+# DEBUG-NEXT: G_LLROUND (opcode {{[0-9]+}}): 2 type indices, 0 imm indices
+# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined
+# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined
 # DEBUG-NEXT: G_BR (opcode {{[0-9]+}}): 0 type indices, 0 imm indices
 # DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined
 # DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined
 # DEBUG-NEXT: G_BRJT (opcode {{[0-9]+}}): 2 type indices
 # DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
 # DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
 # DEBUG-NEXT: G_INSERT_VECTOR_ELT (opcode {{[0-9]+}}): 3 type indices, 0 imm indices
 # DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected

llvm/test/MachineVerifier/test_g_llround.mir

+#RUN: not --crash llc -march=aarch64 -o - -global-isel -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s
+# REQUIRES: aarch64-registered-target
+
+---
+name:            test_llround
+legalized:       true
+regBankSelected: false
+selected:        false
+tracksRegLiveness: true
+liveins:
+body:             |
+  bb.0:
+    liveins: $x0, $q0
+    %ptr:_(p0) = COPY $x0
+    %vector:_(<2 x s64>) = COPY $q0
+
+    ; CHECK: Bad machine code: All register operands must have scalar types
+    ; CHECK: instruction: %no_ptrs:_(s64) = G_LROUND %ptr:_(p0)
+    %no_ptrs:_(s64) = G_LROUND %ptr:_(p0)
+
+    ; CHECK: Bad machine code: All register operands must have scalar types
+    ; CHECK: instruction: %no_vectors:_(s64) = G_LROUND %vector:_(<2 x s64>)
+    %no_vectors:_(s64) = G_LROUND %vector:_(<2 x s64>)

llvm/test/MachineVerifier/test_g_lround.mir

 #RUN: not --crash llc -march=aarch64 -o - -global-isel -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s
 # REQUIRES: aarch64-registered-target
 
 ---
 name:            test_lround
 legalized:       true
 regBankSelected: false
 selected:        false
 tracksRegLiveness: true
 liveins:
 body:             |
   bb.0:
     liveins: $x0, $q0
     %ptr:_(p0) = COPY $x0
     %vector:_(<2 x s64>) = COPY $q0
 
-    ; CHECK: Bad machine code: lround only supports scalars
+    ; CHECK: Bad machine code: All register operands must have scalar types
     ; CHECK: instruction: %no_ptrs:_(s32) = G_LROUND %ptr:_(p0)
     %no_ptrs:_(s32) = G_LROUND %ptr:_(p0)
 
-    ; CHECK: Bad machine code: lround only supports scalars
+    ; CHECK: Bad machine code: All register operands must have scalar types
     ; CHECK: instruction: %no_vectors:_(s32) = G_LROUND %vector:_(<2 x s64>)
     %no_vectors:_(s32) = G_LROUND %vector:_(<2 x s64>)