[AArch64][GlobalISel] Legalize scalar G_FMINNUM + G_FMAXNUM

[paquette]

Summary

For subtargets with full FP16, this is legal for s16, s32, and s64. Without full FP16, it's legal for s32 and s64.

For s128, this is a libcall.

We also support some vector types, but for now, let's just support scalars.

[aemerson]

llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp

734–735

Is this actually needed? We don't support any non-pow-2 FP types right?

[paquette]

llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp

734–735

Yeah actually I think all we need to do is widen from s16 if full 16-bit FP support isn't available.

https://godbolt.org/z/3n4WoMaWd

[paquette]

Replace pow-2 widening stuff with minScalar(0, MinFPScalar).

llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp

getActionDefinitionsBuilder(G_CTPOP)
                   {v4s16, v4s16},
                   {v8s16, v8s16}});
 
   // TODO: Vector types.
   getActionDefinitionsBuilder({G_SADDSAT, G_SSUBSAT}).lowerIf(isScalar(0));
 
   getActionDefinitionsBuilder(G_ISNAN).lower();
 
+  // TODO: Vector types.
+  getActionDefinitionsBuilder({G_FMAXNUM, G_FMINNUM})
+      .legalFor({MinFPScalar, s32, s64})
+      .libcallFor({s128})
+      .minScalar(0, MinFPScalar);
+
   getLegacyLegalizerInfo().computeTables();
   verify(*ST.getInstrInfo());
 }
 
 bool AArch64LegalizerInfo::legalizeCustom(LegalizerHelper &Helper,
                                           MachineInstr &MI) const {
   MachineIRBuilder &MIRBuilder = Helper.MIRBuilder;
   MachineRegisterInfo &MRI = *MIRBuilder.getMRI();

llvm/test/CodeGen/AArch64/GlobalISel/legalize-fmaxnum.mir

+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=aarch64-unknown-unknown -run-pass=legalizer -mattr=+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=FP16
+# RUN: llc -mtriple=aarch64-unknown-unknown -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=NO-FP16
+...
+---
+name:            s16_legal_with_full_fp16
+alignment:       4
+body:             |
+  bb.0:
+    liveins: $h0, $h1
+    ; FP16-LABEL: name: s16_legal_with_full_fp16
+    ; FP16: %a:_(s16) = COPY $h0
+    ; FP16: %b:_(s16) = COPY $h1
+    ; FP16: %maxnum:_(s16) = G_FMAXNUM %a, %b
+    ; FP16: $h0 = COPY %maxnum(s16)
+    ; FP16: RET_ReallyLR implicit $h0
+    ; NO-FP16-LABEL: name: s16_legal_with_full_fp16
+    ; NO-FP16: %a:_(s16) = COPY $h0
+    ; NO-FP16: %b:_(s16) = COPY $h1
+    ; NO-FP16: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT %a(s16)
+    ; NO-FP16: [[FPEXT1:%[0-9]+]]:_(s32) = G_FPEXT %b(s16)
+    ; NO-FP16: [[FMAXNUM:%[0-9]+]]:_(s32) = G_FMAXNUM [[FPEXT]], [[FPEXT1]]
+    ; NO-FP16: %maxnum:_(s16) = G_FPTRUNC [[FMAXNUM]](s32)
+    ; NO-FP16: $h0 = COPY %maxnum(s16)
+    ; NO-FP16: RET_ReallyLR implicit $h0
+    %a:_(s16) = COPY $h0
+    %b:_(s16) = COPY $h1
+    %maxnum:_(s16) = G_FMAXNUM %a, %b
+    $h0 = COPY %maxnum(s16)
+    RET_ReallyLR implicit $h0
+
+...
+---
+name:            s32_legal
+alignment:       4
+body:             |
+  bb.0:
+    liveins: $s0, $s1
+    ; FP16-LABEL: name: s32_legal
+    ; FP16: %a:_(s32) = COPY $s0
+    ; FP16: %b:_(s32) = COPY $s1
+    ; FP16: %maxnum:_(s32) = G_FMAXNUM %a, %b
+    ; FP16: $s0 = COPY %maxnum(s32)
+    ; FP16: RET_ReallyLR implicit $s0
+    ; NO-FP16-LABEL: name: s32_legal
+    ; NO-FP16: %a:_(s32) = COPY $s0
+    ; NO-FP16: %b:_(s32) = COPY $s1
+    ; NO-FP16: %maxnum:_(s32) = G_FMAXNUM %a, %b
+    ; NO-FP16: $s0 = COPY %maxnum(s32)
+    ; NO-FP16: RET_ReallyLR implicit $s0
+    %a:_(s32) = COPY $s0
+    %b:_(s32) = COPY $s1
+    %maxnum:_(s32) = G_FMAXNUM %a, %b
+    $s0 = COPY %maxnum(s32)
+    RET_ReallyLR implicit $s0
+
+...
+---
+name:            s64_legal
+alignment:       4
+body:             |
+  bb.0:
+    liveins: $d0, $d1
+    ; FP16-LABEL: name: s64_legal
+    ; FP16: %a:_(s64) = COPY $d0
+    ; FP16: %b:_(s64) = COPY $d1
+    ; FP16: %maxnum:_(s64) = G_FMAXNUM %a, %b
+    ; FP16: $d0 = COPY %maxnum(s64)
+    ; FP16: RET_ReallyLR implicit $d0
+    ; NO-FP16-LABEL: name: s64_legal
+    ; NO-FP16: %a:_(s64) = COPY $d0
+    ; NO-FP16: %b:_(s64) = COPY $d1
+    ; NO-FP16: %maxnum:_(s64) = G_FMAXNUM %a, %b
+    ; NO-FP16: $d0 = COPY %maxnum(s64)
+    ; NO-FP16: RET_ReallyLR implicit $d0
+    %a:_(s64) = COPY $d0
+    %b:_(s64) = COPY $d1
+    %maxnum:_(s64) = G_FMAXNUM %a, %b
+    $d0 = COPY %maxnum(s64)
+    RET_ReallyLR implicit $d0
+
+...
+---
+name:            s128_libcall
+alignment:       4
+body:             |
+  bb.0:
+    liveins: $q0, $q1
+    ; FP16-LABEL: name: s128_libcall
+    ; FP16: %a:_(s128) = COPY $q0
+    ; FP16: %b:_(s128) = COPY $q1
+    ; FP16: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
+    ; FP16: $q0 = COPY %a(s128)
+    ; FP16: $q1 = COPY %b(s128)
+    ; FP16: BL &fmaxl, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $q0, implicit $q1, implicit-def $q0
+    ; FP16: %maxnum:_(s128) = COPY $q0
+    ; FP16: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+    ; FP16: $q0 = COPY %maxnum(s128)
+    ; FP16: RET_ReallyLR implicit $q0
+    ; NO-FP16-LABEL: name: s128_libcall
+    ; NO-FP16: %a:_(s128) = COPY $q0
+    ; NO-FP16: %b:_(s128) = COPY $q1
+    ; NO-FP16: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
+    ; NO-FP16: $q0 = COPY %a(s128)
+    ; NO-FP16: $q1 = COPY %b(s128)
+    ; NO-FP16: BL &fmaxl, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $q0, implicit $q1, implicit-def $q0
+    ; NO-FP16: %maxnum:_(s128) = COPY $q0
+    ; NO-FP16: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+    ; NO-FP16: $q0 = COPY %maxnum(s128)
+    ; NO-FP16: RET_ReallyLR implicit $q0
+    %a:_(s128) = COPY $q0
+    %b:_(s128) = COPY $q1
+    %maxnum:_(s128) = G_FMAXNUM %a, %b
+    $q0 = COPY %maxnum(s128)
+    RET_ReallyLR implicit $q0

llvm/test/CodeGen/AArch64/GlobalISel/legalize-fminnum.mir

+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=aarch64-unknown-unknown -run-pass=legalizer -mattr=+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=FP16
+# RUN: llc -mtriple=aarch64-unknown-unknown -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=NO-FP16
+...
+---
+name:            s16_legal_with_full_fp16
+alignment:       4
+body:             |
+  bb.0:
+    liveins: $h0, $h1
+    ; FP16-LABEL: name: s16_legal_with_full_fp16
+    ; FP16: %a:_(s16) = COPY $h0
+    ; FP16: %b:_(s16) = COPY $h1
+    ; FP16: %minnum:_(s16) = G_FMINNUM %a, %b
+    ; FP16: $h0 = COPY %minnum(s16)
+    ; FP16: RET_ReallyLR implicit $h0
+    ; NO-FP16-LABEL: name: s16_legal_with_full_fp16
+    ; NO-FP16: %a:_(s16) = COPY $h0
+    ; NO-FP16: %b:_(s16) = COPY $h1
+    ; NO-FP16: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT %a(s16)
+    ; NO-FP16: [[FPEXT1:%[0-9]+]]:_(s32) = G_FPEXT %b(s16)
+    ; NO-FP16: [[FMINNUM:%[0-9]+]]:_(s32) = G_FMINNUM [[FPEXT]], [[FPEXT1]]
+    ; NO-FP16: %minnum:_(s16) = G_FPTRUNC [[FMINNUM]](s32)
+    ; NO-FP16: $h0 = COPY %minnum(s16)
+    ; NO-FP16: RET_ReallyLR implicit $h0
+    %a:_(s16) = COPY $h0
+    %b:_(s16) = COPY $h1
+    %minnum:_(s16) = G_FMINNUM %a, %b
+    $h0 = COPY %minnum(s16)
+    RET_ReallyLR implicit $h0
+
+...
+---
+name:            s32_legal
+alignment:       4
+body:             |
+  bb.0:
+    liveins: $s0, $s1
+    ; FP16-LABEL: name: s32_legal
+    ; FP16: %a:_(s32) = COPY $s0
+    ; FP16: %b:_(s32) = COPY $s1
+    ; FP16: %minnum:_(s32) = G_FMINNUM %a, %b
+    ; FP16: $s0 = COPY %minnum(s32)
+    ; FP16: RET_ReallyLR implicit $s0
+    ; NO-FP16-LABEL: name: s32_legal
+    ; NO-FP16: %a:_(s32) = COPY $s0
+    ; NO-FP16: %b:_(s32) = COPY $s1
+    ; NO-FP16: %minnum:_(s32) = G_FMINNUM %a, %b
+    ; NO-FP16: $s0 = COPY %minnum(s32)
+    ; NO-FP16: RET_ReallyLR implicit $s0
+    %a:_(s32) = COPY $s0
+    %b:_(s32) = COPY $s1
+    %minnum:_(s32) = G_FMINNUM %a, %b
+    $s0 = COPY %minnum(s32)
+    RET_ReallyLR implicit $s0
+
+...
+---
+name:            s64_legal
+alignment:       4
+body:             |
+  bb.0:
+    liveins: $d0, $d1
+    ; FP16-LABEL: name: s64_legal
+    ; FP16: %a:_(s64) = COPY $d0
+    ; FP16: %b:_(s64) = COPY $d1
+    ; FP16: %minnum:_(s64) = G_FMINNUM %a, %b
+    ; FP16: $d0 = COPY %minnum(s64)
+    ; FP16: RET_ReallyLR implicit $d0
+    ; NO-FP16-LABEL: name: s64_legal
+    ; NO-FP16: %a:_(s64) = COPY $d0
+    ; NO-FP16: %b:_(s64) = COPY $d1
+    ; NO-FP16: %minnum:_(s64) = G_FMINNUM %a, %b
+    ; NO-FP16: $d0 = COPY %minnum(s64)
+    ; NO-FP16: RET_ReallyLR implicit $d0
+    %a:_(s64) = COPY $d0
+    %b:_(s64) = COPY $d1
+    %minnum:_(s64) = G_FMINNUM %a, %b
+    $d0 = COPY %minnum(s64)
+    RET_ReallyLR implicit $d0
+
+...
+---
+name:            s128_libcall
+alignment:       4
+body:             |
+  bb.0:
+    liveins: $q0, $q1
+    ; FP16-LABEL: name: s128_libcall
+    ; FP16: %a:_(s128) = COPY $q0
+    ; FP16: %b:_(s128) = COPY $q1
+    ; FP16: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
+    ; FP16: $q0 = COPY %a(s128)
+    ; FP16: $q1 = COPY %b(s128)
+    ; FP16: BL &fminl, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $q0, implicit $q1, implicit-def $q0
+    ; FP16: %minnum:_(s128) = COPY $q0
+    ; FP16: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+    ; FP16: $q0 = COPY %minnum(s128)
+    ; FP16: RET_ReallyLR implicit $q0
+    ; NO-FP16-LABEL: name: s128_libcall
+    ; NO-FP16: %a:_(s128) = COPY $q0
+    ; NO-FP16: %b:_(s128) = COPY $q1
+    ; NO-FP16: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
+    ; NO-FP16: $q0 = COPY %a(s128)
+    ; NO-FP16: $q1 = COPY %b(s128)
+    ; NO-FP16: BL &fminl, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $q0, implicit $q1, implicit-def $q0
+    ; NO-FP16: %minnum:_(s128) = COPY $q0
+    ; NO-FP16: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+    ; NO-FP16: $q0 = COPY %minnum(s128)
+    ; NO-FP16: RET_ReallyLR implicit $q0
+    %a:_(s128) = COPY $q0
+    %b:_(s128) = COPY $q1
+    %minnum:_(s128) = G_FMINNUM %a, %b
+    $q0 = COPY %minnum(s128)
+    RET_ReallyLR implicit $q0

llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir

 # DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
 # DEBUG-NEXT: G_FCOPYSIGN (opcode {{[0-9]+}}): 2 type indices
 # DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined
 # DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined
 # DEBUG-NEXT: G_FCANONICALIZE (opcode {{[0-9]+}}): 1 type index, 0 imm indices
 # DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined
 # DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined
 # DEBUG-NEXT: G_FMINNUM (opcode {{[0-9]+}}): 1 type index
-# DEBUG: .. type index coverage check SKIPPED: no rules defined
-# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined
+# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}}
+# DEBUG-NEXT: .. the first uncovered type index: 1, OK
+# DEBUG-NEXT: .. the first uncovered imm index: 0, OK
 # DEBUG-NEXT: G_FMAXNUM (opcode {{[0-9]+}}): 1 type index
-# DEBUG: .. type index coverage check SKIPPED: no rules defined
-# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined
+# DEBUG-NEXT: .. the first uncovered type index: 1, OK
+# DEBUG-NEXT: .. the first uncovered imm index: 0, OK
 # DEBUG-NEXT: G_FMINNUM_IEEE (opcode {{[0-9]+}}): 1 type index
 # DEBUG: .. type index coverage check SKIPPED: no rules defined
 # DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined
 # DEBUG-NEXT: G_FMAXNUM_IEEE (opcode {{[0-9]+}}): 1 type index
 # DEBUG: .. type index coverage check SKIPPED: no rules defined
 # DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined
 # DEBUG-NEXT: G_FMINIMUM (opcode {{[0-9]+}}): 1 type index
 # DEBUG: .. type index coverage check SKIPPED: no rules defined