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Differential D107604

[AArch64][GlobalISel] Widen G_IMPLICIT_DEF and G_FREEZE before clamping
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Authored by paquette on Aug 5 2021, 2:53 PM.

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aemerson
jroelofs
Commits
rG562c8e14d9f1: [AArch64][GlobalISel] Widen G_IMPLICIT_DEF and G_FREEZE before clamping
Summary

Similar to other cleanup commits which widen instructions before clamping during legalization. Purpose of this is to avoid weird type breakdowns.

In terms of G_IMPLICIT_DEF, this simplifies legalization for other instructions. The legalizer has to emit G_IMPLICIT_DEF to legalize certain instructions, so this can help with emitting merges elsewhere.

Diff Detail

Event Timeline

paquette created this revision.Aug 5 2021, 2:53 PM
Herald added subscribers: danielkiss, hiraditya, kristof.beyls, rovka. · View Herald TranscriptAug 5 2021, 2:53 PM
paquette requested review of this revision.Aug 5 2021, 2:53 PM
Herald added a project: Restricted Project. · View Herald TranscriptAug 5 2021, 2:53 PM
jroelofs accepted this revision.Aug 5 2021, 3:17 PM

LGTM

llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
83

This widen-then-clamp pattern seems really common. Maybe that ought to be a first-class operation?

This revision is now accepted and ready to land.Aug 5 2021, 3:17 PM
Harbormaster completed remote builds in B118270: Diff 364623.Aug 5 2021, 3:52 PM
paquette added inline comments.Aug 5 2021, 6:17 PM
llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
83

Yeah, I think so too. I just wanted to audit everything first.

This revision was landed with ongoing or failed builds.Aug 5 2021, 6:25 PM
Closed by commit rG562c8e14d9f1: [AArch64][GlobalISel] Widen G_IMPLICIT_DEF and G_FREEZE before clamping (authored by paquette). · Explain Why
This revision was automatically updated to reflect the committed changes.
paquette added a commit: rG562c8e14d9f1: [AArch64][GlobalISel] Widen G_IMPLICIT_DEF and G_FREEZE before clamping.

Revision Contents

PathSize
llvm/
lib/
Target/
AArch64/
GISel/
2 lines
test/
CodeGen/
AArch64/
GlobalISel/
69 lines
4 lines
11 lines

Diff 364668

llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp

Show First 20 Lines • Show All 74 Lines • ▼ Show 20 LinesAArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
// Some instructions only support s16 if the subtarget has full 16-bit FP // Some instructions only support s16 if the subtarget has full 16-bit FP
// support. // support.
const bool HasFP16 = ST.hasFullFP16(); const bool HasFP16 = ST.hasFullFP16();
const LLT &MinFPScalar = HasFP16 ? s16 : s32; const LLT &MinFPScalar = HasFP16 ? s16 : s32;
getActionDefinitionsBuilder({G_IMPLICIT_DEF, G_FREEZE}) getActionDefinitionsBuilder({G_IMPLICIT_DEF, G_FREEZE})
.legalFor({p0, s1, s8, s16, s32, s64}) .legalFor({p0, s1, s8, s16, s32, s64})
.legalFor(PackedVectorAllTypeList) .legalFor(PackedVectorAllTypeList)
.widenScalarToNextPow2(0)
jroelofsUnsubmitted
Not Done
ReplyInline Actions

This widen-then-clamp pattern seems really common. Maybe that ought to be a first-class operation?

jroelofs: This widen-then-clamp pattern seems really common. Maybe that ought to be a first-class…
paquetteAuthorUnsubmitted
Done
ReplyInline Actions

Yeah, I think so too. I just wanted to audit everything first.

paquette: Yeah, I think so too. I just wanted to audit everything first.
.clampScalar(0, s8, s64) .clampScalar(0, s8, s64)
.widenScalarToNextPow2(0, 8)
.fewerElementsIf( .fewerElementsIf(
[=](const LegalityQuery &Query) { [=](const LegalityQuery &Query) {
return Query.Types[0].isVector() && return Query.Types[0].isVector() &&
(Query.Types[0].getElementType() != s64 || (Query.Types[0].getElementType() != s64 ||
Query.Types[0].getNumElements() != 2); Query.Types[0].getNumElements() != 2);
}, },
[=](const LegalityQuery &Query) { [=](const LegalityQuery &Query) {
LLT EltTy = Query.Types[0].getElementType(); LLT EltTy = Query.Types[0].getElementType();
▲ Show 20 Lines • Show All 1,220 Lines • Show Last 20 Lines

llvm/test/CodeGen/AArch64/GlobalISel/legalize-cmp.mir

Show First 20 Lines • Show All 113 Lines • ▼ Show 20 Lines
--- ---
name: test_s88_eq name: test_s88_eq
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
; CHECK-LABEL: name: test_s88_eq ; CHECK-LABEL: name: test_s88_eq
; CHECK: bb.0: ; CHECK: bb.0:
; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000) ; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
; CHECK: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF ; CHECK: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
; CHECK: [[UV:%[0-9]+]]:_(s8), [[UV1:%[0-9]+]]:_(s8), [[UV2:%[0-9]+]]:_(s8), [[UV3:%[0-9]+]]:_(s8), [[UV4:%[0-9]+]]:_(s8), [[UV5:%[0-9]+]]:_(s8), [[UV6:%[0-9]+]]:_(s8), [[UV7:%[0-9]+]]:_(s8) = G_UNMERGE_VALUES [[DEF]](s64) ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
; CHECK: [[UV8:%[0-9]+]]:_(s8), [[UV9:%[0-9]+]]:_(s8), [[UV10:%[0-9]+]]:_(s8), [[UV11:%[0-9]+]]:_(s8), [[UV12:%[0-9]+]]:_(s8), [[UV13:%[0-9]+]]:_(s8), [[UV14:%[0-9]+]]:_(s8), [[UV15:%[0-9]+]]:_(s8) = G_UNMERGE_VALUES [[DEF]](s64) ; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 16777215
; CHECK: [[UV16:%[0-9]+]]:_(s8), [[UV17:%[0-9]+]]:_(s8), [[UV18:%[0-9]+]]:_(s8), [[UV19:%[0-9]+]]:_(s8), [[UV20:%[0-9]+]]:_(s8), [[UV21:%[0-9]+]]:_(s8), [[UV22:%[0-9]+]]:_(s8), [[UV23:%[0-9]+]]:_(s8) = G_UNMERGE_VALUES [[DEF]](s64) ; CHECK: [[AND:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C]]
; CHECK: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 0 ; CHECK: [[AND1:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C1]]
; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV]](s8), [[UV1]](s8), [[UV2]](s8), [[UV3]](s8), [[UV4]](s8), [[UV5]](s8), [[UV6]](s8), [[UV7]](s8) ; CHECK: [[AND2:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C]]
; CHECK: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV16]](s8), [[UV17]](s8), [[UV18]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8) ; CHECK: [[AND3:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C1]]
; CHECK: [[UV24:%[0-9]+]]:_(s8), [[UV25:%[0-9]+]]:_(s8), [[UV26:%[0-9]+]]:_(s8), [[UV27:%[0-9]+]]:_(s8), [[UV28:%[0-9]+]]:_(s8), [[UV29:%[0-9]+]]:_(s8), [[UV30:%[0-9]+]]:_(s8), [[UV31:%[0-9]+]]:_(s8) = G_UNMERGE_VALUES [[DEF]](s64) ; CHECK: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV8]](s8), [[UV9]](s8), [[UV10]](s8), [[UV11]](s8), [[UV12]](s8), [[UV13]](s8), [[UV14]](s8), [[UV15]](s8) ; CHECK: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[AND]], [[AND2]]
; CHECK: [[MV3:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV24]](s8), [[UV25]](s8), [[UV26]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8) ; CHECK: [[XOR1:%[0-9]+]]:_(s64) = G_XOR [[AND1]], [[AND3]]
; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[MV]], [[MV2]]
; CHECK: [[XOR1:%[0-9]+]]:_(s64) = G_XOR [[MV1]], [[MV3]]
; CHECK: [[OR:%[0-9]+]]:_(s64) = G_OR [[XOR]], [[XOR1]] ; CHECK: [[OR:%[0-9]+]]:_(s64) = G_OR [[XOR]], [[XOR1]]
; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[OR]](s64), [[C1]] ; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[OR]](s64), [[C2]]
; CHECK: %cmp:_(s1) = G_TRUNC [[ICMP]](s32) ; CHECK: %cmp:_(s1) = G_TRUNC [[ICMP]](s32)
; CHECK: G_BRCOND %cmp(s1), %bb.1 ; CHECK: G_BRCOND %cmp(s1), %bb.1
; CHECK: G_BR %bb.2 ; CHECK: G_BR %bb.2
; CHECK: bb.1: ; CHECK: bb.1:
; CHECK: successors: ; CHECK: successors:
; CHECK: bb.2: ; CHECK: bb.2:
; CHECK: RET_ReallyLR ; CHECK: RET_ReallyLR
bb.1: bb.1:
Show All 11 Lines
--- ---
name: test_s88_ne name: test_s88_ne
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
; CHECK-LABEL: name: test_s88_ne ; CHECK-LABEL: name: test_s88_ne
; CHECK: bb.0: ; CHECK: bb.0:
; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000) ; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
; CHECK: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF ; CHECK: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
; CHECK: [[UV:%[0-9]+]]:_(s8), [[UV1:%[0-9]+]]:_(s8), [[UV2:%[0-9]+]]:_(s8), [[UV3:%[0-9]+]]:_(s8), [[UV4:%[0-9]+]]:_(s8), [[UV5:%[0-9]+]]:_(s8), [[UV6:%[0-9]+]]:_(s8), [[UV7:%[0-9]+]]:_(s8) = G_UNMERGE_VALUES [[DEF]](s64) ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
; CHECK: [[UV8:%[0-9]+]]:_(s8), [[UV9:%[0-9]+]]:_(s8), [[UV10:%[0-9]+]]:_(s8), [[UV11:%[0-9]+]]:_(s8), [[UV12:%[0-9]+]]:_(s8), [[UV13:%[0-9]+]]:_(s8), [[UV14:%[0-9]+]]:_(s8), [[UV15:%[0-9]+]]:_(s8) = G_UNMERGE_VALUES [[DEF]](s64) ; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 16777215
; CHECK: [[UV16:%[0-9]+]]:_(s8), [[UV17:%[0-9]+]]:_(s8), [[UV18:%[0-9]+]]:_(s8), [[UV19:%[0-9]+]]:_(s8), [[UV20:%[0-9]+]]:_(s8), [[UV21:%[0-9]+]]:_(s8), [[UV22:%[0-9]+]]:_(s8), [[UV23:%[0-9]+]]:_(s8) = G_UNMERGE_VALUES [[DEF]](s64) ; CHECK: [[AND:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C]]
; CHECK: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 0 ; CHECK: [[AND1:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C1]]
; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV]](s8), [[UV1]](s8), [[UV2]](s8), [[UV3]](s8), [[UV4]](s8), [[UV5]](s8), [[UV6]](s8), [[UV7]](s8) ; CHECK: [[AND2:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C]]
; CHECK: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV16]](s8), [[UV17]](s8), [[UV18]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8) ; CHECK: [[AND3:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C1]]
; CHECK: [[UV24:%[0-9]+]]:_(s8), [[UV25:%[0-9]+]]:_(s8), [[UV26:%[0-9]+]]:_(s8), [[UV27:%[0-9]+]]:_(s8), [[UV28:%[0-9]+]]:_(s8), [[UV29:%[0-9]+]]:_(s8), [[UV30:%[0-9]+]]:_(s8), [[UV31:%[0-9]+]]:_(s8) = G_UNMERGE_VALUES [[DEF]](s64) ; CHECK: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV8]](s8), [[UV9]](s8), [[UV10]](s8), [[UV11]](s8), [[UV12]](s8), [[UV13]](s8), [[UV14]](s8), [[UV15]](s8) ; CHECK: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[AND]], [[AND2]]
; CHECK: [[MV3:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV24]](s8), [[UV25]](s8), [[UV26]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8) ; CHECK: [[XOR1:%[0-9]+]]:_(s64) = G_XOR [[AND1]], [[AND3]]
; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[MV]], [[MV2]]
; CHECK: [[XOR1:%[0-9]+]]:_(s64) = G_XOR [[MV1]], [[MV3]]
; CHECK: [[OR:%[0-9]+]]:_(s64) = G_OR [[XOR]], [[XOR1]] ; CHECK: [[OR:%[0-9]+]]:_(s64) = G_OR [[XOR]], [[XOR1]]
; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[OR]](s64), [[C1]] ; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[OR]](s64), [[C2]]
; CHECK: %cmp:_(s1) = G_TRUNC [[ICMP]](s32) ; CHECK: %cmp:_(s1) = G_TRUNC [[ICMP]](s32)
; CHECK: G_BRCOND %cmp(s1), %bb.1 ; CHECK: G_BRCOND %cmp(s1), %bb.1
; CHECK: G_BR %bb.2 ; CHECK: G_BR %bb.2
; CHECK: bb.1: ; CHECK: bb.1:
; CHECK: successors: ; CHECK: successors:
; CHECK: bb.2: ; CHECK: bb.2:
; CHECK: RET_ReallyLR ; CHECK: RET_ReallyLR
bb.1: bb.1:
Show All 11 Lines
--- ---
name: test_s96_eq name: test_s96_eq
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
; CHECK-LABEL: name: test_s96_eq ; CHECK-LABEL: name: test_s96_eq
; CHECK: bb.0: ; CHECK: bb.0:
; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000) ; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
; CHECK: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF ; CHECK: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF]](s64) ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
; CHECK: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF]](s64) ; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967295
; CHECK: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF]](s64) ; CHECK: [[AND:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C]]
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; CHECK: [[AND1:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C1]]
; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV]](s32), [[UV1]](s32) ; CHECK: [[AND2:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C]]
; CHECK: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV4]](s32), [[C]](s32) ; CHECK: [[AND3:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C1]]
; CHECK: [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF]](s64) ; CHECK: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV2]](s32), [[UV3]](s32) ; CHECK: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[AND]], [[AND2]]
; CHECK: [[MV3:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV6]](s32), [[C]](s32) ; CHECK: [[XOR1:%[0-9]+]]:_(s64) = G_XOR [[AND1]], [[AND3]]
; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[MV]], [[MV2]]
; CHECK: [[XOR1:%[0-9]+]]:_(s64) = G_XOR [[MV1]], [[MV3]]
; CHECK: [[OR:%[0-9]+]]:_(s64) = G_OR [[XOR]], [[XOR1]] ; CHECK: [[OR:%[0-9]+]]:_(s64) = G_OR [[XOR]], [[XOR1]]
; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[OR]](s64), [[C1]] ; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[OR]](s64), [[C2]]
; CHECK: %cmp:_(s1) = G_TRUNC [[ICMP]](s32) ; CHECK: %cmp:_(s1) = G_TRUNC [[ICMP]](s32)
; CHECK: G_BRCOND %cmp(s1), %bb.1 ; CHECK: G_BRCOND %cmp(s1), %bb.1
; CHECK: G_BR %bb.2 ; CHECK: G_BR %bb.2
; CHECK: bb.1: ; CHECK: bb.1:
; CHECK: successors: ; CHECK: successors:
; CHECK: bb.2: ; CHECK: bb.2:
; CHECK: RET_ReallyLR ; CHECK: RET_ReallyLR
bb.1: bb.1:
Show All 9 Lines

llvm/test/CodeGen/AArch64/GlobalISel/legalize-extracts.mir

Show First 20 Lines • Show All 313 Lines • ▼ Show 20 Lines
name: s64_from_s264 name: s64_from_s264
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
liveins: $x0 liveins: $x0
; CHECK-LABEL: name: s64_from_s264 ; CHECK-LABEL: name: s64_from_s264
; CHECK: liveins: $x0 ; CHECK: liveins: $x0
; CHECK: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF ; CHECK: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
; CHECK: [[UV:%[0-9]+]]:_(s8), [[UV1:%[0-9]+]]:_(s8), [[UV2:%[0-9]+]]:_(s8), [[UV3:%[0-9]+]]:_(s8), [[UV4:%[0-9]+]]:_(s8), [[UV5:%[0-9]+]]:_(s8), [[UV6:%[0-9]+]]:_(s8), [[UV7:%[0-9]+]]:_(s8) = G_UNMERGE_VALUES [[DEF]](s64) ; CHECK: %extract:_(s64) = COPY [[DEF]](s64)
; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV]](s8), [[UV1]](s8), [[UV2]](s8), [[UV3]](s8), [[UV4]](s8), [[UV5]](s8), [[UV6]](s8), [[UV7]](s8)
; CHECK: %extract:_(s64) = COPY [[MV]](s64)
; CHECK: $x0 = COPY %extract(s64) ; CHECK: $x0 = COPY %extract(s64)
; CHECK: RET_ReallyLR implicit $x0 ; CHECK: RET_ReallyLR implicit $x0
%val:_(s264) = G_IMPLICIT_DEF %val:_(s264) = G_IMPLICIT_DEF
%extract:_(s64) = G_EXTRACT %val, 0 %extract:_(s64) = G_EXTRACT %val, 0
$x0 = COPY %extract $x0 = COPY %extract
RET_ReallyLR implicit $x0 RET_ReallyLR implicit $x0

llvm/test/CodeGen/AArch64/GlobalISel/legalize-undef.mir

Show First 20 Lines • Show All 92 Lines • ▼ Show 20 Linesbody: |
bb.0: bb.0:
; CHECK-LABEL: name: test_implicit_def_v8s16 ; CHECK-LABEL: name: test_implicit_def_v8s16
; CHECK: [[DEF:%[0-9]+]]:_(<8 x s16>) = G_IMPLICIT_DEF ; CHECK: [[DEF:%[0-9]+]]:_(<8 x s16>) = G_IMPLICIT_DEF
; CHECK: $q0 = COPY [[DEF]](<8 x s16>) ; CHECK: $q0 = COPY [[DEF]](<8 x s16>)
%0:_(<8 x s16>) = G_IMPLICIT_DEF %0:_(<8 x s16>) = G_IMPLICIT_DEF
$q0 = COPY %0 $q0 = COPY %0
... ...
---
name: test_implicit_def_s88
body: |
bb.0:
liveins:
; CHECK-LABEL: name: test_implicit_def_s88
; CHECK: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
; CHECK: $x0 = COPY [[DEF]](s64)
%undef:_(s88) = G_IMPLICIT_DEF
%trunc:_(s64) = G_TRUNC %undef
$x0 = COPY %trunc(s64)