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Differential D107587

[AArch64][GlobalISel] Widen extloads before clamping during legalization
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Authored by paquette on Aug 5 2021, 11:28 AM.

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aemerson
Commits
rG8a557d831159: [AArch64][GlobalISel] Widen extloads before clamping during legalization
Summary

Allows us to avoid awkward type breakdowns on types like s88, like the other commits.

Diff Detail

Event Timeline

paquette created this revision.Aug 5 2021, 11:28 AM
Herald added subscribers: danielkiss, hiraditya, kristof.beyls, rovka. · View Herald TranscriptAug 5 2021, 11:28 AM
paquette requested review of this revision.Aug 5 2021, 11:28 AM
Herald added a project: Restricted Project. · View Herald TranscriptAug 5 2021, 11:28 AM
Harbormaster completed remote builds in B118225: Diff 364561.Aug 5 2021, 11:58 AM
aemerson accepted this revision.Aug 5 2021, 4:05 PM
This revision is now accepted and ready to land.Aug 5 2021, 4:05 PM
This revision was landed with ongoing or failed builds.Aug 5 2021, 4:14 PM
Closed by commit rG8a557d831159: [AArch64][GlobalISel] Widen extloads before clamping during legalization (authored by paquette). · Explain Why
This revision was automatically updated to reflect the committed changes.
paquette added a commit: rG8a557d831159: [AArch64][GlobalISel] Widen extloads before clamping during legalization.

Revision Contents

PathSize
llvm/
lib/
Target/
AArch64/
GISel/
2 lines
test/
CodeGen/
AArch64/
GlobalISel/
105 lines

Diff 364561

llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp

Show First 20 Lines • Show All 259 Lines • ▼ Show 20 Lines getActionDefinitionsBuilder(G_EXTRACT)
}) })
.clampScalar(1, s32, s128) .clampScalar(1, s32, s128)
.widenScalarToNextPow2(1) .widenScalarToNextPow2(1)
.maxScalarIf(typeInSet(1, {s32}), 0, s16) .maxScalarIf(typeInSet(1, {s32}), 0, s16)
.maxScalarIf(typeInSet(1, {s64}), 0, s32) .maxScalarIf(typeInSet(1, {s64}), 0, s32)
.widenScalarToNextPow2(0); .widenScalarToNextPow2(0);
getActionDefinitionsBuilder({G_SEXTLOAD, G_ZEXTLOAD}) getActionDefinitionsBuilder({G_SEXTLOAD, G_ZEXTLOAD})
.lowerIf(atomicOrderingAtLeastOrStrongerThan(0, AtomicOrdering::Unordered)) .lowerIf(atomicOrderingAtLeastOrStrongerThan(0, AtomicOrdering::Unordered))
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-      .lowerIf(atomicOrderingAtLeastOrStrongerThan(0, AtomicOrdering::Unordered))
+      .lowerIf(
+          atomicOrderingAtLeastOrStrongerThan(0, AtomicOrdering::Unordered))
Lint: Pre-merge checks: clang-format: please reformat the code ``` - .lowerIf(atomicOrderingAtLeastOrStrongerThan…
.legalForTypesWithMemDesc({{s32, p0, s8, 8}, .legalForTypesWithMemDesc({{s32, p0, s8, 8},
{s32, p0, s16, 8}, {s32, p0, s16, 8},
{s32, p0, s32, 8}, {s32, p0, s32, 8},
{s64, p0, s8, 2}, {s64, p0, s8, 2},
{s64, p0, s16, 2}, {s64, p0, s16, 2},
{s64, p0, s32, 4}, {s64, p0, s32, 4},
{s64, p0, s64, 8}, {s64, p0, s64, 8},
{p0, p0, s64, 8}, {p0, p0, s64, 8},
{v2s32, p0, s64, 8}}) {v2s32, p0, s64, 8}})
.clampScalar(0, s32, s64)
.widenScalarToNextPow2(0) .widenScalarToNextPow2(0)
.clampScalar(0, s32, s64)
// TODO: We could support sum-of-pow2's but the lowering code doesn't know // TODO: We could support sum-of-pow2's but the lowering code doesn't know
// how to do that yet. // how to do that yet.
.unsupportedIfMemSizeNotPow2() .unsupportedIfMemSizeNotPow2()
// Lower anything left over into G_*EXT and G_LOAD // Lower anything left over into G_*EXT and G_LOAD
.lower(); .lower();
auto IsPtrVecPred = [=](const LegalityQuery &Query) { auto IsPtrVecPred = [=](const LegalityQuery &Query) {
const LLT &ValTy = Query.Types[0]; const LLT &ValTy = Query.Types[0];
▲ Show 20 Lines • Show All 1,035 Lines • Show Last 20 Lines

llvm/test/CodeGen/AArch64/GlobalISel/legalize-extload.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=aarch64 -run-pass=legalizer %s -o - -verify-machineinstrs | FileCheck %s # RUN: llc -march=aarch64 -run-pass=legalizer %s -o - -verify-machineinstrs | FileCheck %s
--- |
target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
target triple = "aarch64"
define void @test_extload() {
entry:
ret void
}
define i64 @sext_i32_i64(i32* %ptr) {
%ld = load i32, i32* %ptr, align 4
%v = sext i32 %ld to i64
ret i64 %v
}
define i64 @sext_i16_i64(i16* %ptr) {
%ld = load i16, i16* %ptr, align 2
%v = sext i16 %ld to i64
ret i64 %v
}
define i64 @sext_i8_i64(i8* %ptr) {
%ld = load i8, i8* %ptr, align 1
%v = sext i8 %ld to i64
ret i64 %v
}
define i64 @zext_i32_i64(i32* %ptr) {
%ld = load i32, i32* %ptr, align 4
%v = zext i32 %ld to i64
ret i64 %v
}
define i64 @zext_i16_i64(i16* %ptr) {
%ld = load i16, i16* %ptr, align 2
%v = zext i16 %ld to i64
ret i64 %v
}
define i64 @zext_i8_i64(i8* %ptr) {
%ld = load i8, i8* %ptr, align 1
%v = zext i8 %ld to i64
ret i64 %v
}
... ...
--- ---
name: test_extload name: test_extload
body: | body: |
bb.0.entry: bb.0.entry:
liveins: $x0 liveins: $x0
; CHECK-LABEL: name: test_extload ; CHECK-LABEL: name: test_extload
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0 ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s8)) ; CHECK: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s8))
; CHECK: $w0 = COPY [[LOAD]](s32) ; CHECK: $w0 = COPY [[LOAD]](s32)
%0:_(p0) = COPY $x0 %0:_(p0) = COPY $x0
%1:_(s32) = G_LOAD %0 :: (load (s8)) %1:_(s32) = G_LOAD %0 :: (load (s8))
$w0 = COPY %1 $w0 = COPY %1
... ...
--- ---
name: sext_i32_i64 name: sext_i32_i64
body: | body: |
bb.1: bb.1:
liveins: $x0 liveins: $x0
; CHECK-LABEL: name: sext_i32_i64 ; CHECK-LABEL: name: sext_i32_i64
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0 ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: [[SEXTLOAD:%[0-9]+]]:_(s64) = G_SEXTLOAD [[COPY]](p0) :: (load (s32) from %ir.ptr) ; CHECK: [[SEXTLOAD:%[0-9]+]]:_(s64) = G_SEXTLOAD [[COPY]](p0) :: (load (s32))
; CHECK: $x0 = COPY [[SEXTLOAD]](s64) ; CHECK: $x0 = COPY [[SEXTLOAD]](s64)
; CHECK: RET_ReallyLR implicit $x0 ; CHECK: RET_ReallyLR implicit $x0
%0:_(p0) = COPY $x0 %0:_(p0) = COPY $x0
%2:_(s64) = G_SEXTLOAD %0(p0) :: (load (s32) from %ir.ptr) %2:_(s64) = G_SEXTLOAD %0(p0) :: (load (s32))
$x0 = COPY %2(s64) $x0 = COPY %2(s64)
RET_ReallyLR implicit $x0 RET_ReallyLR implicit $x0
... ...
--- ---
name: sext_i16_i64 name: sext_i16_i64
body: | body: |
bb.1: bb.1:
liveins: $x0 liveins: $x0
; CHECK-LABEL: name: sext_i16_i64 ; CHECK-LABEL: name: sext_i16_i64
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0 ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: [[SEXTLOAD:%[0-9]+]]:_(s64) = G_SEXTLOAD [[COPY]](p0) :: (load (s16) from %ir.ptr) ; CHECK: [[SEXTLOAD:%[0-9]+]]:_(s64) = G_SEXTLOAD [[COPY]](p0) :: (load (s16))
; CHECK: $x0 = COPY [[SEXTLOAD]](s64) ; CHECK: $x0 = COPY [[SEXTLOAD]](s64)
; CHECK: RET_ReallyLR implicit $x0 ; CHECK: RET_ReallyLR implicit $x0
%0:_(p0) = COPY $x0 %0:_(p0) = COPY $x0
%2:_(s64) = G_SEXTLOAD %0(p0) :: (load (s16) from %ir.ptr) %2:_(s64) = G_SEXTLOAD %0(p0) :: (load (s16))
$x0 = COPY %2(s64) $x0 = COPY %2(s64)
RET_ReallyLR implicit $x0 RET_ReallyLR implicit $x0
... ...
--- ---
name: sext_i8_i64 name: sext_i8_i64
body: | body: |
bb.1: bb.1:
liveins: $x0 liveins: $x0
; CHECK-LABEL: name: sext_i8_i64 ; CHECK-LABEL: name: sext_i8_i64
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0 ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: [[SEXTLOAD:%[0-9]+]]:_(s64) = G_SEXTLOAD [[COPY]](p0) :: (load (s8) from %ir.ptr) ; CHECK: [[SEXTLOAD:%[0-9]+]]:_(s64) = G_SEXTLOAD [[COPY]](p0) :: (load (s8))
; CHECK: $x0 = COPY [[SEXTLOAD]](s64) ; CHECK: $x0 = COPY [[SEXTLOAD]](s64)
; CHECK: RET_ReallyLR implicit $x0 ; CHECK: RET_ReallyLR implicit $x0
%0:_(p0) = COPY $x0 %0:_(p0) = COPY $x0
%2:_(s64) = G_SEXTLOAD %0(p0) :: (load (s8) from %ir.ptr) %2:_(s64) = G_SEXTLOAD %0(p0) :: (load (s8))
$x0 = COPY %2(s64) $x0 = COPY %2(s64)
RET_ReallyLR implicit $x0 RET_ReallyLR implicit $x0
... ...
--- ---
name: zext_i32_i64 name: zext_i32_i64
body: | body: |
bb.1: bb.1:
liveins: $x0 liveins: $x0
; CHECK-LABEL: name: zext_i32_i64 ; CHECK-LABEL: name: zext_i32_i64
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0 ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: [[ZEXTLOAD:%[0-9]+]]:_(s64) = G_ZEXTLOAD [[COPY]](p0) :: (load (s32) from %ir.ptr) ; CHECK: [[ZEXTLOAD:%[0-9]+]]:_(s64) = G_ZEXTLOAD [[COPY]](p0) :: (load (s32))
; CHECK: $x0 = COPY [[ZEXTLOAD]](s64) ; CHECK: $x0 = COPY [[ZEXTLOAD]](s64)
; CHECK: RET_ReallyLR implicit $x0 ; CHECK: RET_ReallyLR implicit $x0
%0:_(p0) = COPY $x0 %0:_(p0) = COPY $x0
%2:_(s64) = G_ZEXTLOAD %0(p0) :: (load (s32) from %ir.ptr) %2:_(s64) = G_ZEXTLOAD %0(p0) :: (load (s32))
$x0 = COPY %2(s64) $x0 = COPY %2(s64)
RET_ReallyLR implicit $x0 RET_ReallyLR implicit $x0
... ...
--- ---
name: zext_i16_i64 name: zext_i16_i64
body: | body: |
bb.1: bb.1:
liveins: $x0 liveins: $x0
; CHECK-LABEL: name: zext_i16_i64 ; CHECK-LABEL: name: zext_i16_i64
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0 ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: [[ZEXTLOAD:%[0-9]+]]:_(s64) = G_ZEXTLOAD [[COPY]](p0) :: (load (s16) from %ir.ptr) ; CHECK: [[ZEXTLOAD:%[0-9]+]]:_(s64) = G_ZEXTLOAD [[COPY]](p0) :: (load (s16))
; CHECK: $x0 = COPY [[ZEXTLOAD]](s64) ; CHECK: $x0 = COPY [[ZEXTLOAD]](s64)
; CHECK: RET_ReallyLR implicit $x0 ; CHECK: RET_ReallyLR implicit $x0
%0:_(p0) = COPY $x0 %0:_(p0) = COPY $x0
%2:_(s64) = G_ZEXTLOAD %0(p0) :: (load (s16) from %ir.ptr) %2:_(s64) = G_ZEXTLOAD %0(p0) :: (load (s16))
$x0 = COPY %2(s64) $x0 = COPY %2(s64)
RET_ReallyLR implicit $x0 RET_ReallyLR implicit $x0
... ...
--- ---
name: zext_i8_i64 name: zext_i8_i64
body: | body: |
bb.1: bb.1:
liveins: $x0 liveins: $x0
; CHECK-LABEL: name: zext_i8_i64 ; CHECK-LABEL: name: zext_i8_i64
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0 ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: [[ZEXTLOAD:%[0-9]+]]:_(s64) = G_ZEXTLOAD [[COPY]](p0) :: (load (s8) from %ir.ptr) ; CHECK: [[ZEXTLOAD:%[0-9]+]]:_(s64) = G_ZEXTLOAD [[COPY]](p0) :: (load (s8))
; CHECK: $x0 = COPY [[ZEXTLOAD]](s64) ; CHECK: $x0 = COPY [[ZEXTLOAD]](s64)
; CHECK: RET_ReallyLR implicit $x0 ; CHECK: RET_ReallyLR implicit $x0
%0:_(p0) = COPY $x0 %0:_(p0) = COPY $x0
%2:_(s64) = G_ZEXTLOAD %0(p0) :: (load (s8) from %ir.ptr) %2:_(s64) = G_ZEXTLOAD %0(p0) :: (load (s8))
$x0 = COPY %2(s64) $x0 = COPY %2(s64)
RET_ReallyLR implicit $x0 RET_ReallyLR implicit $x0
... ...
---
name: zext_i8_i88
body: |
bb.1:
liveins: $x0
; CHECK-LABEL: name: zext_i8_i88
; CHECK: %ptr:_(p0) = COPY $x0
; CHECK: [[ZEXTLOAD:%[0-9]+]]:_(s64) = G_ZEXTLOAD %ptr(p0) :: (load (s8))
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK: $x0 = COPY [[ZEXTLOAD]](s64)
; CHECK: RET_ReallyLR implicit $x0
%ptr:_(p0) = COPY $x0
%load:_(s88) = G_ZEXTLOAD %ptr(p0) :: (load (s8))
%trunc:_(s64) = G_TRUNC %load
$x0 = COPY %trunc(s64)
RET_ReallyLR implicit $x0
...
...
---
name: sext_i8_i88
body: |
bb.1:
liveins: $x0
; CHECK-LABEL: name: sext_i8_i88
; CHECK: %ptr:_(p0) = COPY $x0
; CHECK: [[SEXTLOAD:%[0-9]+]]:_(s64) = G_SEXTLOAD %ptr(p0) :: (load (s8))
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 63
; CHECK: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SEXTLOAD]], [[C]](s64)
; CHECK: $x0 = COPY [[SEXTLOAD]](s64)
; CHECK: RET_ReallyLR implicit $x0
%ptr:_(p0) = COPY $x0
%load:_(s88) = G_SEXTLOAD %ptr(p0) :: (load (s8))
%trunc:_(s64) = G_TRUNC %load
$x0 = COPY %trunc(s64)
RET_ReallyLR implicit $x0
...