[DAG] isGuaranteedNotToBeUndefOrPoison - handle ISD::BUILD_VECTOR nodes

[RKSimon]

Summary

If all demanded elements of the BUILD_VECTOR pass a isGuaranteedNotToBeUndefOrPoison check, then we can treat this specific demanded use of the BUILD_VECTOR as guaranteed not to be undef or poison either.

NOTE: BUILD_VECTOR has implicit truncation of wider scalar elements - this shouldn't affect the result afaict.

[efriedma]

LGTM

[aqjune]

LGTM too.

llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

bool SelectionDAG::isGuaranteedNotToBeUndefOrPoison(SDValue Op,
 
   if (isIntOrFPConstant(Op))
     return true;
 
   switch (Opcode) {
   case ISD::UNDEF:
     return PoisonOnly;
 
-  // TODO: ISD::BUILD_VECTOR handling
+  case ISD::BUILD_VECTOR:
+    for (unsigned i = 0, e = Op.getNumOperands(); i < e; ++i) {
+      if (!DemandedElts[i])
+        continue;
+      if (!isGuaranteedNotToBeUndefOrPoison(Op.getOperand(i), PoisonOnly,
+                                            Depth + 1))
+        return false;
+    }
+    return true;
 
   // TODO: Search for noundef attributes from library functions.
 
   // TODO: Pointers dereferenced by ISD::LOAD/STORE ops are noundef.
 
   default:
     // Allow the target to implement this method for its nodes.
     if (Opcode >= ISD::BUILTIN_OP_END || Opcode == ISD::INTRINSIC_WO_CHAIN ||
         Opcode == ISD::INTRINSIC_W_CHAIN || Opcode == ISD::INTRINSIC_VOID)
       return TLI->isGuaranteedNotToBeUndefOrPoisonForTargetNode(
           Op, DemandedElts, *this, PoisonOnly, Depth);
     break;

llvm/test/CodeGen/X86/freeze-constant-fold.ll

; CHECK-NEXT:    ret{{[l|q]}}
   %1 = add i32 0, 0
   %2 = freeze i32 %1
   %3 = add i32 0, -1
   %4 = freeze i32 %3
   %5 = add i32 %2, %4
   ret i32 %5
 }
 
-; FIXME: X86 scalarization sees through the freeze, but vector types don't.
 define <4 x i32> @fold_add_freeze_v4i32() {
 ; X86-LABEL: fold_add_freeze_v4i32:
 ; X86:       # %bb.0:
 ; X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X86-NEXT:    movl $-1, 12(%eax)
 ; X86-NEXT:    movl $-1, 8(%eax)
 ; X86-NEXT:    movl $-1, 4(%eax)
 ; X86-NEXT:    movl $-1, (%eax)
 ; X86-NEXT:    retl $4
 ;
 ; X64-LABEL: fold_add_freeze_v4i32:
 ; X64:       # %bb.0:
-; X64-NEXT:    pxor %xmm1, %xmm1
 ; X64-NEXT:    pcmpeqd %xmm0, %xmm0
-; X64-NEXT:    paddd %xmm1, %xmm0
 ; X64-NEXT:    retq
   %1 = insertelement <4 x i32> poison, i32 0, i32 0
   %2 = shufflevector <4 x i32> %1, <4 x i32> poison, <4 x i32> zeroinitializer
   %3 = freeze <4 x i32> %2
   %4 = insertelement <4 x i32> poison, i32 -1, i32 0
   %5 = shufflevector <4 x i32> %4, <4 x i32> poison, <4 x i32> zeroinitializer
   %6 = freeze <4 x i32> %5
   %7 = add <4 x i32> %3, %6
   ret <4 x i32> %7
 }

llvm/test/CodeGen/X86/freeze-legalize.ll

; CHECK-NEXT:    retl
   %b = freeze i10 992
   %res = add i10 %a, %b
   ret i10 %res
 }
 
 define <2 x i10> @promote_vec() {
 ; CHECK-LABEL: promote_vec:
 ; CHECK:       ## %bb.0:
-; CHECK-NEXT:    movw $1674, %ax ## imm = 0x68A
+; CHECK-NEXT:    movw $650, %ax ## imm = 0x28A
 ; CHECK-NEXT:    movw $518, %dx ## imm = 0x206
 ; CHECK-NEXT:    retl
   %a = freeze <2 x i10> <i10 682, i10 125>
   %b = freeze <2 x i10> <i10 992, i10 393>
   %res = add <2 x i10> %a, %b
   ret <2 x i10> %res
 }