[WebAssembly] Compute known bits for SIMD bitmask intrinsics

[tlively]

Summary

This optimizes out the mask when the result of a bitmask is interpreted as an i8
or i16 value. Resolves PR50507.

[aheejin]

llvm/test/CodeGen/WebAssembly/simd-bitmask-mask.ll

7–8

llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.h

private:
   bool isIntDivCheap(EVT VT, AttributeList Attr) const override;
   bool isVectorLoadExtDesirable(SDValue ExtVal) const override;
   EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
                          EVT VT) const override;
   bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I,
                           MachineFunction &MF,
                           unsigned Intrinsic) const override;
 
+  void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known,
+                                     const APInt &DemandedElts,
+                                     const SelectionDAG &DAG,
+                                     unsigned Depth) const override;
+
   SDValue LowerCall(CallLoweringInfo &CLI,
                     SmallVectorImpl<SDValue> &InVals) const override;
   bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
                       bool isVarArg,
                       const SmallVectorImpl<ISD::OutputArg> &Outs,
                       LLVMContext &Context) const override;
   SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
                       const SmallVectorImpl<ISD::OutputArg> &Outs,

llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp

 #include "llvm/CodeGen/WasmEHFuncInfo.h"
 #include "llvm/IR/DiagnosticInfo.h"
 #include "llvm/IR/DiagnosticPrinter.h"
 #include "llvm/IR/Function.h"
 #include "llvm/IR/Intrinsics.h"
 #include "llvm/IR/IntrinsicsWebAssembly.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/ErrorHandling.h"
+#include "llvm/Support/KnownBits.h"
 #include "llvm/Support/MathExtras.h"
 #include "llvm/Support/raw_ostream.h"
 #include "llvm/Target/TargetOptions.h"
 using namespace llvm;
 
 #define DEBUG_TYPE "wasm-lower"
 
 WebAssemblyTargetLowering::WebAssemblyTargetLowering(
case Intrinsic::wasm_memory_atomic_wait64:
     Info.align = Align(8);
     Info.flags = MachineMemOperand::MOVolatile | MachineMemOperand::MOLoad;
     return true;
   default:
     return false;
   }
 }
 
+void WebAssemblyTargetLowering::computeKnownBitsForTargetNode(
+    const SDValue Op, KnownBits &Known, const APInt &DemandedElts,
+    const SelectionDAG &DAG, unsigned Depth) const {
+  switch (Op.getOpcode()) {
+  default:
+    break;
+  case ISD::INTRINSIC_WO_CHAIN: {
+    unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
+    switch (IntNo) {
+    default:
+      break;
+    case Intrinsic::wasm_bitmask: {
+      unsigned BitWidth = Known.getBitWidth();
+      EVT VT = Op.getOperand(1).getSimpleValueType();
+      unsigned PossibleBits = VT.getVectorNumElements();
+      APInt ZeroMask = APInt::getHighBitsSet(BitWidth, BitWidth - PossibleBits);
+      Known.Zero |= ZeroMask;
+      break;
+    }
+    }
+  }
+  }
+}
+
 //===----------------------------------------------------------------------===//
 // WebAssembly Lowering private implementation.
 //===----------------------------------------------------------------------===//
 
 //===----------------------------------------------------------------------===//
 // Lowering Code
 //===----------------------------------------------------------------------===//
 

llvm/test/CodeGen/WebAssembly/simd-bitmask-mask.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mattr=+simd128 | FileCheck %s
+
+; Test that masks on the output of bitselect are optimized out.
+
+target triple = "wasm32-unknown-unknown"
+
+
+declare i32 @llvm.wasm.bitmask.v16i8(<16 x i8>)
+declare i32 @llvm.wasm.bitmask.v8i16(<8 x i16>)
+declare i32 @llvm.wasm.bitmask.v4i32(<4 x i32>)
+declare i32 @llvm.wasm.bitmask.v2i64(<2 x i64>)
+
+define i32 @bitmask_v16i8_mask(<16 x i8> %x) {
+; CHECK-LABEL: bitmask_v16i8_mask:
+; CHECK:         .functype bitmask_v16i8_mask (v128) -> (i32)
+; CHECK-NEXT:  # %bb.0:
+; CHECK-NEXT:    local.get 0
+; CHECK-NEXT:    i8x16.bitmask
+; CHECK-NEXT:    i32.const 32767
+; CHECK-NEXT:    i32.and
+; CHECK-NEXT:    # fallthrough-return
+  %m = tail call i32 @llvm.wasm.bitmask.v16i8(<16 x i8> %x)
+  %v = and i32 %m, 32767 ;; 2^15 - 1
+  ret i32 %v
+}
+
+define i32 @bitmask_v16i8_no_mask(<16 x i8> %x) {
+; CHECK-LABEL: bitmask_v16i8_no_mask:
+; CHECK:         .functype bitmask_v16i8_no_mask (v128) -> (i32)
+; CHECK-NEXT:  # %bb.0:
+; CHECK-NEXT:    local.get 0
+; CHECK-NEXT:    i8x16.bitmask
+; CHECK-NEXT:    # fallthrough-return
+  %m = tail call i32 @llvm.wasm.bitmask.v16i8(<16 x i8> %x)
+  %v = and i32 %m, 65535 ;; 2^16 - 1
+  ret i32 %v
+}
+
+define i32 @bitmask_v8i16_mask(<8 x i16> %x) {
+; CHECK-LABEL: bitmask_v8i16_mask:
+; CHECK:         .functype bitmask_v8i16_mask (v128) -> (i32)
+; CHECK-NEXT:  # %bb.0:
+; CHECK-NEXT:    local.get 0
+; CHECK-NEXT:    i16x8.bitmask
+; CHECK-NEXT:    i32.const 127
+; CHECK-NEXT:    i32.and
+; CHECK-NEXT:    # fallthrough-return
+  %m = tail call i32 @llvm.wasm.bitmask.v8i16(<8 x i16> %x)
+  %v = and i32 %m, 127 ;; 2^7 - 1
+  ret i32 %v
+}
+
+define i32 @bitmask_v8i16_no_mask(<8 x i16> %x) {
+; CHECK-LABEL: bitmask_v8i16_no_mask:
+; CHECK:         .functype bitmask_v8i16_no_mask (v128) -> (i32)
+; CHECK-NEXT:  # %bb.0:
+; CHECK-NEXT:    local.get 0
+; CHECK-NEXT:    i16x8.bitmask
+; CHECK-NEXT:    # fallthrough-return
+  %m = tail call i32 @llvm.wasm.bitmask.v8i16(<8 x i16> %x)
+  %v = and i32 %m, 255 ;; 2^8 - 1
+  ret i32 %v
+}
+
+define i32 @bitmask_v4i32_mask(<4 x i32> %x) {
+; CHECK-LABEL: bitmask_v4i32_mask:
+; CHECK:         .functype bitmask_v4i32_mask (v128) -> (i32)
+; CHECK-NEXT:  # %bb.0:
+; CHECK-NEXT:    local.get 0
+; CHECK-NEXT:    i32x4.bitmask
+; CHECK-NEXT:    i32.const 7
+; CHECK-NEXT:    i32.and
+; CHECK-NEXT:    # fallthrough-return
+  %m = tail call i32 @llvm.wasm.bitmask.v4i32(<4 x i32> %x)
+  %v = and i32 %m, 7 ;; 2^3 - 1
+  ret i32 %v
+}
+
+define i32 @bitmask_v4i32_no_mask(<4 x i32> %x) {
+; CHECK-LABEL: bitmask_v4i32_no_mask:
+; CHECK:         .functype bitmask_v4i32_no_mask (v128) -> (i32)
+; CHECK-NEXT:  # %bb.0:
+; CHECK-NEXT:    local.get 0
+; CHECK-NEXT:    i32x4.bitmask
+; CHECK-NEXT:    # fallthrough-return
+  %m = tail call i32 @llvm.wasm.bitmask.v4i32(<4 x i32> %x)
+  %v = and i32 %m, 15 ;; 2^4 - 1
+  ret i32 %v
+}
+
+define i32 @bitmask_v2i64_mask(<2 x i64> %x) {
+; CHECK-LABEL: bitmask_v2i64_mask:
+; CHECK:         .functype bitmask_v2i64_mask (v128) -> (i32)
+; CHECK-NEXT:  # %bb.0:
+; CHECK-NEXT:    local.get 0
+; CHECK-NEXT:    i64x2.bitmask
+; CHECK-NEXT:    i32.const 1
+; CHECK-NEXT:    i32.and
+; CHECK-NEXT:    # fallthrough-return
+  %m = tail call i32 @llvm.wasm.bitmask.v2i64(<2 x i64> %x)
+  %v = and i32 %m, 1 ;; 2^1 - 1
+  ret i32 %v
+}
+
+define i32 @bitmask_v2i64_no_mask(<2 x i64> %x) {
+; CHECK-LABEL: bitmask_v2i64_no_mask:
+; CHECK:         .functype bitmask_v2i64_no_mask (v128) -> (i32)
+; CHECK-NEXT:  # %bb.0:
+; CHECK-NEXT:    local.get 0
+; CHECK-NEXT:    i64x2.bitmask
+; CHECK-NEXT:    # fallthrough-return
+  %m = tail call i32 @llvm.wasm.bitmask.v2i64(<2 x i64> %x)
+  %v = and i32 %m, 3 ;; 2^2 - 1
+  ret i32 %v
+}