[Bazel] Added missing targets to LLVM bazel rules.

[izuk]

Summary

Added the following targets to the LLVM Bazel overlay:

AVR
Mips
MPS430
SystemZ
XCore

[GMNGeoffrey]

utils/bazel/llvm-project-overlay/llvm/BUILD.bazel

1510–1730

These are missing "lib/Target/Foo" prefixes for the filenames. With the addition of the suggested change, I've confirmed that the Bazel build passes (still working on a proper pre-merge check)

[izuk]

Fixed missing lib/Target/Foo prefixes.

utils/bazel/configure.bzl

 
 # Directory of overlay files relative to WORKSPACE
 DEFAULT_OVERLAY_PATH = "llvm-project-overlay"
 
 DEFAULT_TARGETS = [
     "AArch64",
     "AMDGPU",
     "ARM",
+    "AVR",
     "BPF",
     "Hexagon",
     "Lanai",
+    "Mips",
+    "MSP430",
     "NVPTX",
     "PowerPC",
     "RISCV",
     "Sparc",
+    "SystemZ",
     "WebAssembly",
     "X86",
+    "XCore",
 ]
 
 def _overlay_directories(repository_ctx):
     src_workspace_path = str(repository_ctx.path(
         repository_ctx.attr.src_workspace,
     ).dirname)
 
     src_path = paths.join(src_workspace_path, repository_ctx.attr.src_path)

utils/bazel/llvm-project-overlay/llvm/BUILD.bazel

llvm_target_lib_list = [lib for lib in [
             ("-gen-searchable-tables", "lib/Target/AMDGPU/AMDGPUGenSearchableTables.inc"),
         ],
         "tbl_deps": [
             ":amdgpu_isel_target_gen",
             ":r600_target_gen",
         ],
     },
     {
+        "name": "AVR",
+        "short_name": "AVR",
+        "tbl_outs": [
+            ("-gen-asm-matcher", "lib/Target/AVR/AVRGenAsmMatcher.inc"),
+            ("-gen-asm-writer", "lib/Target/AVR/AVRGenAsmWriter.inc"),
+            ("-gen-callingconv", "lib/Target/AVR/AVRGenCallingConv.inc"),
+            ("-gen-dag-isel", "lib/Target/AVR/AVRGenDAGISel.inc"),
+            ("-gen-disassembler", "lib/Target/AVR/AVRGenDisassemblerTables.inc"),
+            ("-gen-emitter", "lib/Target/AVR/AVRGenMCCodeEmitter.inc"),
+            ("-gen-instr-info", "lib/Target/AVR/AVRGenInstrInfo.inc"),
+            ("-gen-register-info", "lib/Target/AVR/AVRGenRegisterInfo.inc"),
+            ("-gen-subtarget", "lib/Target/AVR/AVRGenSubtargetInfo.inc"),
+        ],
+    },
+    {
         "name": "BPF",
         "short_name": "BPF",
         "tbl_outs": [
             ("-gen-asm-writer", "lib/Target/BPF/BPFGenAsmWriter.inc"),
             ("-gen-asm-matcher", "lib/Target/BPF/BPFGenAsmMatcher.inc"),
             ("-gen-callingconv", "lib/Target/BPF/BPFGenCallingConv.inc"),
             ("-gen-dag-isel", "lib/Target/BPF/BPFGenDAGISel.inc"),
             ("-gen-disassembler", "lib/Target/BPF/BPFGenDisassemblerTables.inc"),
             ("-gen-emitter", "lib/Target/BPF/BPFGenMCCodeEmitter.inc"),
             ("-gen-instr-info", "lib/Target/BPF/BPFGenInstrInfo.inc"),
             ("-gen-register-info", "lib/Target/BPF/BPFGenRegisterInfo.inc"),
             ("-gen-subtarget", "lib/Target/BPF/BPFGenSubtargetInfo.inc"),
         ],
     },
     {
         "name": "Hexagon",
         "short_name": "Hexagon",
         "tbl_outs": [
             ("-gen-asm-matcher", "lib/Target/Hexagon/HexagonGenAsmMatcher.inc"),
             ("-gen-asm-writer", "lib/Target/Hexagon/HexagonGenAsmWriter.inc"),
             ("-gen-callingconv", "lib/Target/Hexagon/HexagonGenCallingConv.inc"),
             ("-gen-dag-isel", "lib/Target/Hexagon/HexagonGenDAGISel.inc"),
             ("-gen-dfa-packetizer", "lib/Target/Hexagon/HexagonGenDFAPacketizer.inc"),
             ("-gen-disassembler", "lib/Target/Hexagon/HexagonGenDisassemblerTables.inc"),
             ("-gen-instr-info", "lib/Target/Hexagon/HexagonGenInstrInfo.inc"),
             ("-gen-emitter", "lib/Target/Hexagon/HexagonGenMCCodeEmitter.inc"),
             ("-gen-register-info", "lib/Target/Hexagon/HexagonGenRegisterInfo.inc"),
             ("-gen-subtarget", "lib/Target/Hexagon/HexagonGenSubtargetInfo.inc"),
         ],
     },
     {
         "name": "Lanai",
         "short_name": "Lanai",
         "tbl_outs": [
             ("-gen-asm-matcher", "lib/Target/Lanai/LanaiGenAsmMatcher.inc"),
             ("-gen-asm-writer", "lib/Target/Lanai/LanaiGenAsmWriter.inc"),
             ("-gen-callingconv", "lib/Target/Lanai/LanaiGenCallingConv.inc"),
             ("-gen-dag-isel", "lib/Target/Lanai/LanaiGenDAGISel.inc"),
             ("-gen-disassembler", "lib/Target/Lanai/LanaiGenDisassemblerTables.inc"),
             ("-gen-emitter", "lib/Target/Lanai/LanaiGenMCCodeEmitter.inc"),
             ("-gen-instr-info", "lib/Target/Lanai/LanaiGenInstrInfo.inc"),
             ("-gen-register-info", "lib/Target/Lanai/LanaiGenRegisterInfo.inc"),
             ("-gen-subtarget", "lib/Target/Lanai/LanaiGenSubtargetInfo.inc"),
         ],
     },
     {
+        "name": "Mips",
+        "short_name": "Mips",
+        "tbl_outs": [
+            ("-gen-asm-matcher", "lib/Target/Mips/MipsGenAsmMatcher.inc"),
+            ("-gen-asm-writer", "lib/Target/Mips/MipsGenAsmWriter.inc"),
+            ("-gen-callingconv", "lib/Target/Mips/MipsGenCallingConv.inc"),
+            ("-gen-dag-isel", "lib/Target/Mips/MipsGenDAGISel.inc"),
+            ("-gen-disassembler", "lib/Target/Mips/MipsGenDisassemblerTables.inc"),
+            ("-gen-emitter", "lib/Target/Mips/MipsGenMCCodeEmitter.inc"),
+            ("-gen-exegesis", "lib/Target/Mips/MipsGenExegesis.inc"),
+            ("-gen-fast-isel", "lib/Target/Mips/MipsGenFastISel.inc"),
+            ("-gen-global-isel", "lib/Target/Mips/MipsGenGlobalISel.inc"),
+            ("-gen-instr-info", "lib/Target/Mips/MipsGenInstrInfo.inc"),
+            ("-gen-pseudo-lowering", "lib/Target/Mips/MipsGenMCPseudoLowering.inc"),
+            ("-gen-register-bank", "lib/Target/Mips/MipsGenRegisterBank.inc"),
+            ("-gen-register-info", "lib/Target/Mips/MipsGenRegisterInfo.inc"),
+            ("-gen-subtarget", "lib/Target/Mips/MipsGenSubtargetInfo.inc"),
+        ],
+    },
+    {
+        "name": "MSP430",
+        "short_name": "MSP430",
+        "tbl_outs": [
+            ("-gen-asm-matcher", "lib/Target/MSP430/MSP430GenAsmMatcher.inc"),
+            ("-gen-asm-writer", "lib/Target/MSP430/MSP430GenAsmWriter.inc"),
+            ("-gen-callingconv", "lib/Target/MSP430/MSP430GenCallingConv.inc"),
+            ("-gen-dag-isel", "lib/Target/MSP430/MSP430GenDAGISel.inc"),
+            ("-gen-disassembler", "lib/Target/MSP430/MSP430GenDisassemblerTables.inc"),
+            ("-gen-emitter", "lib/Target/MSP430/MSP430GenMCCodeEmitter.inc"),
+            ("-gen-instr-info", "lib/Target/MSP430/MSP430GenInstrInfo.inc"),
+            ("-gen-register-info", "lib/Target/MSP430/MSP430GenRegisterInfo.inc"),
+            ("-gen-subtarget", "lib/Target/MSP430/MSP430GenSubtargetInfo.inc"),
+        ],
+    },
+    {
         "name": "NVPTX",
         "short_name": "NVPTX",
         "tbl_outs": [
             ("-gen-register-info", "lib/Target/NVPTX/NVPTXGenRegisterInfo.inc"),
             ("-gen-instr-info", "lib/Target/NVPTX/NVPTXGenInstrInfo.inc"),
             ("-gen-asm-writer", "lib/Target/NVPTX/NVPTXGenAsmWriter.inc"),
             ("-gen-dag-isel", "lib/Target/NVPTX/NVPTXGenDAGISel.inc"),
             ("-gen-subtarget", "lib/Target/NVPTX/NVPTXGenSubtargetInfo.inc"),
         ],
     },
     {
         "name": "PowerPC",
         "short_name": "PPC",
         "tbl_outs": [
             ("-gen-asm-writer", "lib/Target/PowerPC/PPCGenAsmWriter.inc"),
             ("-gen-asm-matcher", "lib/Target/PowerPC/PPCGenAsmMatcher.inc"),
             ("-gen-emitter", "lib/Target/PowerPC/PPCGenMCCodeEmitter.inc"),
             ("-gen-register-info", "lib/Target/PowerPC/PPCGenRegisterInfo.inc"),
             ("-gen-instr-info", "lib/Target/PowerPC/PPCGenInstrInfo.inc"),
             ("-gen-dag-isel", "lib/Target/PowerPC/PPCGenDAGISel.inc"),
             ("-gen-fast-isel", "lib/Target/PowerPC/PPCGenFastISel.inc"),
             ("-gen-callingconv", "lib/Target/PowerPC/PPCGenCallingConv.inc"),
             ("-gen-subtarget", "lib/Target/PowerPC/PPCGenSubtargetInfo.inc"),
             ("-gen-disassembler", "lib/Target/PowerPC/PPCGenDisassemblerTables.inc"),
             ("-gen-register-bank", "lib/Target/PowerPC/PPCGenRegisterBank.inc"),
             ("-gen-global-isel", "lib/Target/PowerPC/PPCGenGlobalISel.inc"),
         ],
     },
     {
         "name": "Sparc",
         "short_name": "Sparc",
         "tbl_outs": [
             ("-gen-asm-writer", "lib/Target/Sparc/SparcGenAsmWriter.inc"),
             ("-gen-asm-matcher", "lib/Target/Sparc/SparcGenAsmMatcher.inc"),
             ("-gen-emitter", "lib/Target/Sparc/SparcGenMCCodeEmitter.inc"),
             ("-gen-register-info", "lib/Target/Sparc/SparcGenRegisterInfo.inc"),
             ("-gen-instr-info", "lib/Target/Sparc/SparcGenInstrInfo.inc"),
             ("-gen-dag-isel", "lib/Target/Sparc/SparcGenDAGISel.inc"),
             ("-gen-callingconv", "lib/Target/Sparc/SparcGenCallingConv.inc"),
             ("-gen-subtarget", "lib/Target/Sparc/SparcGenSubtargetInfo.inc"),
             ("-gen-disassembler", "lib/Target/Sparc/SparcGenDisassemblerTables.inc"),
         ],
     },
     {
+        "name": "SystemZ",
+        "short_name": "SystemZ",
+        "tbl_outs": [
+            ("-gen-asm-matcher", "lib/Target/SystemZ/SystemZGenAsmMatcher.inc"),
+            ("-gen-asm-writer", "lib/Target/SystemZ/SystemZGenAsmWriter.inc"),
+            ("-gen-callingconv", "lib/Target/SystemZ/SystemZGenCallingConv.inc"),
+            ("-gen-dag-isel", "lib/Target/SystemZ/SystemZGenDAGISel.inc"),
+            ("-gen-disassembler", "lib/Target/SystemZ/SystemZGenDisassemblerTables.inc"),
+            ("-gen-emitter", "lib/Target/SystemZ/SystemZGenMCCodeEmitter.inc"),
+            ("-gen-instr-info", "lib/Target/SystemZ/SystemZGenInstrInfo.inc"),
+            ("-gen-register-info", "lib/Target/SystemZ/SystemZGenRegisterInfo.inc"),
+            ("-gen-subtarget", "lib/Target/SystemZ/SystemZGenSubtargetInfo.inc"),
+        ],
+    },
+    {
         "name": "RISCV",
         "short_name": "RISCV",
         "tbl_outs": [
             ("-gen-asm-matcher", "lib/Target/RISCV/RISCVGenAsmMatcher.inc"),
             ("-gen-asm-writer", "lib/Target/RISCV/RISCVGenAsmWriter.inc"),
             ("-gen-compress-inst-emitter", "lib/Target/RISCV/RISCVGenCompressInstEmitter.inc"),
             ("-gen-dag-isel", "lib/Target/RISCV/RISCVGenDAGISel.inc"),
             ("-gen-disassembler", "lib/Target/RISCV/RISCVGenDisassemblerTables.inc"),
             ("-gen-global-isel", "lib/Target/RISCV/RISCVGenGlobalISel.inc"),
             ("-gen-instr-info", "lib/Target/RISCV/RISCVGenInstrInfo.inc"),
             ("-gen-emitter", "lib/Target/RISCV/RISCVGenMCCodeEmitter.inc"),
             ("-gen-pseudo-lowering", "lib/Target/RISCV/RISCVGenMCPseudoLowering.inc"),
             ("-gen-register-bank", "lib/Target/RISCV/RISCVGenRegisterBank.inc"),
             ("-gen-register-info", "lib/Target/RISCV/RISCVGenRegisterInfo.inc"),
             ("-gen-subtarget", "lib/Target/RISCV/RISCVGenSubtargetInfo.inc"),
             ("-gen-searchable-tables", "lib/Target/RISCV/RISCVGenSearchableTables.inc"),
         ],
     },
     {
         "name": "WebAssembly",
         "short_name": "WebAssembly",
         "tbl_outs": [
             ("-gen-disassembler", "lib/Target/WebAssembly/WebAssemblyGenDisassemblerTables.inc"),
             ("-gen-asm-writer", "lib/Target/WebAssembly/WebAssemblyGenAsmWriter.inc"),
             ("-gen-instr-info", "lib/Target/WebAssembly/WebAssemblyGenInstrInfo.inc"),
             ("-gen-dag-isel", "lib/Target/WebAssembly/WebAssemblyGenDAGISel.inc"),
             ("-gen-fast-isel", "lib/Target/WebAssembly/WebAssemblyGenFastISel.inc"),
             ("-gen-emitter", "lib/Target/WebAssembly/WebAssemblyGenMCCodeEmitter.inc"),
             ("-gen-register-info", "lib/Target/WebAssembly/WebAssemblyGenRegisterInfo.inc"),
             ("-gen-subtarget", "lib/Target/WebAssembly/WebAssemblyGenSubtargetInfo.inc"),
             ("-gen-asm-matcher", "lib/Target/WebAssembly/WebAssemblyGenAsmMatcher.inc"),
         ],
     },
     {
         "name": "X86",
         "short_name": "X86",
         "tbl_outs": [
             ("-gen-register-bank", "lib/Target/X86/X86GenRegisterBank.inc"),
             ("-gen-register-info", "lib/Target/X86/X86GenRegisterInfo.inc"),
             ("-gen-disassembler", "lib/Target/X86/X86GenDisassemblerTables.inc"),
             ("-gen-instr-info", "lib/Target/X86/X86GenInstrInfo.inc"),
             ("-gen-asm-writer", "lib/Target/X86/X86GenAsmWriter.inc"),
             ("-gen-asm-writer -asmwriternum=1", "lib/Target/X86/X86GenAsmWriter1.inc"),
             ("-gen-asm-matcher", "lib/Target/X86/X86GenAsmMatcher.inc"),
             ("-gen-dag-isel", "lib/Target/X86/X86GenDAGISel.inc"),
             ("-gen-fast-isel", "lib/Target/X86/X86GenFastISel.inc"),
             ("-gen-global-isel", "lib/Target/X86/X86GenGlobalISel.inc"),
             ("-gen-callingconv", "lib/Target/X86/X86GenCallingConv.inc"),
             ("-gen-subtarget", "lib/Target/X86/X86GenSubtargetInfo.inc"),
             ("-gen-x86-EVEX2VEX-tables", "lib/Target/X86/X86GenEVEX2VEXTables.inc"),
             ("-gen-exegesis", "lib/Target/X86/X86GenExegesis.inc"),
         ],
     },
+    {
+        "name": "XCore",
+        "short_name": "XCore",
+        "tbl_outs": [
+            ("-gen-asm-writer", "lib/Target/XCore/XCoreGenAsmWriter.inc"),
+            ("-gen-callingconv", "lib/Target/XCore/XCoreGenCallingConv.inc"),
+            ("-gen-dag-isel", "lib/Target/XCore/XCoreGenDAGISel.inc"),
+            ("-gen-disassembler", "lib/Target/XCore/XCoreGenDisassemblerTables.inc"),
+            ("-gen-instr-info", "lib/Target/XCore/XCoreGenInstrInfo.inc"),
+            ("-gen-register-info", "lib/Target/XCore/XCoreGenRegisterInfo.inc"),
+            ("-gen-subtarget", "lib/Target/XCore/XCoreGenSubtargetInfo.inc"),
+        ],
+    },




 ] if lib["name"] in llvm_targets]
 
 cc_library(
     name = "x86_target_layering_problem_hdrs",
     textual_hdrs = ["lib/Target/X86/X86InstrInfo.h"],
 )
 
 filegroup(