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Differential D106865

Precommit test for D106857.
ClosedPublic

Authored by jacquesguan on Jul 27 2021, 5:28 AM.

Details

Reviewers
frasercrmck
craig.topper
Commits
rGed804588341e: [RISCV][test] Precommit tests for VSETVLI insertion improvement (D106857).
Summary

It is the test for D106857.

Diff Detail

Event Timeline

jacquesguan created this revision.Jul 27 2021, 5:28 AM
Herald added subscribers: luismarques, apazos, sameer.abuasal and 17 others. · View Herald TranscriptJul 27 2021, 5:28 AM
jacquesguan requested review of this revision.Jul 27 2021, 5:28 AM
Herald added a project: Restricted Project. · View Herald TranscriptJul 27 2021, 5:28 AM
Herald added subscribers: llvm-commits, MaskRay. · View Herald Transcript
jacquesguan mentioned this in D106857: [RISCV] Teach VSETVLI insertion to merge the unused VSETVLI with the one need to be insert after it..Jul 27 2021, 5:30 AM
Harbormaster completed remote builds in B116403: Diff 361992.Jul 27 2021, 6:19 AM
jacquesguan updated this revision to Diff 362656.Jul 29 2021, 12:17 AM

Update case for the same VLMAX.

Harbormaster completed remote builds in B116886: Diff 362656.Jul 29 2021, 12:55 AM
jacquesguan updated this revision to Diff 362952.Jul 29 2021, 7:08 PM

Add test cases that use the same AVL.

jacquesguan added a reviewer: craig.topper.Jul 29 2021, 7:09 PM
Harbormaster completed remote builds in B117092: Diff 362952.Jul 29 2021, 7:57 PM
craig.topper accepted this revision.Aug 2 2021, 5:10 PM

LGTM

This revision is now accepted and ready to land.Aug 2 2021, 5:10 PM
Closed by commit rGed804588341e: [RISCV][test] Precommit tests for VSETVLI insertion improvement (D106857). (authored by jacquesguan, committed by benshi001). · Explain WhyAug 2 2021, 9:08 PM
This revision was automatically updated to reflect the committed changes.
benshi001 added a commit: rGed804588341e: [RISCV][test] Precommit tests for VSETVLI insertion improvement (D106857)..

Revision Contents

PathSize
llvm/
test/
CodeGen/
RISCV/
rvv/
112 lines

Diff 361992

llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+m,+f,+d,+a,+c,+experimental-v \
; RUN: -verify-machineinstrs -O2 < %s | FileCheck %s
declare i64 @llvm.riscv.vsetvli(i64, i64, i64)
declare <vscale x 1 x double> @llvm.riscv.vfadd.nxv1f64.nxv1f64(<vscale x 1 x double>, <vscale x 1 x double>, i64)
declare void @foo()
define <vscale x 1 x double> @test1(i64 %avl, i8 zeroext %cond, <vscale x 1 x double> %a, <vscale x 1 x double> %b) nounwind {
; CHECK-LABEL: test1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32, m1, ta, mu
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
; CHECK-NEXT: vfadd.vv v8, v8, v9
; CHECK-NEXT: ret
entry:
%0 = tail call i64 @llvm.riscv.vsetvli(i64 %avl, i64 2, i64 0)
%1 = tail call <vscale x 1 x double> @llvm.riscv.vfadd.nxv1f64.nxv1f64(<vscale x 1 x double> %a, <vscale x 1 x double> %b, i64 %0)
ret <vscale x 1 x double> %1
}
define <vscale x 1 x double> @test2(i64 %avl, i8 zeroext %cond, <vscale x 1 x double> %a, <vscale x 1 x double> %b) nounwind {
; CHECK-LABEL: test2:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a0, e32, m1, ta, mu
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
; CHECK-NEXT: vfadd.vv v8, v8, v9
; CHECK-NEXT: ret
entry:
%0 = tail call i64 @llvm.riscv.vsetvli(i64 %avl, i64 2, i64 0)
%1 = tail call <vscale x 1 x double> @llvm.riscv.vfadd.nxv1f64.nxv1f64(<vscale x 1 x double> %a, <vscale x 1 x double> %b, i64 %avl)
ret <vscale x 1 x double> %1
}
define <vscale x 1 x double> @test3(i64 %avl, i8 zeroext %cond, <vscale x 1 x double> %a, <vscale x 1 x double> %b) nounwind {
; CHECK-LABEL: test3:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -32
; CHECK-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; CHECK-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 1
; CHECK-NEXT: sub sp, sp, a1
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: add a1, a1, sp
; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vs1r.v v9, (a1) # Unknown-size Folded Spill
; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vs1r.v v8, (a1) # Unknown-size Folded Spill
; CHECK-NEXT: vsetvli s0, a0, e32, m1, ta, mu
; CHECK-NEXT: call foo@plt
; CHECK-NEXT: vsetvli zero, s0, e64, m1, ta, mu
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: add a0, a0, sp
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl1r.v v25, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vl1r.v v26, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: vfadd.vv v8, v26, v25
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 1
; CHECK-NEXT: add sp, sp, a0
; CHECK-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; CHECK-NEXT: addi sp, sp, 32
; CHECK-NEXT: ret
entry:
%0 = tail call i64 @llvm.riscv.vsetvli(i64 %avl, i64 2, i64 0)
tail call void @foo()
%1 = tail call <vscale x 1 x double> @llvm.riscv.vfadd.nxv1f64.nxv1f64(<vscale x 1 x double> %a, <vscale x 1 x double> %b, i64 %0)
ret <vscale x 1 x double> %1
}
define <vscale x 1 x double> @test4(i64 %avl, i8 zeroext %cond, <vscale x 1 x double> %a, <vscale x 1 x double> %b) nounwind {
; CHECK-LABEL: test4:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -32
; CHECK-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; CHECK-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 1
; CHECK-NEXT: sub sp, sp, a1
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: add a1, a1, sp
; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vs1r.v v9, (a1) # Unknown-size Folded Spill
; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vs1r.v v8, (a1) # Unknown-size Folded Spill
; CHECK-NEXT: mv s0, a0
; CHECK-NEXT: vsetvli a0, a0, e32, m1, ta, mu
; CHECK-NEXT: call foo@plt
; CHECK-NEXT: vsetvli zero, s0, e64, m1, ta, mu
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: add a0, a0, sp
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl1r.v v25, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vl1r.v v26, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: vfadd.vv v8, v26, v25
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 1
; CHECK-NEXT: add sp, sp, a0
; CHECK-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; CHECK-NEXT: addi sp, sp, 32
; CHECK-NEXT: ret
entry:
%0 = tail call i64 @llvm.riscv.vsetvli(i64 %avl, i64 2, i64 0)
tail call void @foo()
%1 = tail call <vscale x 1 x double> @llvm.riscv.vfadd.nxv1f64.nxv1f64(<vscale x 1 x double> %a, <vscale x 1 x double> %b, i64 %avl)
ret <vscale x 1 x double> %1
}