[RISCV] Teach VSETVLI insertion to merge the unused VSETVLI with the one need to be insert after it.

[jacquesguan]

Summary

If a vsetvli instruction is not compatible with the next vector instruction, and there is no other things that may update or use VL/VTYPE, we could merge it with the next vsetvli instruction that should be insert for the vector instruction.
This commit only merge VTYPE with the former vsetvli instruction which has the same VL.

[frasercrmck]

llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp

636

Could this be a property of VSETVLIInfo somehow? It seems odd to track two separate bits of state.

If not I think the variable needs a better name.

677

Is this path not setting VSetMI by inserting a VSETVLI?

llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll

1

It would be helpful if the test case was pre-committed so we can better see the changes introduced by this patch.

[jacquesguan]

llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll

1

Thanks, I added the test in D106865.

[jacquesguan]

Add field MI to class VSETVLIInfo for recording the merge target VSET(I)VLI.

llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp

636

Done, thanks.

[craig.topper]

llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp

636

Putting it in VSETVLIINfo allocates space for every basic block as part of the global analysis. But it is only used in the function that runs after the global analysis is done. From that perspective I'm not sure it makes sense to be in the class.

689

What if the original vsetvli had a smaller vlmax than the instruction we're inserting for. Won't we lose the clipping that should have existed?

llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll

13

What if a0 is used by another instruction or a pointer increment? This changes VLMAX which changes where AVL gets clipped, potentially breaking the other uses.

[jacquesguan]

llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp

689

Yes, so we can only merge vsetvli only if those two vsetvli have the same AVL and the same VLMAX or we can confirm that the first vsetvli's result won't be used.

[jacquesguan]

Remove MI from VSETVLIInfo, add constraints that should have the same VLMAX for merging vsetvli.

[jacquesguan]

llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp

677

No need to set it here, CurInfo is definitely not from an explicit VSET(I)VLI of this MBB.

[jacquesguan]

llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll

13

A new condition added for checking if is a virtual register.

[craig.topper]

llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp

688

Is the hasSameAVL case tested? Both the tests use the output of the vsetvli intrinsic as the AVL for the instruction.

[jacquesguan]

Add test cases that use the same AVL.

[jacquesguan]

llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp

688

Done, thanks.

[jacquesguan]

Fix lint.

[craig.topper]

LGTM

llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp

bool RISCVInsertVSETVLI::needVSETVLIPHI(const VSETVLIInfo &Require,
 
   // If all the incoming values to the PHI checked out, we don't need
   // to insert a VSETVLI.
   return false;
 }
 
 void RISCVInsertVSETVLI::emitVSETVLIs(MachineBasicBlock &MBB) {
   VSETVLIInfo CurInfo;
+  MachineInstr *VSetMI = nullptr;
 
   for (MachineInstr &MI : MBB) {
     // If this is an explicit VSETVLI or VSETIVLI, update our state.
     if (MI.getOpcode() == RISCV::PseudoVSETVLI ||
         MI.getOpcode() == RISCV::PseudoVSETIVLI) {
       // Conservatively, mark the VL and VTYPE as live.
       assert(MI.getOperand(3).getReg() == RISCV::VL &&
              MI.getOperand(4).getReg() == RISCV::VTYPE &&
              "Unexpected operands where VL and VTYPE should be");
       MI.getOperand(3).setIsDead(false);
       MI.getOperand(4).setIsDead(false);
       CurInfo = getInfoForVSETVLI(MI);
+      VSetMI = &MI;
       continue;
     }
 
     uint64_t TSFlags = MI.getDesc().TSFlags;
     if (RISCVII::hasSEWOp(TSFlags)) {
       VSETVLIInfo NewInfo = computeInfoForInstr(MI, TSFlags, MRI);
       if (RISCVII::hasVLOp(TSFlags)) {
         MachineOperand &VLOp = MI.getOperand(MI.getNumExplicitOperands() - 2);
if (RISCVII::hasSEWOp(TSFlags)) {
       if (!CurInfo.isValid()) {
         // We haven't found any vector instructions or VL/VTYPE changes yet,
         // use the predecessor information.
         assert(BlockInfo[MBB.getNumber()].Pred.isValid() &&
                "Expected a valid predecessor state.");
         if (needVSETVLI(NewInfo, BlockInfo[MBB.getNumber()].Pred) &&
             needVSETVLIPHI(NewInfo, MBB)) {
           insertVSETVLI(MBB, MI, NewInfo, BlockInfo[MBB.getNumber()].Pred);
           CurInfo = NewInfo;
         }
       } else {
         // If this instruction isn't compatible with the previous VL/VTYPE
         // we need to insert a VSETVLI.
         if (needVSETVLI(NewInfo, CurInfo)) {
+          // If the previous VL/VTYPE is set by VSETVLI and do not use, Merge it
+          // with current VL/VTYPE.
+          if (VSetMI &&
+              (CurInfo.hasSameAVL(NewInfo) ||
+               (NewInfo.hasAVLReg() &&
+                NewInfo.getAVLReg() == VSetMI->getOperand(0).getReg())))
+            VSetMI->getOperand(2).setImm(NewInfo.encodeVTYPE());
+          else
             insertVSETVLI(MBB, MI, NewInfo, CurInfo);
           CurInfo = NewInfo;
         }
       }
+      VSetMI = nullptr;
     }
 
     // If this is something updates VL/VTYPE that we don't know about, set
     // the state to unknown.
     if (MI.isCall() || MI.isInlineAsm() || MI.modifiesRegister(RISCV::VL) ||
         MI.modifiesRegister(RISCV::VTYPE)) {
       CurInfo = VSETVLIInfo::getUnknown();
+      VSetMI = nullptr;
     }
   }
 }
 
 bool RISCVInsertVSETVLI::runOnMachineFunction(MachineFunction &MF) {
   // Skip if the vector extension is not enabled.
   const RISCVSubtarget &ST = MF.getSubtarget<RISCVSubtarget>();
   if (!ST.hasStdExtV())

llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=+m,+f,+d,+a,+c,+experimental-v \
+; RUN:    -verify-machineinstrs -O2 < %s | FileCheck %s
+
+declare i64 @llvm.riscv.vsetvli(i64, i64, i64)
+declare <vscale x 1 x double> @llvm.riscv.vfadd.nxv1f64.nxv1f64(<vscale x 1 x double>, <vscale x 1 x double>, i64)
+declare void @foo()
+
+define <vscale x 1 x double> @test1(i64 %avl, i8 zeroext %cond, <vscale x 1 x double> %a, <vscale x 1 x double> %b) nounwind {
+; CHECK-LABEL: test1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e64, m1, ta, mu
+; CHECK-NEXT:    vfadd.vv v8, v8, v9
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call i64 @llvm.riscv.vsetvli(i64 %avl, i64 2, i64 0)
+  %1 = tail call <vscale x 1 x double> @llvm.riscv.vfadd.nxv1f64.nxv1f64(<vscale x 1 x double> %a, <vscale x 1 x double> %b, i64 %0)
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test2(i64 %avl, i8 zeroext %cond, <vscale x 1 x double> %a, <vscale x 1 x double> %b) nounwind {
+; CHECK-LABEL: test2:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e64, m1, ta, mu
+; CHECK-NEXT:    vfadd.vv v8, v8, v9
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call i64 @llvm.riscv.vsetvli(i64 %avl, i64 2, i64 0)
+  %1 = tail call <vscale x 1 x double> @llvm.riscv.vfadd.nxv1f64.nxv1f64(<vscale x 1 x double> %a, <vscale x 1 x double> %b, i64 %avl)
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test3(i64 %avl, i8 zeroext %cond, <vscale x 1 x double> %a, <vscale x 1 x double> %b) nounwind {
+; CHECK-LABEL: test3:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    addi sp, sp, -32
+; CHECK-NEXT:    sd ra, 24(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    sd s0, 16(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    csrr a1, vlenb
+; CHECK-NEXT:    slli a1, a1, 1
+; CHECK-NEXT:    sub sp, sp, a1
+; CHECK-NEXT:    csrr a1, vlenb
+; CHECK-NEXT:    add a1, a1, sp
+; CHECK-NEXT:    addi a1, a1, 16
+; CHECK-NEXT:    vs1r.v v9, (a1) # Unknown-size Folded Spill
+; CHECK-NEXT:    addi a1, sp, 16
+; CHECK-NEXT:    vs1r.v v8, (a1) # Unknown-size Folded Spill
+; CHECK-NEXT:    vsetvli s0, a0, e32, m1, ta, mu
+; CHECK-NEXT:    call foo@plt
+; CHECK-NEXT:    vsetvli zero, s0, e64, m1, ta, mu
+; CHECK-NEXT:    csrr a0, vlenb
+; CHECK-NEXT:    add a0, a0, sp
+; CHECK-NEXT:    addi a0, a0, 16
+; CHECK-NEXT:    vl1r.v v25, (a0) # Unknown-size Folded Reload
+; CHECK-NEXT:    addi a0, sp, 16
+; CHECK-NEXT:    vl1r.v v26, (a0) # Unknown-size Folded Reload
+; CHECK-NEXT:    vfadd.vv v8, v26, v25
+; CHECK-NEXT:    csrr a0, vlenb
+; CHECK-NEXT:    slli a0, a0, 1
+; CHECK-NEXT:    add sp, sp, a0
+; CHECK-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    addi sp, sp, 32
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call i64 @llvm.riscv.vsetvli(i64 %avl, i64 2, i64 0)
+  tail call void @foo()
+  %1 = tail call <vscale x 1 x double> @llvm.riscv.vfadd.nxv1f64.nxv1f64(<vscale x 1 x double> %a, <vscale x 1 x double> %b, i64 %0)
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test4(i64 %avl, i8 zeroext %cond, <vscale x 1 x double> %a, <vscale x 1 x double> %b) nounwind {
+; CHECK-LABEL: test4:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    addi sp, sp, -32
+; CHECK-NEXT:    sd ra, 24(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    sd s0, 16(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    csrr a1, vlenb
+; CHECK-NEXT:    slli a1, a1, 1
+; CHECK-NEXT:    sub sp, sp, a1
+; CHECK-NEXT:    csrr a1, vlenb
+; CHECK-NEXT:    add a1, a1, sp
+; CHECK-NEXT:    addi a1, a1, 16
+; CHECK-NEXT:    vs1r.v v9, (a1) # Unknown-size Folded Spill
+; CHECK-NEXT:    addi a1, sp, 16
+; CHECK-NEXT:    vs1r.v v8, (a1) # Unknown-size Folded Spill
+; CHECK-NEXT:    mv s0, a0
+; CHECK-NEXT:    vsetvli a0, a0, e32, m1, ta, mu
+; CHECK-NEXT:    call foo@plt
+; CHECK-NEXT:    vsetvli zero, s0, e64, m1, ta, mu
+; CHECK-NEXT:    csrr a0, vlenb
+; CHECK-NEXT:    add a0, a0, sp
+; CHECK-NEXT:    addi a0, a0, 16
+; CHECK-NEXT:    vl1r.v v25, (a0) # Unknown-size Folded Reload
+; CHECK-NEXT:    addi a0, sp, 16
+; CHECK-NEXT:    vl1r.v v26, (a0) # Unknown-size Folded Reload
+; CHECK-NEXT:    vfadd.vv v8, v26, v25
+; CHECK-NEXT:    csrr a0, vlenb
+; CHECK-NEXT:    slli a0, a0, 1
+; CHECK-NEXT:    add sp, sp, a0
+; CHECK-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    addi sp, sp, 32
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call i64 @llvm.riscv.vsetvli(i64 %avl, i64 2, i64 0)
+  tail call void @foo()
+  %1 = tail call <vscale x 1 x double> @llvm.riscv.vfadd.nxv1f64.nxv1f64(<vscale x 1 x double> %a, <vscale x 1 x double> %b, i64 %avl)
+  ret <vscale x 1 x double> %1
+}
+