[PowerPC]Add addex instruction definition and MC tests

[lei]

Summary

Add td definitions and asm/disasm tests for the addex instruction introduced in
ISA 3.0.

[nemanjai]

LGTM.

[amyk]

This LGTM.

llvm/lib/Target/PowerPC/PPCInstrFormats.td

2162

nit: One extra space.

[NeHuang]

LGTM.

llvm/lib/Target/PowerPC/P9InstrResources.td

def : InstRW<[],
   TRAP,
   RFCI,
   RFDI,
   RFMCI,
   SC,
   DCBA,
   DCBI,
   DCCCI,
-  ICCCI
+  ICCCI,
+  ADDEX
 )> { let Unsupported = 1; }

llvm/lib/Target/PowerPC/PPCInstrFormats.td

class Z23Form_8<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr,
   let Inst{11-14} = 0;
   let Inst{15} = R;
   let Inst{16-20} = VRB;
   let Inst{21-22} = idx;
   let Inst{23-30} = xo;
   let Inst{31}    = RC;
 }
 
+class Z23Form_RTAB5_CY2<bits<6> opcode, bits<8> xo, dag OOL, dag IOL,
+                        string asmstr, InstrItinClass itin, list<dag> pattern>
+         : I<opcode, OOL, IOL, asmstr, itin> {
+  bits<5> RT;
+  bits<5> RA;
+  bits<5> RB;
+  bits<2> CY;
+
+  let Pattern = pattern;
+
+  let Inst{6-10}  = RT;
+  let Inst{11-15} = RA;
+  let Inst{16-20} = RB;
+  let Inst{21-22} = CY;
+  let Inst{23-30} = xo;
+  let Inst{31} = 0;
+}
+
 //===----------------------------------------------------------------------===//
 // EmitTimePseudo won't have encoding information for the [MC]CodeEmitter
 // stuff
 class PPCEmitTimePseudo<dag OOL, dag IOL, string asmstr, list<dag> pattern>
     : I<0, OOL, IOL, asmstr, NoItinerary> {
   let isCodeGenOnly = 1;
   let PPC64 = 0;
   let Pattern = pattern;
   let Inst{31-0} = 0;

llvm/lib/Target/PowerPC/PPCInstrInfo.td

 
 let Predicates = [IsISA3_0] in {
 def MODSW : XForm_8<31, 779, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
                         "modsw $rT, $rA, $rB", IIC_IntDivW,
                         [(set i32:$rT, (srem i32:$rA, i32:$rB))]>;
 def MODUW : XForm_8<31, 267, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
                         "moduw $rT, $rA, $rB", IIC_IntDivW,
                         [(set i32:$rT, (urem i32:$rA, i32:$rB))]>;
+let hasSideEffects = 1 in
+def ADDEX : Z23Form_RTAB5_CY2<31, 170, (outs gprc:$rT),
+                              (ins gprc:$rA, gprc:$rB, u2imm:$CY),
+                              "addex $rT, $rA, $rB, $CY", IIC_IntGeneral, []>;
 }
 
 let PPC970_Unit = 1, hasSideEffects = 0 in {  // FXU Operations.
 // XO-Form instructions.  Arithmetic instructions that can set overflow bit
 let isCommutable = 1 in
 defm ADD4  : XOForm_1rx<31, 266, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
                         "add", "$rT, $rA, $rB", IIC_IntSimple,
                         [(set i32:$rT, (add i32:$rA, i32:$rB))]>;

llvm/test/MC/Disassembler/PowerPC/ppc64-encoding.txt

 0x7c 0x43 0x27 0x16
 
 # CHECK: divweuo. 2, 3, 4
 0x7c 0x43 0x27 0x17
 
 # CHECK: modsw 2, 3, 4
 0x7c 0x43 0x26 0x16
 
+# CHECK: addex 2, 4, 5, 0
+0x7C 0x44 0x29 0x54
+
 # CHECK: moduw 2, 3, 4
 0x7c 0x43 0x22 0x16
 
 # CHECK: modsd 2, 3, 4
 0x7c 0x43 0x26 0x12
 
 # CHECK: modud 2, 3, 4
 0x7c 0x43 0x22 0x12

llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding.txt

 0x16 0x27 0x43 0x7c
 
 # CHECK: divweuo. 2, 3, 4
 0x17 0x27 0x43 0x7c
 
 # CHECK: modsw 2, 3, 4
 0x16 0x26 0x43 0x7c
 
+# CHECK: addex 2, 4, 5, 0
+0x54 0x29 0x44 0x7C
+
 # CHECK: moduw 2, 3, 4
 0x16 0x22 0x43 0x7c
 
 # CHECK: modsd 2, 3, 4
 0x12 0x26 0x43 0x7c
 
 # CHECK: modud 2, 3, 4
 0x12 0x22 0x43 0x7c

llvm/test/MC/PowerPC/ppc64-encoding.s

 # CHECK-LE: adde. 2, 3, 4                   # encoding: [0x15,0x21,0x43,0x7c]
             adde. 2, 3, 4
 # CHECK-BE: addeo 2, 3, 4                   # encoding: [0x7c,0x43,0x25,0x14]
 # CHECK-LE: addeo 2, 3, 4                   # encoding: [0x14,0x25,0x43,0x7c]
             addeo 2, 3, 4
 # CHECK-BE: addeo. 2, 3, 4                  # encoding: [0x7c,0x43,0x25,0x15]
 # CHECK-LE: addeo. 2, 3, 4                  # encoding: [0x15,0x25,0x43,0x7c]
             addeo. 2, 3, 4
+# CHECK-BE: addex 2, 4, 5, 0                # encoding: [0x7c,0x44,0x29,0x54]
+# CHECK-LE: addex 2, 4, 5, 0                # encoding: [0x54,0x29,0x44,0x7c]
+            addex 2, 4, 5, 0
 # CHECK-BE: subfe 2, 3, 4                   # encoding: [0x7c,0x43,0x21,0x10]
 # CHECK-LE: subfe 2, 3, 4                   # encoding: [0x10,0x21,0x43,0x7c]
             subfe 2, 3, 4
 # CHECK-BE: subfe. 2, 3, 4                  # encoding: [0x7c,0x43,0x21,0x11]
 # CHECK-LE: subfe. 2, 3, 4                  # encoding: [0x11,0x21,0x43,0x7c]
             subfe. 2, 3, 4
 # CHECK-BE: subfeo 2, 3, 4                  # encoding: [0x7c,0x43,0x25,0x10]
 # CHECK-LE: subfeo 2, 3, 4                  # encoding: [0x10,0x25,0x43,0x7c]