Merge all the llvm-exegesis unit tests into a single binary

[tstellar]

Summary

These tests access private symbols in the backends, so they cannot link
against libLLVM.so and must be statically linked. Linking these tests
can be slow and with debug builds the resulting binaries use a lot of
disk space.

By merging them into a single test binary means we now only need to
statically link 1 test instead of 6, which helps reduce the build
times and saves disk space.

[courbet]

Thanks for doing this.

There are a few formatting errors to fix.

llvm/tools/llvm-exegesis/lib/BenchmarkResult.h

struct InstructionBenchmark {
   class Error readYamlFrom(const LLVMState &State, StringRef InputContent);
 
   // Write functions, non-const because of YAML traits.
   class Error writeYamlTo(const LLVMState &State, raw_ostream &S);
 
   class Error writeYaml(const LLVMState &State, const StringRef Filename);
 };
 
+bool operator==(const BenchmarkMeasure &A, const BenchmarkMeasure &B);
+
 //------------------------------------------------------------------------------
 // Utilities to work with Benchmark measures.
 
 // A class that measures stats over benchmark measures.
 class PerInstructionStats {
 public:
   void push(const BenchmarkMeasure &BM);
 

llvm/tools/llvm-exegesis/lib/BenchmarkResult.cpp

if (Key.empty())
     Key = BM.Key;
   assert(Key == BM.Key);
   ++NumValues;
   SumValues += BM.PerInstructionValue;
   MaxValue = std::max(MaxValue, BM.PerInstructionValue);
   MinValue = std::min(MinValue, BM.PerInstructionValue);
 }
 
+bool operator==(const BenchmarkMeasure &A, const BenchmarkMeasure &B) {
+  return std::tie(A.Key, A.PerInstructionValue, A.PerSnippetValue) ==
+         std::tie(B.Key, B.PerInstructionValue, B.PerSnippetValue);
+}
+
+
 } // namespace exegesis
 } // namespace llvm

llvm/unittests/tools/llvm-exegesis/AArch64/CMakeLists.txt

-include_directories(
+add_llvm_exegesis_unittest_includes(
   ${LLVM_MAIN_SRC_DIR}/lib/Target/AArch64
   ${LLVM_BINARY_DIR}/lib/Target/AArch64
   ${LLVM_MAIN_SRC_DIR}/tools/llvm-exegesis/lib
   )
 
-set(LLVM_LINK_COMPONENTS
+add_llvm_exegesis_unittest_link_components(
   MC
   MCParser
   Object
   Support
   Symbolize
   AArch64
   )
 
-add_llvm_target_unittest(LLVMExegesisAArch64Tests
+add_llvm_exegesis_unittest_sources(
   TargetTest.cpp
   )
-target_link_libraries(LLVMExegesisAArch64Tests PRIVATE
-  LLVMExegesis
+add_llvm_exegesis_unittest_link_libraries(
   LLVMExegesisAArch64)

llvm/unittests/tools/llvm-exegesis/ARM/CMakeLists.txt

-include_directories(
+add_llvm_exegesis_unittest_includes(
   ${LLVM_MAIN_SRC_DIR}/lib/Target/ARM
   ${LLVM_BINARY_DIR}/lib/Target/ARM
   ${LLVM_MAIN_SRC_DIR}/tools/llvm-exegesis/lib
   )
 
-set(LLVM_LINK_COMPONENTS
+add_llvm_exegesis_unittest_link_components(
   Core
   MC
   MCParser
   Object
   Support
   Symbolize
   ARM
   )
 
-add_llvm_target_unittest(LLVMExegesisARMTests
+add_llvm_exegesis_unittest_sources(
   AssemblerTest.cpp
   )
-target_link_libraries(LLVMExegesisARMTests PRIVATE LLVMExegesis)

llvm/unittests/tools/llvm-exegesis/CMakeLists.txt

-include_directories(
+set(exegesis_includes
   ${LLVM_MAIN_SRC_DIR}/tools/llvm-exegesis/lib
   )
 
 set(LLVM_LINK_COMPONENTS
   MC
   MCParser
   Object
   Support
   Symbolize
   )
 
-add_llvm_unittest(LLVMExegesisTests
+set(exegesis_sources
   BenchmarkRunnerTest.cpp
   ClusteringTest.cpp
   PerfHelperTest.cpp
   RegisterValueTest.cpp
   SnippetGeneratorTest.cpp
   )
-target_link_libraries(LLVMExegesisTests PRIVATE LLVMExegesis)
+
+set(exegesis_link_libraries LLVMExegesis)
+
+function(add_llvm_exegesis_unittest_includes)
+  set(exegesis_includes ${exegesis_includes} ${ARGV} PARENT_SCOPE)
+endfunction()
+
+function(add_llvm_exegesis_unittest_sources)
+  set(sources ${ARGV})
+  list(TRANSFORM sources PREPEND "${CMAKE_CURRENT_LIST_DIR}/")
+  set(exegesis_sources ${exegesis_sources} ${sources} PARENT_SCOPE)
+endfunction()
+
+function(add_llvm_exegesis_unittest_link_components comps)
+  set(LLVM_LINK_COMPONENTS ${LLVM_LINK_COMPONENTS} ${ARGV} PARENT_SCOPE)
+endfunction()
+
+function(add_llvm_exegesis_unittest_link_libraries libs)
+  set(exegesis_link_libraries ${exegesis_link_libraries} ${ARGV} PARENT_SCOPE)
+endfunction()
+
 
 if(LLVM_TARGETS_TO_BUILD MATCHES "X86")
-  add_subdirectory(X86)
+  include(X86/CMakeLists.txt)
 endif()
 if(LLVM_TARGETS_TO_BUILD MATCHES "ARM")
-  add_subdirectory(ARM)
+  include(ARM/CMakeLists.txt)
 endif()
 if(LLVM_TARGETS_TO_BUILD MATCHES "AArch64")
-  add_subdirectory(AArch64)
+  include(AArch64/CMakeLists.txt)
 endif()
 if(LLVM_TARGETS_TO_BUILD MATCHES "PowerPC")
-  add_subdirectory(PowerPC)
+  include(PowerPC/CMakeLists.txt)
 endif()
 if(LLVM_TARGETS_TO_BUILD MATCHES "Mips")
-  add_subdirectory(Mips)
+  include(Mips/CMakeLists.txt)
 endif()
+
+include_directories(${exegesis_includes})
+
+list(REMOVE_DUPLICATES LLVM_LINK_COMPONENTS)
+
+add_llvm_target_unittest(LLVMExegesisTests
+  ${exegesis_sources}
+  )
+target_link_libraries(LLVMExegesisTests PRIVATE ${exegesis_link_libraries})

llvm/unittests/tools/llvm-exegesis/Mips/BenchmarkResultTest.cpp

 using ::testing::Pointwise;
 using ::testing::Property;
 
 using llvm::unittest::TempDir;
 
 namespace llvm {
 namespace exegesis {
 
-bool operator==(const BenchmarkMeasure &A, const BenchmarkMeasure &B) {
-  return std::tie(A.Key, A.PerInstructionValue, A.PerSnippetValue) ==
-         std::tie(B.Key, B.PerInstructionValue, B.PerSnippetValue);
-}
-
 static std::string Dump(const MCInst &McInst) {
   std::string Buffer;
   raw_string_ostream OS(Buffer);
   McInst.print(OS);
   return Buffer;
 }
 
 MATCHER(EqMCInst, "") {
   const std::string Lhs = Dump(get<0>(arg));
   const std::string Rhs = Dump(get<1>(arg));
   if (Lhs != Rhs) {
     *result_listener << Lhs << " <=> " << Rhs;
     return false;
   }
   return true;
 }
 
 namespace {
 
-class BenchmarkResultTest : public MipsTestBase {};
+class MipsBenchmarkResultTest : public MipsTestBase {};
 
-TEST_F(BenchmarkResultTest, WriteToAndReadFromDisk) {
+TEST_F(MipsBenchmarkResultTest, WriteToAndReadFromDisk) {
   ExitOnError ExitOnErr;
 
   InstructionBenchmark ToDisk;
 
   ToDisk.Key.Instructions.push_back(MCInstBuilder(Mips::XOR)
                                         .addReg(Mips::T0)
                                         .addReg(Mips::T1)
                                         .addReg(Mips::T2));
ExitOnErr(ToDisk.writeYaml(State, Filename));
     EXPECT_EQ(FromDisk.LLVMTriple, ToDisk.LLVMTriple);
     EXPECT_EQ(FromDisk.NumRepetitions, ToDisk.NumRepetitions);
     EXPECT_THAT(FromDisk.Measurements, ToDisk.Measurements);
     EXPECT_THAT(FromDisk.Error, ToDisk.Error);
     EXPECT_EQ(FromDisk.Info, ToDisk.Info);
   }
 }
 
-TEST_F(BenchmarkResultTest, PerInstructionStats) {
+TEST_F(MipsBenchmarkResultTest, PerInstructionStats) {
   PerInstructionStats Stats;
   Stats.push(BenchmarkMeasure{"a", 0.5, 0.0});
   Stats.push(BenchmarkMeasure{"a", 1.5, 0.0});
   Stats.push(BenchmarkMeasure{"a", -1.0, 0.0});
   Stats.push(BenchmarkMeasure{"a", 0.0, 0.0});
   EXPECT_EQ(Stats.min(), -1.0);
   EXPECT_EQ(Stats.max(), 1.5);
   EXPECT_EQ(Stats.avg(), 0.25); // (0.5+1.5-1.0+0.0) / 4
 }
 } // namespace
 } // namespace exegesis
 } // namespace llvm

llvm/unittests/tools/llvm-exegesis/Mips/CMakeLists.txt

-include_directories(
+add_llvm_exegesis_unittest_includes(
   ${LLVM_MAIN_SRC_DIR}/lib/Target/Mips
   ${LLVM_BINARY_DIR}/lib/Target/Mips
   ${LLVM_MAIN_SRC_DIR}/tools/llvm-exegesis/lib
   )
 
-set(LLVM_LINK_COMPONENTS
+add_llvm_exegesis_unittest_link_components(
   MC
   MCParser
   Object
   Support
   Symbolize
   Mips
   )
 
-add_llvm_target_unittest(LLVMExegesisMipsTests
+add_llvm_exegesis_unittest_sources(
   BenchmarkResultTest.cpp
   RegisterAliasingTest.cpp
   SnippetGeneratorTest.cpp
   TargetTest.cpp
   )
-target_link_libraries(LLVMExegesisMipsTests PRIVATE
-  LLVMExegesis
+add_llvm_exegesis_unittest_link_libraries(
   LLVMExegesisMips)

llvm/unittests/tools/llvm-exegesis/Mips/RegisterAliasingTest.cpp

 #include "llvm/Support/TargetSelect.h"
 #include "gmock/gmock.h"
 #include "gtest/gtest.h"
 
 namespace llvm {
 namespace exegesis {
 namespace {
 
-class RegisterAliasingTest : public MipsTestBase {};
+class MipsRegisterAliasingTest : public MipsTestBase {};
 
-TEST_F(RegisterAliasingTest, TrackSimpleRegister) {
+TEST_F(MipsRegisterAliasingTest, TrackSimpleRegister) {
   const auto &RegInfo = State.getRegInfo();
   const RegisterAliasingTracker tracker(RegInfo, Mips::T0_64);
   std::set<MCPhysReg> ActualAliasedRegisters;
   for (unsigned I : tracker.aliasedBits().set_bits())
     ActualAliasedRegisters.insert(static_cast<MCPhysReg>(I));
   const std::set<MCPhysReg> ExpectedAliasedRegisters = {Mips::T0, Mips::T0_64};
   ASSERT_THAT(ActualAliasedRegisters, ExpectedAliasedRegisters);
   for (MCPhysReg aliased : ExpectedAliasedRegisters) {
     ASSERT_THAT(tracker.getOrigin(aliased), Mips::T0_64);
   }
 }
 
-TEST_F(RegisterAliasingTest, TrackRegisterClass) {
+TEST_F(MipsRegisterAliasingTest, TrackRegisterClass) {
   // The alias bits for
   // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClassID
   // are the union of the alias bits for ZERO_64, V0_64, V1_64 and S1_64.
   const auto &RegInfo = State.getRegInfo();
   const BitVector NoReservedReg(RegInfo.getNumRegs());
 
   const RegisterAliasingTracker RegClassTracker(
       RegInfo, NoReservedReg,
       RegInfo.getRegClass(
           Mips::GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClassID));
 
   BitVector sum(RegInfo.getNumRegs());
   sum |= RegisterAliasingTracker(RegInfo, Mips::ZERO_64).aliasedBits();
   sum |= RegisterAliasingTracker(RegInfo, Mips::V0_64).aliasedBits();
   sum |= RegisterAliasingTracker(RegInfo, Mips::V1_64).aliasedBits();
   sum |= RegisterAliasingTracker(RegInfo, Mips::S1_64).aliasedBits();
 
   ASSERT_THAT(RegClassTracker.aliasedBits(), sum);
 }
 
-TEST_F(RegisterAliasingTest, TrackRegisterClassCache) {
+TEST_F(MipsRegisterAliasingTest, TrackRegisterClassCache) {
   // Fetching the same tracker twice yields the same pointers.
   const auto &RegInfo = State.getRegInfo();
   const BitVector NoReservedReg(RegInfo.getNumRegs());
   RegisterAliasingTrackerCache Cache(RegInfo, NoReservedReg);
   ASSERT_THAT(&Cache.getRegister(Mips::T0), &Cache.getRegister(Mips::T0));
 
   ASSERT_THAT(&Cache.getRegisterClass(Mips::ACC64RegClassID),
               &Cache.getRegisterClass(Mips::ACC64RegClassID));
 }
 
 } // namespace
 } // namespace exegesis
 } // namespace llvm

llvm/unittests/tools/llvm-exegesis/Mips/SnippetGeneratorTest.cpp

 using testing::AnyOf;
 using testing::ElementsAre;
 using testing::HasSubstr;
 using testing::SizeIs;
 
 MATCHER(IsInvalid, "") { return !arg.isValid(); }
 MATCHER(IsReg, "") { return arg.isReg(); }
 
-class MipsSnippetGeneratorTest : public MipsTestBase {};
-
 template <typename SnippetGeneratorT>
-class SnippetGeneratorTest : public MipsSnippetGeneratorTest {
+class MipsSnippetGeneratorTest : public MipsTestBase {
 protected:
-  SnippetGeneratorTest() : Generator(State, SnippetGenerator::Options()) {}
+  MipsSnippetGeneratorTest() : Generator(State, SnippetGenerator::Options()) {}
 
   std::vector<CodeTemplate> checkAndGetCodeTemplates(unsigned Opcode) {
     randomGenerator().seed(0); // Initialize seed.
     const Instruction &Instr = State.getIC().getInstr(Opcode);
     auto CodeTemplateOrError = Generator.generateCodeTemplates(
         &Instr, State.getRATC().emptyRegisters());
     EXPECT_FALSE(CodeTemplateOrError.takeError()); // Valid configuration.
     return std::move(CodeTemplateOrError.get());
   }
 
   SnippetGeneratorT Generator;
 };
 
-using SerialSnippetGeneratorTest = SnippetGeneratorTest<SerialSnippetGenerator>;
+using MipsSerialSnippetGeneratorTest = MipsSnippetGeneratorTest<SerialSnippetGenerator>;
 
-using ParallelSnippetGeneratorTest =
-    SnippetGeneratorTest<ParallelSnippetGenerator>;
+using MipsParallelSnippetGeneratorTest =
+    MipsSnippetGeneratorTest<ParallelSnippetGenerator>;
 
-TEST_F(SerialSnippetGeneratorTest, ImplicitSelfDependencyThroughExplicitRegs) {
+TEST_F(MipsSerialSnippetGeneratorTest, ImplicitSelfDependencyThroughExplicitRegs) {
   // - ADD
   // - Op0 Explicit Def RegClass(GPR32)
   // - Op1 Explicit Use RegClass(GPR32)
   // - Op2 Explicit Use RegClass(GPR32)
   // - Var0 [Op0]
   // - Var1 [Op1]
   // - Var2 [Op2]
   // - hasAliasingRegisters
   const unsigned Opcode = Mips::ADD;
   const auto CodeTemplates = checkAndGetCodeTemplates(Opcode);
   ASSERT_THAT(CodeTemplates, SizeIs(1));
   const auto &CT = CodeTemplates[0];
   EXPECT_THAT(CT.Execution, ExecutionMode::SERIAL_VIA_EXPLICIT_REGS);
   ASSERT_THAT(CT.Instructions, SizeIs(1));
   const InstructionTemplate &IT = CT.Instructions[0];
   EXPECT_THAT(IT.getOpcode(), Opcode);
   ASSERT_THAT(IT.getVariableValues(), SizeIs(3));
   EXPECT_THAT(IT.getVariableValues(),
               AnyOf(ElementsAre(IsReg(), IsInvalid(), IsReg()),
                     ElementsAre(IsReg(), IsReg(), IsInvalid())))
       << "Op0 is either set to Op1 or to Op2";
 }
 
-TEST_F(SerialSnippetGeneratorTest,
+TEST_F(MipsSerialSnippetGeneratorTest,
        ImplicitSelfDependencyThroughExplicitRegsForbidAll) {
   // - XOR
   // - Op0 Explicit Def RegClass(GPR32)
   // - Op1 Explicit Use RegClass(GPR32)
   // - Op2 Explicit Use RegClass(GPR32)
   // - Var0 [Op0]
   // - Var1 [Op1]
   // - Var2 [Op2]
   // - hasAliasingRegisters
   randomGenerator().seed(0); // Initialize seed.
   const Instruction &Instr = State.getIC().getInstr(Mips::XOR);
   auto AllRegisters = State.getRATC().emptyRegisters();
   AllRegisters.flip();
   auto Error =
       Generator.generateCodeTemplates(&Instr, AllRegisters).takeError();
   EXPECT_TRUE((bool)Error);
   consumeError(std::move(Error));
 }
 
-TEST_F(ParallelSnippetGeneratorTest, MemoryUse) {
+TEST_F(MipsParallelSnippetGeneratorTest, MemoryUse) {
   // LB reads from memory.
   // - LB
   // - Op0 Explicit Def RegClass(GPR32)
   // - Op1 Explicit Use Memory RegClass(MSA128F16)
   // - Op2 Explicit Use Memory
   // - Var0 [Op0]
   // - Var1 [Op1]
   // - Var2 [Op2]

llvm/unittests/tools/llvm-exegesis/PowerPC/AnalysisTest.cpp

-//===-- AnalysisTest.cpp ---------------------------------------*- C++ -*-===//
+//===-- PPCAnalysisTest.cpp ---------------------------------------*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
 #include "Analysis.h"
 
 #include <cassert>
 #include <memory>
 
 #include "llvm/Support/TargetRegistry.h"
 #include "llvm/Support/TargetSelect.h"
 #include "gmock/gmock.h"
 #include "gtest/gtest.h"
 
 namespace llvm{
 namespace exegesis {
 namespace {
 
 using testing::Pair;
 using testing::UnorderedElementsAre;
 
-class AnalysisTest : public ::testing::Test {
+class PPCAnalysisTest : public ::testing::Test {
 protected:
-  AnalysisTest() {
+  PPCAnalysisTest() {
     const std::string TT = "powerpc64le-unknown-linux";
     std::string error;
     const Target *const TheTarget = TargetRegistry::lookupTarget(TT, error);
     if (!TheTarget) {
       errs() << error << "\n";
       return;
     }
     STI.reset(TheTarget->createMCSubtargetInfo(TT, "pwr9", ""));

 protected:
   std::unique_ptr<const MCSubtargetInfo> STI;
   uint16_t ALUIdx = 0;
   uint16_t ALUEIdx = 0;
   uint16_t ALUOIdx = 0;
   uint16_t IPAGENIdx = 0;
 };
 
-TEST_F(AnalysisTest, ComputeIdealizedProcResPressure_2ALU) {
+TEST_F(PPCAnalysisTest, ComputeIdealizedProcResPressure_2ALU) {
   const auto Pressure =
       computeIdealizedProcResPressure(STI->getSchedModel(), {{ALUIdx, 2}});
   EXPECT_THAT(Pressure, UnorderedElementsAre(Pair(ALUIdx, 2.0)));
 }
 
-TEST_F(AnalysisTest, ComputeIdealizedProcResPressure_1ALUE) {
+TEST_F(PPCAnalysisTest, ComputeIdealizedProcResPressure_1ALUE) {
   const auto Pressure =
       computeIdealizedProcResPressure(STI->getSchedModel(), {{ALUEIdx, 2}});
   EXPECT_THAT(Pressure, UnorderedElementsAre(Pair(ALUEIdx, 2.0)));
 }
 
-TEST_F(AnalysisTest, ComputeIdealizedProcResPressure_1ALU1IPAGEN) {
+TEST_F(PPCAnalysisTest, ComputeIdealizedProcResPressure_1ALU1IPAGEN) {
   const auto Pressure =
       computeIdealizedProcResPressure(STI->getSchedModel(), {{ALUIdx, 1}, {IPAGENIdx, 1}});
   EXPECT_THAT(Pressure, UnorderedElementsAre(Pair(ALUIdx, 1.0),Pair(IPAGENIdx, 1)));
 }
 } // namespace
 } // namespace exegesis
 } // namespace llvm

llvm/unittests/tools/llvm-exegesis/PowerPC/CMakeLists.txt

-include_directories(
+add_llvm_exegesis_unittest_includes(
   ${LLVM_MAIN_SRC_DIR}/lib/Target/PowerPC
   ${LLVM_BINARY_DIR}/lib/Target/PowerPC
   ${LLVM_MAIN_SRC_DIR}/tools/llvm-exegesis/lib
   )
 
-set(LLVM_LINK_COMPONENTS
+add_llvm_exegesis_unittest_link_components(
   MC
   MCParser
   Object
   Support
   Symbolize
   PowerPC
   )
 
-add_llvm_target_unittest(LLVMExegesisPowerPCTests
+add_llvm_exegesis_unittest_sources(
   AnalysisTest.cpp
   SnippetGeneratorTest.cpp
   TargetTest.cpp
   )
-target_link_libraries(LLVMExegesisPowerPCTests PRIVATE
-  LLVMExegesis
+add_llvm_exegesis_unittest_link_libraries(
   LLVMExegesisPowerPC)

llvm/unittests/tools/llvm-exegesis/PowerPC/SnippetGeneratorTest.cpp

 using testing::AnyOf;
 using testing::ElementsAre;
 using testing::HasSubstr;
 using testing::SizeIs;
 
 MATCHER(IsInvalid, "") { return !arg.isValid(); }
 MATCHER(IsReg, "") { return arg.isReg(); }
 
-class PPCSnippetGeneratorTest : public PPCTestBase {};
-
 template <typename SnippetGeneratorT>
-class SnippetGeneratorTest : public PPCSnippetGeneratorTest {
+class PPCSnippetGeneratorTest : public PPCTestBase {
 protected:
-  SnippetGeneratorTest() : Generator(State, SnippetGenerator::Options()) {}
+  PPCSnippetGeneratorTest() : Generator(State, SnippetGenerator::Options()) {}
 
   std::vector<CodeTemplate> checkAndGetCodeTemplates(unsigned Opcode) {
     randomGenerator().seed(0); // Initialize seed.
     const Instruction &Instr = State.getIC().getInstr(Opcode);
     auto CodeTemplateOrError = Generator.generateCodeTemplates(
         &Instr, State.getRATC().emptyRegisters());
     EXPECT_FALSE(CodeTemplateOrError.takeError()); // Valid configuration.
     return std::move(CodeTemplateOrError.get());
   }
 
   SnippetGeneratorT Generator;
 };
 
-using SerialSnippetGeneratorTest = SnippetGeneratorTest<SerialSnippetGenerator>;
+using PPCSerialSnippetGeneratorTest = PPCSnippetGeneratorTest<SerialSnippetGenerator>;
 
-using ParallelSnippetGeneratorTest =
-    SnippetGeneratorTest<ParallelSnippetGenerator>;
+using PPCParallelSnippetGeneratorTest =
+    PPCSnippetGeneratorTest<ParallelSnippetGenerator>;
 
-TEST_F(SerialSnippetGeneratorTest, ImplicitSelfDependencyThroughExplicitRegs) {
+TEST_F(PPCSerialSnippetGeneratorTest, ImplicitSelfDependencyThroughExplicitRegs) {
   // - ADD8
   // - Op0 Explicit Def RegClass(G8RC)
   // - Op1 Explicit Use RegClass(G8RC)
   // - Op2 Explicit Use RegClass(G8RC)
   // - Var0 [Op0]
   // - Var1 [Op1]
   // - Var2 [Op2]
   // - hasAliasingRegisters
   const unsigned Opcode = PPC::ADD8;
   const auto CodeTemplates = checkAndGetCodeTemplates(Opcode);
   ASSERT_THAT(CodeTemplates, SizeIs(1));
   const auto &CT = CodeTemplates[0];
   EXPECT_THAT(CT.Execution, ExecutionMode::SERIAL_VIA_EXPLICIT_REGS);
   ASSERT_THAT(CT.Instructions, SizeIs(1));
   const InstructionTemplate &IT = CT.Instructions[0];
   EXPECT_THAT(IT.getOpcode(), Opcode);
   ASSERT_THAT(IT.getVariableValues(), SizeIs(3));
   EXPECT_THAT(IT.getVariableValues(),
               AnyOf(ElementsAre(IsReg(), IsInvalid(), IsReg()),
                     ElementsAre(IsReg(), IsReg(), IsInvalid())))
       << "Op0 is either set to Op1 or to Op2";
 }
 
-TEST_F(SerialSnippetGeneratorTest, ImplicitSelfDependencyThroughTiedRegs) {
+TEST_F(PPCSerialSnippetGeneratorTest, ImplicitSelfDependencyThroughTiedRegs) {
 
   // - RLDIMI
   // - Op0 Explicit Def RegClass(G8RC)
   // - Op1 Explicit Use RegClass(G8RC) TiedToOp0
   // - Op2 Explicit Use RegClass(G8RC)
   // - Op3 Explicit Use Immediate
   // - Op4 Explicit Use Immediate
   // - Var0 [Op0,Op1]
TEST_F(PPCSerialSnippetGeneratorTest, ImplicitSelfDependencyThroughTiedRegs) {
   ASSERT_THAT(CT.Instructions, SizeIs(1));
   const InstructionTemplate &IT = CT.Instructions[0];
   EXPECT_THAT(IT.getOpcode(), Opcode);
   ASSERT_THAT(IT.getVariableValues(), SizeIs(4));
   EXPECT_THAT(IT.getVariableValues()[2], IsInvalid()) << "Operand 1 is not set";
   EXPECT_THAT(IT.getVariableValues()[3], IsInvalid()) << "Operand 2 is not set";
 }
 
-TEST_F(ParallelSnippetGeneratorTest, MemoryUse) {
+TEST_F(PPCParallelSnippetGeneratorTest, MemoryUse) {
   // - LDX
   // - Op0 Explicit Def RegClass(G8RC)
   // - Op1 Explicit Use Memory RegClass(GPRC)
   // - Op2 Explicit Use Memory RegClass(VSSRC)
   // - Var0 [Op0]
   // - Var1 [Op1]
   // - Var2 [Op2]
   // - hasMemoryOperands

llvm/unittests/tools/llvm-exegesis/X86/BenchmarkResultTest.cpp

 using ::testing::Eq;
 using ::testing::get;
 using ::testing::Pointwise;
 using ::testing::Property;
 
 namespace llvm {
 namespace exegesis {
 
-bool operator==(const BenchmarkMeasure &A, const BenchmarkMeasure &B) {
-  return std::tie(A.Key, A.PerInstructionValue, A.PerSnippetValue) ==
-         std::tie(B.Key, B.PerInstructionValue, B.PerSnippetValue);
-}
-
 static std::string Dump(const MCInst &McInst) {
   std::string Buffer;
   raw_string_ostream OS(Buffer);
   McInst.print(OS);
   return Buffer;
 }
 
 MATCHER(EqMCInst, "") {

llvm/unittests/tools/llvm-exegesis/X86/CMakeLists.txt

-include_directories(
+add_llvm_exegesis_unittest_includes(
   ${LLVM_MAIN_SRC_DIR}/lib/Target/X86
   ${LLVM_BINARY_DIR}/lib/Target/X86
   ${LLVM_MAIN_SRC_DIR}/tools/llvm-exegesis/lib
   )
 
-set(LLVM_LINK_COMPONENTS
+add_llvm_exegesis_unittest_sources(
+  AssemblerTest.cpp
+  BenchmarkResultTest.cpp
+  RegisterAliasingTest.cpp
+  SchedClassResolutionTest.cpp
+  SnippetFileTest.cpp
+  SnippetGeneratorTest.cpp
+  SnippetRepetitorTest.cpp
+  TargetTest.cpp
+  )
+
+add_llvm_exegesis_unittest_link_components(
   Core
   Codegen
   MC
   MCParser
   Object
   Support
   Symbolize
   X86
   )
 
-add_llvm_target_unittest(LLVMExegesisX86Tests
-  AssemblerTest.cpp
-  BenchmarkResultTest.cpp
-  RegisterAliasingTest.cpp
-  SchedClassResolutionTest.cpp
-  SnippetFileTest.cpp
-  SnippetGeneratorTest.cpp
-  SnippetRepetitorTest.cpp
-  TargetTest.cpp
+add_llvm_exegesis_unittest_link_libraries(
+  LLVMExegesisX86
   )
-target_link_libraries(LLVMExegesisX86Tests PRIVATE
-  LLVMExegesis
-  LLVMExegesisX86)

llvm/unittests/tools/llvm-exegesis/X86/RegisterAliasingTest.cpp

-//===-- RegisterAliasingTest.cpp --------------------------------*- C++ -*-===//
+//===-- X86RegisterAliasingTest.cpp --------------------------------*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
 
 #include "RegisterAliasing.h"
 
 #include <cassert>
 #include <memory>
 
 #include "TestBase.h"
 #include "X86InstrInfo.h"
 #include "llvm/Support/TargetRegistry.h"
 #include "llvm/Support/TargetSelect.h"
 #include "gmock/gmock.h"
 #include "gtest/gtest.h"
 
 namespace llvm {
 namespace exegesis {
 namespace {
 
-class RegisterAliasingTest : public X86TestBase {};
+class X86RegisterAliasingTest : public X86TestBase {};
 
-TEST_F(RegisterAliasingTest, TrackSimpleRegister) {
+TEST_F(X86RegisterAliasingTest, TrackSimpleRegister) {
   const auto &RegInfo = State.getRegInfo();
   const RegisterAliasingTracker tracker(RegInfo, X86::EAX);
   std::set<MCPhysReg> ActualAliasedRegisters;
   for (unsigned I : tracker.aliasedBits().set_bits())
     ActualAliasedRegisters.insert(static_cast<MCPhysReg>(I));
   const std::set<MCPhysReg> ExpectedAliasedRegisters = {
       X86::AL, X86::AH, X86::AX, X86::EAX, X86::HAX, X86::RAX};
   ASSERT_THAT(ActualAliasedRegisters, ExpectedAliasedRegisters);
   for (MCPhysReg aliased : ExpectedAliasedRegisters) {
     ASSERT_THAT(tracker.getOrigin(aliased), X86::EAX);
   }
 }
 
-TEST_F(RegisterAliasingTest, TrackRegisterClass) {
+TEST_F(X86RegisterAliasingTest, TrackRegisterClass) {
   // The alias bits for GR8_ABCD_LRegClassID are the union of the alias bits for
   // AL, BL, CL and DL.
   const auto &RegInfo = State.getRegInfo();
   const BitVector NoReservedReg(RegInfo.getNumRegs());
 
   const RegisterAliasingTracker RegClassTracker(
       RegInfo, NoReservedReg, RegInfo.getRegClass(X86::GR8_ABCD_LRegClassID));
 
   BitVector sum(RegInfo.getNumRegs());
   sum |= RegisterAliasingTracker(RegInfo, X86::AL).aliasedBits();
   sum |= RegisterAliasingTracker(RegInfo, X86::BL).aliasedBits();
   sum |= RegisterAliasingTracker(RegInfo, X86::CL).aliasedBits();
   sum |= RegisterAliasingTracker(RegInfo, X86::DL).aliasedBits();
 
   ASSERT_THAT(RegClassTracker.aliasedBits(), sum);
 }
 
-TEST_F(RegisterAliasingTest, TrackRegisterClassCache) {
+TEST_F(X86RegisterAliasingTest, TrackRegisterClassCache) {
   // Fetching twice the same tracker yields the same pointers.
   const auto &RegInfo = State.getRegInfo();
   const BitVector NoReservedReg(RegInfo.getNumRegs());
   RegisterAliasingTrackerCache Cache(RegInfo, NoReservedReg);
   ASSERT_THAT(&Cache.getRegister(X86::AX), &Cache.getRegister(X86::AX));
 
   ASSERT_THAT(&Cache.getRegisterClass(X86::GR8_ABCD_LRegClassID),
               &Cache.getRegisterClass(X86::GR8_ABCD_LRegClassID));
 }
 
 } // namespace
 } // namespace exegesis
 } // namespace llvm

llvm/unittests/tools/llvm-exegesis/X86/SchedClassResolutionTest.cpp

 
 namespace llvm {
 namespace exegesis {
 namespace {
 
 using testing::Pair;
 using testing::UnorderedElementsAre;
 
-class SchedClassResolutionTest : public X86TestBase {
+class X86SchedClassResolutionTest : public X86TestBase {
 protected:
-  SchedClassResolutionTest() : STI(State.getSubtargetInfo()) {
+  X86SchedClassResolutionTest() : STI(State.getSubtargetInfo()) {
     // Compute the ProxResIdx of ports uses in tests.
     const auto &SM = STI.getSchedModel();
     for (unsigned I = 0, E = SM.getNumProcResourceKinds(); I < E; ++I) {
       const std::string Name = SM.getProcResource(I)->Name;
       if (Name == "HWPort0") {
         P0Idx = I;
       } else if (Name == "HWPort1") {
         P1Idx = I;
protected:
   uint16_t P0Idx = 0;
   uint16_t P1Idx = 0;
   uint16_t P5Idx = 0;
   uint16_t P6Idx = 0;
   uint16_t P05Idx = 0;
   uint16_t P0156Idx = 0;
 };
 
-TEST_F(SchedClassResolutionTest, ComputeIdealizedProcResPressure_2P0) {
+TEST_F(X86SchedClassResolutionTest, ComputeIdealizedProcResPressure_2P0) {
   const auto Pressure =
       computeIdealizedProcResPressure(STI.getSchedModel(), {{P0Idx, 2}});
   EXPECT_THAT(Pressure, UnorderedElementsAre(Pair(P0Idx, 2.0)));
 }
 
-TEST_F(SchedClassResolutionTest, ComputeIdealizedProcResPressure_2P05) {
+TEST_F(X86SchedClassResolutionTest, ComputeIdealizedProcResPressure_2P05) {
   const auto Pressure =
       computeIdealizedProcResPressure(STI.getSchedModel(), {{P05Idx, 2}});
   EXPECT_THAT(Pressure,
               UnorderedElementsAre(Pair(P0Idx, 1.0), Pair(P5Idx, 1.0)));
 }
 
-TEST_F(SchedClassResolutionTest, ComputeIdealizedProcResPressure_2P05_2P0156) {
+TEST_F(X86SchedClassResolutionTest, ComputeIdealizedProcResPressure_2P05_2P0156) {
   const auto Pressure = computeIdealizedProcResPressure(
       STI.getSchedModel(), {{P05Idx, 2}, {P0156Idx, 2}});
   EXPECT_THAT(Pressure,
               UnorderedElementsAre(Pair(P0Idx, 1.0), Pair(P1Idx, 1.0),
                                    Pair(P5Idx, 1.0), Pair(P6Idx, 1.0)));
 }
 
-TEST_F(SchedClassResolutionTest,
+TEST_F(X86SchedClassResolutionTest,
        ComputeIdealizedProcResPressure_1P1_1P05_2P0156) {
   const auto Pressure = computeIdealizedProcResPressure(
       STI.getSchedModel(), {{P1Idx, 1}, {P05Idx, 1}, {P0156Idx, 2}});
   EXPECT_THAT(Pressure,
               UnorderedElementsAre(Pair(P0Idx, 1.0), Pair(P1Idx, 1.0),
                                    Pair(P5Idx, 1.0), Pair(P6Idx, 1.0)));
 }
 
 } // namespace
 } // namespace exegesis
 } // namespace llvm

llvm/unittests/tools/llvm-exegesis/X86/SnippetGeneratorTest.cpp

 using testing::HasSubstr;
 using testing::Not;
 using testing::SizeIs;
 using testing::UnorderedElementsAre;
 
 MATCHER(IsInvalid, "") { return !arg.isValid(); }
 MATCHER(IsReg, "") { return arg.isReg(); }
 
-class X86SnippetGeneratorTest : public X86TestBase {
-protected:
-  X86SnippetGeneratorTest() : InstrInfo(State.getInstrInfo()) {}
-
-  const MCInstrInfo &InstrInfo;
-};
-
 template <typename SnippetGeneratorT>
-class SnippetGeneratorTest : public X86SnippetGeneratorTest {
+class X86SnippetGeneratorTest : public X86TestBase {
 protected:
-  SnippetGeneratorTest() : Generator(State, SnippetGenerator::Options()) {}
+  X86SnippetGeneratorTest() : Generator(State, SnippetGenerator::Options()),
+                        InstrInfo(State.getInstrInfo()) {}
 
   std::vector<CodeTemplate> checkAndGetCodeTemplates(unsigned Opcode) {
     randomGenerator().seed(0); // Initialize seed.
     const Instruction &Instr = State.getIC().getInstr(Opcode);
     auto CodeTemplateOrError = Generator.generateCodeTemplates(
         &Instr, State.getRATC().emptyRegisters());
     EXPECT_FALSE(CodeTemplateOrError.takeError()); // Valid configuration.
     return std::move(CodeTemplateOrError.get());
   }
 
   SnippetGeneratorT Generator;
+  const MCInstrInfo &InstrInfo;
 };
 
-using SerialSnippetGeneratorTest = SnippetGeneratorTest<SerialSnippetGenerator>;
+using X86SerialSnippetGeneratorTest = X86SnippetGeneratorTest<SerialSnippetGenerator>;
 
-using ParallelSnippetGeneratorTest =
-    SnippetGeneratorTest<ParallelSnippetGenerator>;
+using X86ParallelSnippetGeneratorTest =
+    X86SnippetGeneratorTest<ParallelSnippetGenerator>;
 
-TEST_F(SerialSnippetGeneratorTest, ImplicitSelfDependencyThroughImplicitReg) {
+TEST_F(X86SerialSnippetGeneratorTest, ImplicitSelfDependencyThroughImplicitReg) {
   // - ADC16i16
   // - Op0 Explicit Use Immediate
   // - Op1 Implicit Def Reg(AX)
   // - Op2 Implicit Def Reg(EFLAGS)
   // - Op3 Implicit Use Reg(AX)
   // - Op4 Implicit Use Reg(EFLAGS)
   // - Var0 [Op0]
   // - hasAliasingImplicitRegisters (execution is always serial)
TEST_F(X86SerialSnippetGeneratorTest, ImplicitSelfDependencyThroughImplicitReg) {
   EXPECT_THAT(CT.Execution, ExecutionMode::ALWAYS_SERIAL_IMPLICIT_REGS_ALIAS);
   ASSERT_THAT(CT.Instructions, SizeIs(1));
   const InstructionTemplate &IT = CT.Instructions[0];
   EXPECT_THAT(IT.getOpcode(), Opcode);
   ASSERT_THAT(IT.getVariableValues(), SizeIs(1)); // Imm.
   EXPECT_THAT(IT.getVariableValues()[0], IsInvalid()) << "Immediate is not set";
 }
 
-TEST_F(SerialSnippetGeneratorTest, ImplicitSelfDependencyThroughTiedRegs) {
+TEST_F(X86SerialSnippetGeneratorTest, ImplicitSelfDependencyThroughTiedRegs) {
   // - ADD16ri
   // - Op0 Explicit Def RegClass(GR16)
   // - Op1 Explicit Use RegClass(GR16) TiedToOp0
   // - Op2 Explicit Use Immediate
   // - Op3 Implicit Def Reg(EFLAGS)
   // - Var0 [Op0,Op1]
   // - Var1 [Op2]
   // - hasTiedRegisters (execution is always serial)
   // - hasAliasingRegisters
   const unsigned Opcode = X86::ADD16ri;
   EXPECT_THAT(InstrInfo.get(Opcode).getImplicitDefs()[0], X86::EFLAGS);
   const auto CodeTemplates = checkAndGetCodeTemplates(Opcode);
   ASSERT_THAT(CodeTemplates, SizeIs(1));
   const auto &CT = CodeTemplates[0];
   EXPECT_THAT(CT.Execution, ExecutionMode::ALWAYS_SERIAL_TIED_REGS_ALIAS);
   ASSERT_THAT(CT.Instructions, SizeIs(1));
   const InstructionTemplate &IT = CT.Instructions[0];
   EXPECT_THAT(IT.getOpcode(), Opcode);
   ASSERT_THAT(IT.getVariableValues(), SizeIs(2));
   EXPECT_THAT(IT.getVariableValues()[0], IsInvalid()) << "Operand 1 is not set";
   EXPECT_THAT(IT.getVariableValues()[1], IsInvalid()) << "Operand 2 is not set";
 }
 
-TEST_F(SerialSnippetGeneratorTest, ImplicitSelfDependencyThroughExplicitRegs) {
+TEST_F(X86SerialSnippetGeneratorTest, ImplicitSelfDependencyThroughExplicitRegs) {
   // - VXORPSrr
   // - Op0 Explicit Def RegClass(VR128)
   // - Op1 Explicit Use RegClass(VR128)
   // - Op2 Explicit Use RegClass(VR128)
   // - Var0 [Op0]
   // - Var1 [Op1]
   // - Var2 [Op2]
   // - hasAliasingRegisters
   const unsigned Opcode = X86::VXORPSrr;
   const auto CodeTemplates = checkAndGetCodeTemplates(Opcode);
   ASSERT_THAT(CodeTemplates, SizeIs(1));
   const auto &CT = CodeTemplates[0];
   EXPECT_THAT(CT.Execution, ExecutionMode::SERIAL_VIA_EXPLICIT_REGS);
   ASSERT_THAT(CT.Instructions, SizeIs(1));
   const InstructionTemplate &IT = CT.Instructions[0];
   EXPECT_THAT(IT.getOpcode(), Opcode);
   ASSERT_THAT(IT.getVariableValues(), SizeIs(3));
   EXPECT_THAT(IT.getVariableValues(),
               AnyOf(ElementsAre(IsReg(), IsInvalid(), IsReg()),
                     ElementsAre(IsReg(), IsReg(), IsInvalid())))
       << "Op0 is either set to Op1 or to Op2";
 }
 
-TEST_F(SerialSnippetGeneratorTest,
+TEST_F(X86SerialSnippetGeneratorTest,
        ImplicitSelfDependencyThroughExplicitRegsForbidAll) {
   // - VXORPSrr
   // - Op0 Explicit Def RegClass(VR128)
   // - Op1 Explicit Use RegClass(VR128)
   // - Op2 Explicit Use RegClass(VR128)
   // - Var0 [Op0]
   // - Var1 [Op1]
   // - Var2 [Op2]
   // - hasAliasingRegisters
   const unsigned Opcode = X86::VXORPSrr;
   randomGenerator().seed(0); // Initialize seed.
   const Instruction &Instr = State.getIC().getInstr(Opcode);
   auto AllRegisters = State.getRATC().emptyRegisters();
   AllRegisters.flip();
   auto Error =
       Generator.generateCodeTemplates(&Instr, AllRegisters).takeError();
   EXPECT_TRUE((bool)Error);
   consumeError(std::move(Error));
 }
 
-TEST_F(SerialSnippetGeneratorTest, DependencyThroughOtherOpcode) {
+TEST_F(X86SerialSnippetGeneratorTest, DependencyThroughOtherOpcode) {
   // - CMP64rr
   // - Op0 Explicit Use RegClass(GR64)
   // - Op1 Explicit Use RegClass(GR64)
   // - Op2 Implicit Def Reg(EFLAGS)
   // - Var0 [Op0]
   // - Var1 [Op1]
   const unsigned Opcode = X86::CMP64rr;
   const auto CodeTemplates = checkAndGetCodeTemplates(Opcode);
   ASSERT_THAT(CodeTemplates, SizeIs(Gt(1U))) << "Many templates are available";
   for (const auto &CT : CodeTemplates) {
     EXPECT_THAT(CT.Execution, ExecutionMode::SERIAL_VIA_NON_MEMORY_INSTR);
     ASSERT_THAT(CT.Instructions, SizeIs(2));
     const InstructionTemplate &IT = CT.Instructions[0];
     EXPECT_THAT(IT.getOpcode(), Opcode);
     ASSERT_THAT(IT.getVariableValues(), SizeIs(2));
     EXPECT_THAT(IT.getVariableValues(),
                 AnyOf(ElementsAre(IsReg(), IsInvalid()),
                       ElementsAre(IsInvalid(), IsReg())));
     EXPECT_THAT(CT.Instructions[1].getOpcode(), Not(Opcode));
     // TODO: check that the two instructions alias each other.
   }
 }
 
-TEST_F(SerialSnippetGeneratorTest, LAHF) {
+TEST_F(X86SerialSnippetGeneratorTest, LAHF) {
   // - LAHF
   // - Op0 Implicit Def Reg(AH)
   // - Op1 Implicit Use Reg(EFLAGS)
   const unsigned Opcode = X86::LAHF;
   const auto CodeTemplates = checkAndGetCodeTemplates(Opcode);
   ASSERT_THAT(CodeTemplates, SizeIs(Gt(1U))) << "Many templates are available";
   for (const auto &CT : CodeTemplates) {
     EXPECT_THAT(CT.Execution, ExecutionMode::SERIAL_VIA_NON_MEMORY_INSTR);
     ASSERT_THAT(CT.Instructions, SizeIs(2));
     const InstructionTemplate &IT = CT.Instructions[0];
     EXPECT_THAT(IT.getOpcode(), Opcode);
     ASSERT_THAT(IT.getVariableValues(), SizeIs(0));
   }
 }
 
-TEST_F(SerialSnippetGeneratorTest, VCVTUSI642SDZrrb_Int) {
+TEST_F(X86SerialSnippetGeneratorTest, VCVTUSI642SDZrrb_Int) {
   // - VCVTUSI642SDZrrb_Int
   // - Op0 Explicit Def RegClass(VR128X)
   // - Op1 Explicit Use RegClass(VR128X)
   // - Op2 Explicit Use STATIC_ROUNDING
   // - Op2 Explicit Use RegClass(GR64)
   // - Op4 Implicit Use Reg(MXSCR)
   const unsigned Opcode = X86::VCVTUSI642SDZrrb_Int;
   const Instruction &Instr = State.getIC().getInstr(Opcode);
   std::vector<BenchmarkCode> Configs;
   auto Error = Generator.generateConfigurations(
       &Instr, Configs, State.getRATC().emptyRegisters());
   ASSERT_FALSE(Error);
   ASSERT_THAT(Configs, SizeIs(1));
   const BenchmarkCode &BC = Configs[0];
   ASSERT_THAT(BC.Key.Instructions, SizeIs(1));
   ASSERT_TRUE(BC.Key.Instructions[0].getOperand(3).isImm());
 }
 
-TEST_F(ParallelSnippetGeneratorTest, ParallelInstruction) {
+TEST_F(X86ParallelSnippetGeneratorTest, ParallelInstruction) {
   // - BNDCL32rr
   // - Op0 Explicit Use RegClass(BNDR)
   // - Op1 Explicit Use RegClass(GR32)
   // - Var0 [Op0]
   // - Var1 [Op1]
   const unsigned Opcode = X86::BNDCL32rr;
   const auto CodeTemplates = checkAndGetCodeTemplates(Opcode);
   ASSERT_THAT(CodeTemplates, SizeIs(1));
   const auto &CT = CodeTemplates[0];
   EXPECT_THAT(CT.Info, HasSubstr("parallel"));
   EXPECT_THAT(CT.Execution, ExecutionMode::UNKNOWN);
   ASSERT_THAT(CT.Instructions, SizeIs(1));
   const InstructionTemplate &IT = CT.Instructions[0];
   EXPECT_THAT(IT.getOpcode(), Opcode);
   ASSERT_THAT(IT.getVariableValues(), SizeIs(2));
   EXPECT_THAT(IT.getVariableValues()[0], IsInvalid());
   EXPECT_THAT(IT.getVariableValues()[1], IsInvalid());
 }
 
-TEST_F(ParallelSnippetGeneratorTest, SerialInstruction) {
+TEST_F(X86ParallelSnippetGeneratorTest, SerialInstruction) {
   // - CDQ
   // - Op0 Implicit Def Reg(EAX)
   // - Op1 Implicit Def Reg(EDX)
   // - Op2 Implicit Use Reg(EAX)
   // - hasAliasingImplicitRegisters (execution is always serial)
   // - hasAliasingRegisters
   const unsigned Opcode = X86::CDQ;
   const auto CodeTemplates = checkAndGetCodeTemplates(Opcode);
   ASSERT_THAT(CodeTemplates, SizeIs(1));
   const auto &CT = CodeTemplates[0];
   EXPECT_THAT(CT.Info, HasSubstr("serial"));
   EXPECT_THAT(CT.Execution, ExecutionMode::UNKNOWN);
   ASSERT_THAT(CT.Instructions, SizeIs(1));
   const InstructionTemplate &IT = CT.Instructions[0];
   EXPECT_THAT(IT.getOpcode(), Opcode);
   ASSERT_THAT(IT.getVariableValues(), SizeIs(0));
 }
 
-TEST_F(ParallelSnippetGeneratorTest, StaticRenaming) {
+TEST_F(X86ParallelSnippetGeneratorTest, StaticRenaming) {
   // CMOV32rr has tied variables, we enumerate the possible values to execute
   // as many in parallel as possible.
 
   // - CMOV32rr
   // - Op0 Explicit Def RegClass(GR32)
   // - Op1 Explicit Use RegClass(GR32) TiedToOp0
   // - Op2 Explicit Use RegClass(GR32)
   // - Op3 Explicit Use Immediate
TEST_F(X86ParallelSnippetGeneratorTest, StaticRenaming) {
   for (const auto &IT : CT.Instructions) {
     ASSERT_THAT(IT.getVariableValues(), SizeIs(3));
     AllDefRegisters.insert(IT.getVariableValues()[0].getReg());
   }
   EXPECT_THAT(AllDefRegisters, SizeIs(kInstructionCount))
       << "Each instruction writes to a different register";
 }
 
-TEST_F(ParallelSnippetGeneratorTest, NoTiedVariables) {
+TEST_F(X86ParallelSnippetGeneratorTest, NoTiedVariables) {
   // CMOV_GR32 has no tied variables, we make sure def and use are different
   // from each other.
 
   // - CMOV_GR32
   // - Op0 Explicit Def RegClass(GR32)
   // - Op1 Explicit Use RegClass(GR32)
   // - Op2 Explicit Use RegClass(GR32)
   // - Op3 Explicit Use Immediate
EXPECT_THAT(IT.getVariableValues()[0].getReg(),
               Not(IT.getVariableValues()[1].getReg()))
       << "Def is different from first Use";
   EXPECT_THAT(IT.getVariableValues()[0].getReg(),
               Not(IT.getVariableValues()[2].getReg()))
       << "Def is different from second Use";
   EXPECT_THAT(IT.getVariableValues()[3], IsInvalid());
 }
 
-TEST_F(ParallelSnippetGeneratorTest, MemoryUse) {
+TEST_F(X86ParallelSnippetGeneratorTest, MemoryUse) {
   // Mov32rm reads from memory.
   // - MOV32rm
   // - Op0 Explicit Def RegClass(GR32)
   // - Op1 Explicit Use Memory RegClass(GR8)
   // - Op2 Explicit Use Memory
   // - Op3 Explicit Use Memory RegClass(GRH8)
   // - Op4 Explicit Use Memory
   // - Op5 Explicit Use Memory RegClass(SEGMENT_REG)
TEST_F(X86ParallelSnippetGeneratorTest, MemoryUse) {
   EXPECT_THAT(IT.getOpcode(), Opcode);
   ASSERT_THAT(IT.getVariableValues(), SizeIs(6));
   EXPECT_EQ(IT.getVariableValues()[2].getImm(), 1);
   EXPECT_EQ(IT.getVariableValues()[3].getReg(), 0u);
   EXPECT_EQ(IT.getVariableValues()[4].getImm(), 0);
   EXPECT_EQ(IT.getVariableValues()[5].getReg(), 0u);
 }
 
-TEST_F(ParallelSnippetGeneratorTest, MOV16ms) {
+TEST_F(X86ParallelSnippetGeneratorTest, MOV16ms) {
   const unsigned Opcode = X86::MOV16ms;
   const Instruction &Instr = State.getIC().getInstr(Opcode);
   std::vector<BenchmarkCode> Benchmarks;
   auto Err = Generator.generateConfigurations(&Instr, Benchmarks,
                                               State.getRATC().emptyRegisters());
   EXPECT_TRUE((bool)Err);
   EXPECT_THAT(toString(std::move(Err)),
               testing::HasSubstr("no available registers"));
 }
 
-class FakeSnippetGenerator : public SnippetGenerator {
+class X86FakeSnippetGenerator : public SnippetGenerator {
 public:
-  FakeSnippetGenerator(const LLVMState &State, const Options &Opts)
+  X86FakeSnippetGenerator(const LLVMState &State, const Options &Opts)
       : SnippetGenerator(State, Opts) {}
 
   const Instruction &getInstr(unsigned Opcode) {
     return State.getIC().getInstr(Opcode);
   }
 
   InstructionTemplate getInstructionTemplate(unsigned Opcode) {
     return {&getInstr(Opcode)};
   }
 
 private:
   Expected<std::vector<CodeTemplate>>
   generateCodeTemplates(InstructionTemplate, const BitVector &) const override {
     return make_error<StringError>("not implemented", inconvertibleErrorCode());
   }
 };
 
-using FakeSnippetGeneratorTest = SnippetGeneratorTest<FakeSnippetGenerator>;
+using X86FakeSnippetGeneratorTest = X86SnippetGeneratorTest<X86FakeSnippetGenerator>;
 
 testing::Matcher<const RegisterValue &> IsRegisterValue(unsigned Reg,
                                                         APInt Value) {
   return testing::AllOf(testing::Field(&RegisterValue::Register, Reg),
                         testing::Field(&RegisterValue::Value, Value));
 }
 
-TEST_F(FakeSnippetGeneratorTest, MemoryUse_Movsb) {
+TEST_F(X86FakeSnippetGeneratorTest, MemoryUse_Movsb) {
   // MOVSB writes to scratch memory register.
   // - MOVSB
   // - Op0 Explicit Use Memory RegClass(GR8)
   // - Op1 Explicit Use Memory RegClass(GR8)
   // - Op2 Explicit Use Memory RegClass(SEGMENT_REG)
   // - Op3 Implicit Def Reg(EDI)
   // - Op4 Implicit Def Reg(ESI)
   // - Op5 Implicit Use Reg(EDI)
TEST_F(X86FakeSnippetGeneratorTest, MemoryUse_Movsb) {
   const Instruction &Instr = State.getIC().getInstr(Opcode);
   std::vector<BenchmarkCode> Benchmarks;
   auto Error = Generator.generateConfigurations(
       &Instr, Benchmarks, State.getRATC().emptyRegisters());
   EXPECT_TRUE((bool)Error);
   consumeError(std::move(Error));
 }
 
-TEST_F(FakeSnippetGeneratorTest, ComputeRegisterInitialValuesAdd16ri) {
+TEST_F(X86FakeSnippetGeneratorTest, ComputeRegisterInitialValuesAdd16ri) {
   // ADD16ri:
   // explicit def 0       : reg RegClass=GR16
   // explicit use 1       : reg RegClass=GR16 | TIED_TO:0
   // explicit use 2       : imm
   // implicit def         : EFLAGS
   InstructionTemplate IT = Generator.getInstructionTemplate(X86::ADD16ri);
   IT.getValueFor(IT.getInstr().Variables[0]) = MCOperand::createReg(X86::AX);
   std::vector<InstructionTemplate> Snippet;
   Snippet.push_back(std::move(IT));
   const auto RIV = Generator.computeRegisterInitialValues(Snippet);
   EXPECT_THAT(RIV, ElementsAre(IsRegisterValue(X86::AX, APInt())));
 }
 
-TEST_F(FakeSnippetGeneratorTest, ComputeRegisterInitialValuesAdd64rr) {
+TEST_F(X86FakeSnippetGeneratorTest, ComputeRegisterInitialValuesAdd64rr) {
   // ADD64rr:
   //  mov64ri rax, 42
   //  add64rr rax, rax, rbx
   // -> only rbx needs defining.
   std::vector<InstructionTemplate> Snippet;
   {
     InstructionTemplate Mov = Generator.getInstructionTemplate(X86::MOV64ri);
     Mov.getValueFor(Mov.getInstr().Variables[0]) =

llvm/unittests/tools/llvm-exegesis/X86/TargetTest.cpp

protected:
 
   const Instruction &getInstr(unsigned OpCode) {
     return State.getIC().getInstr(OpCode);
   }
 
   LLVMState State;
 };
 
-class Core2TargetTest : public X86TargetTest {
+class X86Core2TargetTest : public X86TargetTest {
 public:
-  Core2TargetTest() : X86TargetTest("") {}
+  X86Core2TargetTest() : X86TargetTest("") {}
 };
 
-class Core2AvxTargetTest : public X86TargetTest {
+class X86Core2AvxTargetTest : public X86TargetTest {
 public:
-  Core2AvxTargetTest() : X86TargetTest("+avx") {}
+  X86Core2AvxTargetTest() : X86TargetTest("+avx") {}
 };
 
-class Core2Avx512TargetTest : public X86TargetTest {
+class X86Core2Avx512TargetTest : public X86TargetTest {
 public:
-  Core2Avx512TargetTest() : X86TargetTest("+avx512vl") {}
+  X86Core2Avx512TargetTest() : X86TargetTest("+avx512vl") {}
 };
 
-TEST_F(Core2TargetTest, NoHighByteRegs) {
+TEST_F(X86Core2TargetTest, NoHighByteRegs) {
   EXPECT_TRUE(State.getRATC().reservedRegisters().test(X86::AH));
 }
 
-TEST_F(Core2TargetTest, SetFlags) {
+TEST_F(X86Core2TargetTest, SetFlags) {
   const unsigned Reg = X86::EFLAGS;
   EXPECT_THAT(setRegTo(Reg, APInt(64, 0x1111222233334444ULL)),
               ElementsAre(IsStackAllocate(8),
                           IsMovValueToStack(X86::MOV32mi, 0x33334444UL, 0),
                           IsMovValueToStack(X86::MOV32mi, 0x11112222UL, 4),
                           OpcodeIs(X86::POPF64)));
 }
 
-TEST_F(Core2TargetTest, SetRegToGR8Value) {
+TEST_F(X86Core2TargetTest, SetRegToGR8Value) {
   const uint8_t Value = 0xFFU;
   const unsigned Reg = X86::AL;
   EXPECT_THAT(setRegTo(Reg, APInt(8, Value)),
               ElementsAre(IsMovImmediate(X86::MOV8ri, Reg, Value)));
 }
 
-TEST_F(Core2TargetTest, SetRegToGR16Value) {
+TEST_F(X86Core2TargetTest, SetRegToGR16Value) {
   const uint16_t Value = 0xFFFFU;
   const unsigned Reg = X86::BX;
   EXPECT_THAT(setRegTo(Reg, APInt(16, Value)),
               ElementsAre(IsMovImmediate(X86::MOV16ri, Reg, Value)));
 }
 
-TEST_F(Core2TargetTest, SetRegToGR32Value) {
+TEST_F(X86Core2TargetTest, SetRegToGR32Value) {
   const uint32_t Value = 0x7FFFFU;
   const unsigned Reg = X86::ECX;
   EXPECT_THAT(setRegTo(Reg, APInt(32, Value)),
               ElementsAre(IsMovImmediate(X86::MOV32ri, Reg, Value)));
 }
 
-TEST_F(Core2TargetTest, SetRegToGR64Value) {
+TEST_F(X86Core2TargetTest, SetRegToGR64Value) {
   const uint64_t Value = 0x7FFFFFFFFFFFFFFFULL;
   const unsigned Reg = X86::RDX;
   EXPECT_THAT(setRegTo(Reg, APInt(64, Value)),
               ElementsAre(IsMovImmediate(X86::MOV64ri, Reg, Value)));
 }
 
-TEST_F(Core2TargetTest, SetRegToVR64Value) {
+TEST_F(X86Core2TargetTest, SetRegToVR64Value) {
   EXPECT_THAT(setRegTo(X86::MM0, APInt(64, 0x1111222233334444ULL)),
               ElementsAre(IsStackAllocate(8),
                           IsMovValueToStack(X86::MOV32mi, 0x33334444UL, 0),
                           IsMovValueToStack(X86::MOV32mi, 0x11112222UL, 4),
                           IsMovValueFromStack(X86::MMX_MOVQ64rm, X86::MM0),
                           IsStackDeallocate(8)));
 }
 
-TEST_F(Core2TargetTest, SetRegToVR128Value_Use_MOVDQUrm) {
+TEST_F(X86Core2TargetTest, SetRegToVR128Value_Use_MOVDQUrm) {
   EXPECT_THAT(
       setRegTo(X86::XMM0, APInt(128, "11112222333344445555666677778888", 16)),
       ElementsAre(IsStackAllocate(16),
                   IsMovValueToStack(X86::MOV32mi, 0x77778888UL, 0),
                   IsMovValueToStack(X86::MOV32mi, 0x55556666UL, 4),
                   IsMovValueToStack(X86::MOV32mi, 0x33334444UL, 8),
                   IsMovValueToStack(X86::MOV32mi, 0x11112222UL, 12),
                   IsMovValueFromStack(X86::MOVDQUrm, X86::XMM0),
                   IsStackDeallocate(16)));
 }
 
-TEST_F(Core2AvxTargetTest, SetRegToVR128Value_Use_VMOVDQUrm) {
+TEST_F(X86Core2AvxTargetTest, SetRegToVR128Value_Use_VMOVDQUrm) {
   EXPECT_THAT(
       setRegTo(X86::XMM0, APInt(128, "11112222333344445555666677778888", 16)),
       ElementsAre(IsStackAllocate(16),
                   IsMovValueToStack(X86::MOV32mi, 0x77778888UL, 0),
                   IsMovValueToStack(X86::MOV32mi, 0x55556666UL, 4),
                   IsMovValueToStack(X86::MOV32mi, 0x33334444UL, 8),
                   IsMovValueToStack(X86::MOV32mi, 0x11112222UL, 12),
                   IsMovValueFromStack(X86::VMOVDQUrm, X86::XMM0),
                   IsStackDeallocate(16)));
 }
 
-TEST_F(Core2Avx512TargetTest, SetRegToVR128Value_Use_VMOVDQU32Z128rm) {
+TEST_F(X86Core2Avx512TargetTest, SetRegToVR128Value_Use_VMOVDQU32Z128rm) {
   EXPECT_THAT(
       setRegTo(X86::XMM0, APInt(128, "11112222333344445555666677778888", 16)),
       ElementsAre(IsStackAllocate(16),
                   IsMovValueToStack(X86::MOV32mi, 0x77778888UL, 0),
                   IsMovValueToStack(X86::MOV32mi, 0x55556666UL, 4),
                   IsMovValueToStack(X86::MOV32mi, 0x33334444UL, 8),
                   IsMovValueToStack(X86::MOV32mi, 0x11112222UL, 12),
                   IsMovValueFromStack(X86::VMOVDQU32Z128rm, X86::XMM0),
                   IsStackDeallocate(16)));
 }
 
-TEST_F(Core2AvxTargetTest, SetRegToVR256Value_Use_VMOVDQUYrm) {
+TEST_F(X86Core2AvxTargetTest, SetRegToVR256Value_Use_VMOVDQUYrm) {
   const char ValueStr[] =
       "1111111122222222333333334444444455555555666666667777777788888888";
   EXPECT_THAT(
       setRegTo(X86::YMM0, APInt(256, ValueStr, 16)),
       ElementsAreArray({IsStackAllocate(32),
                         IsMovValueToStack(X86::MOV32mi, 0x88888888UL, 0),
                         IsMovValueToStack(X86::MOV32mi, 0x77777777UL, 4),
                         IsMovValueToStack(X86::MOV32mi, 0x66666666UL, 8),
                         IsMovValueToStack(X86::MOV32mi, 0x55555555UL, 12),
                         IsMovValueToStack(X86::MOV32mi, 0x44444444UL, 16),
                         IsMovValueToStack(X86::MOV32mi, 0x33333333UL, 20),
                         IsMovValueToStack(X86::MOV32mi, 0x22222222UL, 24),
                         IsMovValueToStack(X86::MOV32mi, 0x11111111UL, 28),
                         IsMovValueFromStack(X86::VMOVDQUYrm, X86::YMM0),
                         IsStackDeallocate(32)}));
 }
 
-TEST_F(Core2Avx512TargetTest, SetRegToVR256Value_Use_VMOVDQU32Z256rm) {
+TEST_F(X86Core2Avx512TargetTest, SetRegToVR256Value_Use_VMOVDQU32Z256rm) {
   const char ValueStr[] =
       "1111111122222222333333334444444455555555666666667777777788888888";
   EXPECT_THAT(
       setRegTo(X86::YMM0, APInt(256, ValueStr, 16)),
       ElementsAreArray({IsStackAllocate(32),
                         IsMovValueToStack(X86::MOV32mi, 0x88888888UL, 0),
                         IsMovValueToStack(X86::MOV32mi, 0x77777777UL, 4),
                         IsMovValueToStack(X86::MOV32mi, 0x66666666UL, 8),
                         IsMovValueToStack(X86::MOV32mi, 0x55555555UL, 12),
                         IsMovValueToStack(X86::MOV32mi, 0x44444444UL, 16),
                         IsMovValueToStack(X86::MOV32mi, 0x33333333UL, 20),
                         IsMovValueToStack(X86::MOV32mi, 0x22222222UL, 24),
                         IsMovValueToStack(X86::MOV32mi, 0x11111111UL, 28),
                         IsMovValueFromStack(X86::VMOVDQU32Z256rm, X86::YMM0),
                         IsStackDeallocate(32)}));
 }
 
-TEST_F(Core2Avx512TargetTest, SetRegToVR512Value) {
+TEST_F(X86Core2Avx512TargetTest, SetRegToVR512Value) {
   const char ValueStr[] =
       "1111111122222222333333334444444455555555666666667777777788888888"
       "99999999AAAAAAAABBBBBBBBCCCCCCCCDDDDDDDDEEEEEEEEFFFFFFFF00000000";
   EXPECT_THAT(
       setRegTo(X86::ZMM0, APInt(512, ValueStr, 16)),
       ElementsAreArray({IsStackAllocate(64),
                         IsMovValueToStack(X86::MOV32mi, 0x00000000UL, 0),
                         IsMovValueToStack(X86::MOV32mi, 0xFFFFFFFFUL, 4),
EXPECT_THAT(
                         IsMovValueToStack(X86::MOV32mi, 0x11111111UL, 60),
                         IsMovValueFromStack(X86::VMOVDQU32Zrm, X86::ZMM0),
                         IsStackDeallocate(64)}));
 }
 
 // Note: We always put 80 bits on the stack independently of the size of the
 // value. This uses a bit more space but makes the code simpler.
 
-TEST_F(Core2TargetTest, SetRegToST0_32Bits) {
+TEST_F(X86Core2TargetTest, SetRegToST0_32Bits) {
   EXPECT_THAT(setRegTo(X86::ST0, APInt(32, 0x11112222ULL)),
               ElementsAre(IsStackAllocate(10),
                           IsMovValueToStack(X86::MOV32mi, 0x11112222UL, 0),
                           IsMovValueToStack(X86::MOV32mi, 0x00000000UL, 4),
                           IsMovValueToStack(X86::MOV16mi, 0x0000UL, 8),
                           OpcodeIs(X86::LD_F80m), IsStackDeallocate(10)));
 }
 
-TEST_F(Core2TargetTest, SetRegToST1_32Bits) {
+TEST_F(X86Core2TargetTest, SetRegToST1_32Bits) {
   const MCInst CopySt0ToSt1 = MCInstBuilder(X86::ST_Frr).addReg(X86::ST1);
   EXPECT_THAT(setRegTo(X86::ST1, APInt(32, 0x11112222ULL)),
               ElementsAre(IsStackAllocate(10),
                           IsMovValueToStack(X86::MOV32mi, 0x11112222UL, 0),
                           IsMovValueToStack(X86::MOV32mi, 0x00000000UL, 4),
                           IsMovValueToStack(X86::MOV16mi, 0x0000UL, 8),
                           OpcodeIs(X86::LD_F80m), CopySt0ToSt1,
                           IsStackDeallocate(10)));
 }
 
-TEST_F(Core2TargetTest, SetRegToST0_64Bits) {
+TEST_F(X86Core2TargetTest, SetRegToST0_64Bits) {
   EXPECT_THAT(setRegTo(X86::ST0, APInt(64, 0x1111222233334444ULL)),
               ElementsAre(IsStackAllocate(10),
                           IsMovValueToStack(X86::MOV32mi, 0x33334444UL, 0),
                           IsMovValueToStack(X86::MOV32mi, 0x11112222UL, 4),
                           IsMovValueToStack(X86::MOV16mi, 0x0000UL, 8),
                           OpcodeIs(X86::LD_F80m), IsStackDeallocate(10)));
 }
 
-TEST_F(Core2TargetTest, SetRegToST0_80Bits) {
+TEST_F(X86Core2TargetTest, SetRegToST0_80Bits) {
   EXPECT_THAT(setRegTo(X86::ST0, APInt(80, "11112222333344445555", 16)),
               ElementsAre(IsStackAllocate(10),
                           IsMovValueToStack(X86::MOV32mi, 0x44445555UL, 0),
                           IsMovValueToStack(X86::MOV32mi, 0x22223333UL, 4),
                           IsMovValueToStack(X86::MOV16mi, 0x1111UL, 8),
                           OpcodeIs(X86::LD_F80m), IsStackDeallocate(10)));
 }
 
-TEST_F(Core2TargetTest, SetRegToFP0_80Bits) {
+TEST_F(X86Core2TargetTest, SetRegToFP0_80Bits) {
   EXPECT_THAT(setRegTo(X86::FP0, APInt(80, "11112222333344445555", 16)),
               ElementsAre(IsStackAllocate(10),
                           IsMovValueToStack(X86::MOV32mi, 0x44445555UL, 0),
                           IsMovValueToStack(X86::MOV32mi, 0x22223333UL, 4),
                           IsMovValueToStack(X86::MOV16mi, 0x1111UL, 8),
                           OpcodeIs(X86::LD_Fp80m), IsStackDeallocate(10)));
 }
 
-TEST_F(Core2TargetTest, SetRegToFP1_32Bits) {
+TEST_F(X86Core2TargetTest, SetRegToFP1_32Bits) {
   EXPECT_THAT(setRegTo(X86::FP1, APInt(32, 0x11112222ULL)),
               ElementsAre(IsStackAllocate(10),
                           IsMovValueToStack(X86::MOV32mi, 0x11112222UL, 0),
                           IsMovValueToStack(X86::MOV32mi, 0x00000000UL, 4),
                           IsMovValueToStack(X86::MOV16mi, 0x0000UL, 8),
                           OpcodeIs(X86::LD_Fp80m), IsStackDeallocate(10)));
 }
 
-TEST_F(Core2TargetTest, SetRegToFP1_4Bits) {
+TEST_F(X86Core2TargetTest, SetRegToFP1_4Bits) {
   EXPECT_THAT(setRegTo(X86::FP1, APInt(4, 0x1ULL)),
               ElementsAre(IsStackAllocate(10),
                           IsMovValueToStack(X86::MOV32mi, 0x00000001UL, 0),
                           IsMovValueToStack(X86::MOV32mi, 0x00000000UL, 4),
                           IsMovValueToStack(X86::MOV16mi, 0x0000UL, 8),
                           OpcodeIs(X86::LD_Fp80m), IsStackDeallocate(10)));
 }
 
-TEST_F(Core2Avx512TargetTest, FillMemoryOperands_ADD64rm) {
+TEST_F(X86Core2Avx512TargetTest, FillMemoryOperands_ADD64rm) {
   const Instruction &I = getInstr(X86::ADD64rm);
   InstructionTemplate IT(&I);
   constexpr const int kOffset = 42;
   State.getExegesisTarget().fillMemoryOperands(IT, X86::RDI, kOffset);
   // Memory is operands 2-6.
   EXPECT_THAT(IT.getValueFor(I.Operands[2]), IsReg(X86::RDI));
   EXPECT_THAT(IT.getValueFor(I.Operands[3]), IsImm(1));
   EXPECT_THAT(IT.getValueFor(I.Operands[4]), IsReg(0));
   EXPECT_THAT(IT.getValueFor(I.Operands[5]), IsImm(kOffset));
   EXPECT_THAT(IT.getValueFor(I.Operands[6]), IsReg(0));
 }
 
-TEST_F(Core2Avx512TargetTest, FillMemoryOperands_VGATHERDPSZ128rm) {
+TEST_F(X86Core2Avx512TargetTest, FillMemoryOperands_VGATHERDPSZ128rm) {
   const Instruction &I = getInstr(X86::VGATHERDPSZ128rm);
   InstructionTemplate IT(&I);
   constexpr const int kOffset = 42;
   State.getExegesisTarget().fillMemoryOperands(IT, X86::RDI, kOffset);
   // Memory is operands 4-8.
   EXPECT_THAT(IT.getValueFor(I.Operands[4]), IsReg(X86::RDI));
   EXPECT_THAT(IT.getValueFor(I.Operands[5]), IsImm(1));
   EXPECT_THAT(IT.getValueFor(I.Operands[6]), IsReg(0));
   EXPECT_THAT(IT.getValueFor(I.Operands[7]), IsImm(kOffset));
   EXPECT_THAT(IT.getValueFor(I.Operands[8]), IsReg(0));
 }
 
-TEST_F(Core2TargetTest, AllowAsBackToBack) {
+TEST_F(X86Core2TargetTest, AllowAsBackToBack) {
   EXPECT_TRUE(
       State.getExegesisTarget().allowAsBackToBack(getInstr(X86::ADD64rr)));
   EXPECT_FALSE(
       State.getExegesisTarget().allowAsBackToBack(getInstr(X86::LEA64r)));
 }
 
 } // namespace
 } // namespace exegesis
 } // namespace llvm