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[X86] Enable half type support in inline assembly constraints
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Authored by pengfei on Jul 12 2021, 1:35 AM.

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pengfei created this revision.Jul 12 2021, 1:35 AM
pengfei requested review of this revision.Jul 12 2021, 1:35 AM
Herald added a project: Restricted Project. · View Herald TranscriptJul 12 2021, 1:35 AM
LuoYuanke added inline comments.Jul 12 2021, 6:19 AM
llvm/test/CodeGen/X86/inline-asm-avx512f-x-constraint.ll
22

Add more vector types (half, <8 x half>) to improve the coverage?

pengfei updated this revision to Diff 369629.Mon, Aug 30, 10:49 PM

Rebased.

llvm/test/CodeGen/X86/inline-asm-avx512f-x-constraint.ll
22

There will be many tests to meet the coverage, since we have the matrix {'v', 'x', 'Yz', ...} * 128/256/512. I checked we don't fully tested double either, I guess there might be no much value to do so since no difference among different FP types in SSE register classes.

LuoYuanke added inline comments.Tue, Aug 31, 12:43 AM
llvm/test/CodeGen/X86/inline-asm-avx512f-x-constraint.ll
24

Maybe use a meaningful instruction, .e.g vaddph.

pengfei updated this revision to Diff 369644.Tue, Aug 31, 12:51 AM
pengfei marked an inline comment as done.

Address Yuanke's comments.

Thanks Yuanke.

LuoYuanke accepted this revision.Tue, Aug 31, 12:58 AM

LGTM, thanks!

This revision is now accepted and ready to land.Tue, Aug 31, 12:58 AM