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Differential D105626

[RISCV][Clang] Add macro __riscv_zvlsseg for RVV Zvlsseg builtins
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Authored by jacquesguan on Jul 8 2021, 6:00 AM.

Details

Reviewers
craig.topper
HsiangKai
Commits
rG88326bbce38c: [RISCV][clang] Add macro __riscv_zvlsseg for RVV Zvlsseg builtins
Summary

Add extension macro __riscv_zvlsseg to enable Zvlsseg builtins only with target feature Zvlsseg.

Diff Detail

Event Timeline

jacquesguan created this revision.Jul 8 2021, 6:00 AM
Herald added subscribers: vkmr, frasercrmck, evandro and 24 others. · View Herald TranscriptJul 8 2021, 6:00 AM
jacquesguan requested review of this revision.Jul 8 2021, 6:00 AM
Herald added a project: Restricted Project. · View Herald TranscriptJul 8 2021, 6:00 AM
Herald added subscribers: cfe-commits, MaskRay. · View Herald Transcript
jacquesguan added a reviewer: HsiangKai.Jul 8 2021, 6:02 AM
Harbormaster completed remote builds in B112970: Diff 357201.Jul 8 2021, 6:48 AM
HsiangKai accepted this revision.Jul 8 2021, 7:55 AM

Thanks. LGTM.

This revision is now accepted and ready to land.Jul 8 2021, 7:55 AM
jacquesguan updated this revision to Diff 357408.Jul 8 2021, 8:20 PM

Add target feature zvlsseg for rvv-intrinsics/vlsegff.c

Harbormaster completed remote builds in B113128: Diff 357408.Jul 8 2021, 9:05 PM
Closed by commit rG88326bbce38c: [RISCV][clang] Add macro __riscv_zvlsseg for RVV Zvlsseg builtins (authored by jacquesguan, committed by benshi001). · Explain WhyJul 8 2021, 10:19 PM
This revision was automatically updated to reflect the committed changes.
benshi001 added a commit: rG88326bbce38c: [RISCV][clang] Add macro __riscv_zvlsseg for RVV Zvlsseg builtins.

Revision Contents

PathSize
clang/
test/
CodeGen/
RISCV/
rvv-intrinsics-overloaded/
10 lines
10 lines
rvv-intrinsics/
10 lines
10 lines
utils/
TableGen/
5 lines

Diff 357417

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlseg.c

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// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// REQUIRES: riscv-registered-target // REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +f -target-feature +d \ // RUN: %clang_cc1 -triple riscv32 -target-feature +f -target-feature +d \
// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \ // RUN: -target-feature +experimental-v -target-feature +experimental-zfh \
// RUN: -disable-O0-optnone -fallow-half-arguments-and-returns -emit-llvm %s \ // RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone \
// RUN: -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: -fallow-half-arguments-and-returns -emit-llvm %s -o - \
// RUN: | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \ // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \ // RUN: -target-feature +experimental-v -target-feature +experimental-zfh \
// RUN: -disable-O0-optnone -fallow-half-arguments-and-returns -emit-llvm %s \ // RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone \
// RUN: -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s // RUN: -fallow-half-arguments-and-returns -emit-llvm %s -o - \
// RUN: | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
#include <riscv_vector.h> #include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vlseg2e8_v_i8mf8_m( // CHECK-RV32-LABEL: @test_vlseg2e8_v_i8mf8_m(
// CHECK-RV32-NEXT: entry: // CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { <vscale x 1 x i8>, <vscale x 1 x i8> } @llvm.riscv.vlseg2.mask.nxv1i8.i32(<vscale x 1 x i8> [[MASKEDOFF0:%.*]], <vscale x 1 x i8> [[MASKEDOFF1:%.*]], i8* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP0:%.*]] = call { <vscale x 1 x i8>, <vscale x 1 x i8> } @llvm.riscv.vlseg2.mask.nxv1i8.i32(<vscale x 1 x i8> [[MASKEDOFF0:%.*]], <vscale x 1 x i8> [[MASKEDOFF1:%.*]], i8* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP0]], 0 // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP0]], 0
// CHECK-RV32-NEXT: store <vscale x 1 x i8> [[TMP1]], <vscale x 1 x i8>* [[V0:%.*]], align 4 // CHECK-RV32-NEXT: store <vscale x 1 x i8> [[TMP1]], <vscale x 1 x i8>* [[V0:%.*]], align 4
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clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlsegff.c

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// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// REQUIRES: riscv-registered-target // REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +f -target-feature +d \ // RUN: %clang_cc1 -triple riscv32 -target-feature +f -target-feature +d \
// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \ // RUN: -target-feature +experimental-v -target-feature +experimental-zfh \
// RUN: -disable-O0-optnone -fallow-half-arguments-and-returns -emit-llvm %s \ // RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone \
// RUN: -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: -fallow-half-arguments-and-returns -emit-llvm %s -o - \
// RUN: | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \ // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \ // RUN: -target-feature +experimental-v -target-feature +experimental-zfh \
// RUN: -disable-O0-optnone -fallow-half-arguments-and-returns -emit-llvm %s \ // RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone \
// RUN: -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s // RUN: -fallow-half-arguments-and-returns -emit-llvm %s -o - \
// RUN: | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
#include <riscv_vector.h> #include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vlseg2e8ff_v_i8mf8_m( // CHECK-RV32-LABEL: @test_vlseg2e8ff_v_i8mf8_m(
// CHECK-RV32-NEXT: entry: // CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { <vscale x 1 x i8>, <vscale x 1 x i8>, i32 } @llvm.riscv.vlseg2ff.mask.nxv1i8.i32(<vscale x 1 x i8> [[MASKEDOFF0:%.*]], <vscale x 1 x i8> [[MASKEDOFF1:%.*]], i8* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP0:%.*]] = call { <vscale x 1 x i8>, <vscale x 1 x i8>, i32 } @llvm.riscv.vlseg2ff.mask.nxv1i8.i32(<vscale x 1 x i8> [[MASKEDOFF0:%.*]], <vscale x 1 x i8> [[MASKEDOFF1:%.*]], i8* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, i32 } [[TMP0]], 0
// CHECK-RV32-NEXT: store <vscale x 1 x i8> [[TMP1]], <vscale x 1 x i8>* [[V0:%.*]], align 4 // CHECK-RV32-NEXT: store <vscale x 1 x i8> [[TMP1]], <vscale x 1 x i8>* [[V0:%.*]], align 4
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clang/test/CodeGen/RISCV/rvv-intrinsics/vlseg.c

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// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// REQUIRES: riscv-registered-target // REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +f -target-feature +d \ // RUN: %clang_cc1 -triple riscv32 -target-feature +f -target-feature +d \
// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \ // RUN: -target-feature +experimental-v -target-feature +experimental-zfh \
// RUN: -disable-O0-optnone -fallow-half-arguments-and-returns -emit-llvm %s \ // RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone \
// RUN: -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: -fallow-half-arguments-and-returns -emit-llvm %s -o - \
// RUN: | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \ // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \ // RUN: -target-feature +experimental-v -target-feature +experimental-zfh \
// RUN: -disable-O0-optnone -fallow-half-arguments-and-returns -emit-llvm %s \ // RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone \
// RUN: -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s // RUN: -fallow-half-arguments-and-returns -emit-llvm %s -o - \
// RUN: | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
#include <riscv_vector.h> #include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vlseg2e8_v_i8mf8( // CHECK-RV32-LABEL: @test_vlseg2e8_v_i8mf8(
// CHECK-RV32-NEXT: entry: // CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { <vscale x 1 x i8>, <vscale x 1 x i8> } @llvm.riscv.vlseg2.nxv1i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP0:%.*]] = call { <vscale x 1 x i8>, <vscale x 1 x i8> } @llvm.riscv.vlseg2.nxv1i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP0]], 0 // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP0]], 0
// CHECK-RV32-NEXT: store <vscale x 1 x i8> [[TMP1]], <vscale x 1 x i8>* [[V0:%.*]], align 4 // CHECK-RV32-NEXT: store <vscale x 1 x i8> [[TMP1]], <vscale x 1 x i8>* [[V0:%.*]], align 4
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clang/test/CodeGen/RISCV/rvv-intrinsics/vlsegff.c

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// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// REQUIRES: riscv-registered-target // REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +f -target-feature +d \ // RUN: %clang_cc1 -triple riscv32 -target-feature +f -target-feature +d \
// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \ // RUN: -target-feature +experimental-v -target-feature +experimental-zfh \
// RUN: -disable-O0-optnone -fallow-half-arguments-and-returns -emit-llvm %s \ // RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone \
// RUN: -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: -fallow-half-arguments-and-returns -emit-llvm %s -o - \
// RUN: | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \ // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \ // RUN: -target-feature +experimental-v -target-feature +experimental-zfh \
// RUN: -disable-O0-optnone -fallow-half-arguments-and-returns -emit-llvm %s \ // RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone \
// RUN: -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s // RUN: -fallow-half-arguments-and-returns -emit-llvm %s -o - \
// RUN: | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
#include <riscv_vector.h> #include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vlseg2e8ff_v_i8mf8( // CHECK-RV32-LABEL: @test_vlseg2e8ff_v_i8mf8(
// CHECK-RV32-NEXT: entry: // CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { <vscale x 1 x i8>, <vscale x 1 x i8>, i32 } @llvm.riscv.vlseg2ff.nxv1i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP0:%.*]] = call { <vscale x 1 x i8>, <vscale x 1 x i8>, i32 } @llvm.riscv.vlseg2ff.nxv1i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, i32 } [[TMP0]], 0
// CHECK-RV32-NEXT: store <vscale x 1 x i8> [[TMP1]], <vscale x 1 x i8>* [[V0:%.*]], align 4 // CHECK-RV32-NEXT: store <vscale x 1 x i8> [[TMP1]], <vscale x 1 x i8>* [[V0:%.*]], align 4
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clang/utils/TableGen/RISCVVEmitter.cpp

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using RVVTypes = std::vector<RVVTypePtr>; using RVVTypes = std::vector<RVVTypePtr>;
enum RISCVExtension : uint8_t { enum RISCVExtension : uint8_t {
Basic = 0, Basic = 0,
F = 1 << 1, F = 1 << 1,
D = 1 << 2, D = 1 << 2,
Zfh = 1 << 3, Zfh = 1 << 3,
Zvamo = 1 << 4, Zvamo = 1 << 4,
Zvlsseg = 1 << 5,
}; };
// TODO refactor RVVIntrinsic class design after support all intrinsic // TODO refactor RVVIntrinsic class design after support all intrinsic
// combination. This represents an instantiation of an intrinsic with a // combination. This represents an instantiation of an intrinsic with a
// particular type and prototype // particular type and prototype
class RVVIntrinsic { class RVVIntrinsic {
private: private:
▲ Show 20 Lines • Show All 627 Lines • ▼ Show 20 Lines if (T->isFloatVector(16) || T->isFloat(16))
RISCVExtensions |= RISCVExtension::Zfh; RISCVExtensions |= RISCVExtension::Zfh;
else if (T->isFloatVector(32) || T->isFloat(32)) else if (T->isFloatVector(32) || T->isFloat(32))
RISCVExtensions |= RISCVExtension::F; RISCVExtensions |= RISCVExtension::F;
else if (T->isFloatVector(64) || T->isFloat(64)) else if (T->isFloatVector(64) || T->isFloat(64))
RISCVExtensions |= RISCVExtension::D; RISCVExtensions |= RISCVExtension::D;
} }
if (RequiredExtension == "Zvamo") if (RequiredExtension == "Zvamo")
RISCVExtensions |= RISCVExtension::Zvamo; RISCVExtensions |= RISCVExtension::Zvamo;
if (RequiredExtension == "Zvlsseg")
RISCVExtensions |= RISCVExtension::Zvlsseg;
// Init OutputType and InputTypes // Init OutputType and InputTypes
OutputType = OutInTypes[0]; OutputType = OutInTypes[0];
InputTypes.assign(OutInTypes.begin() + 1, OutInTypes.end()); InputTypes.assign(OutInTypes.begin() + 1, OutInTypes.end());
// IntrinsicTypes is nonmasked version index. Need to update it // IntrinsicTypes is nonmasked version index. Need to update it
// if there is maskedoff operand (It is always in first operand). // if there is maskedoff operand (It is always in first operand).
IntrinsicTypes = NewIntrinsicTypes; IntrinsicTypes = NewIntrinsicTypes;
▲ Show 20 Lines • Show All 437 Lines • ▼ Show 20 Linesbool RVVEmitter::emitExtDefStr(uint8_t Extents, raw_ostream &OS) {
if (Extents & RISCVExtension::F) if (Extents & RISCVExtension::F)
OS << LS << "defined(__riscv_f)"; OS << LS << "defined(__riscv_f)";
if (Extents & RISCVExtension::D) if (Extents & RISCVExtension::D)
OS << LS << "defined(__riscv_d)"; OS << LS << "defined(__riscv_d)";
if (Extents & RISCVExtension::Zfh) if (Extents & RISCVExtension::Zfh)
OS << LS << "defined(__riscv_zfh)"; OS << LS << "defined(__riscv_zfh)";
if (Extents & RISCVExtension::Zvamo) if (Extents & RISCVExtension::Zvamo)
OS << LS << "defined(__riscv_zvamo)"; OS << LS << "defined(__riscv_zvamo)";
if (Extents & RISCVExtension::Zvlsseg)
OS << LS << "defined(__riscv_zvlsseg)";
OS << "\n"; OS << "\n";
return true; return true;
} }
namespace clang { namespace clang {
void EmitRVVHeader(RecordKeeper &Records, raw_ostream &OS) { void EmitRVVHeader(RecordKeeper &Records, raw_ostream &OS) {
RVVEmitter(Records).createHeader(OS); RVVEmitter(Records).createHeader(OS);
} }
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