[AMDGPU] PHI node cost should not be counted for the size and latency.

[alex-t]

Summary

Details: https://reviews.llvm.org/D96805 changed the GCNTTIImpl::getCFInstrCost to return 1 for the PHI nodes
for the TTI::TCK_CodeSize and TTI::TCK_SizeAndLatency. This is incorrect because the value moves that are the
result of the PHI lowering are inserted into the basic block predecessors - not into the block itself.
As a result of this change LoopRotate and LoopUnroll were broken because of the incorrect Loop header and loop
body size/cost estimation.

[dfukalov]

llvm/test/Analysis/CostModel/AMDGPU/control-flow.ll

8

Please update the sizes reported after your change instead of just removing the test lines here and below.

[alex-t]

Test corrected

[dfukalov]

llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp

841

Nit: leave this or similar related todo comments somewhere, it wasn't done.

[alex-t]

llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp

841

Such a prediction is unlikely possible. The number of copies that survived after the register coalescing too much dependent on the passes that run in between.

[alex-t]

:

llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp

InstructionCost GCNTTIImpl::getCFInstrCost(unsigned Opcode,
   case Instruction::Switch: {
     auto SI = dyn_cast_or_null<SwitchInst>(I);
     // Each case (including default) takes 1 cmp + 1 cbr instructions in
     // average.
     return (SI ? (SI->getNumCases() + 1) : 4) * (CBrCost + 1);
   }
   case Instruction::Ret:
     return SCost ? 1 : 10;
-  case Instruction::PHI:
-    // TODO: 1. A prediction phi won't be eliminated?
-    //       2. Estimate data copy instructions in this case.
-    return 1;
   }
   return BaseT::getCFInstrCost(Opcode, CostKind, I);
 }
 
 InstructionCost
 GCNTTIImpl::getArithmeticReductionCost(unsigned Opcode, VectorType *Ty,
                                        bool IsPairwise,
                                        TTI::TargetCostKind CostKind) {

llvm/test/Analysis/CostModel/AMDGPU/control-flow.ll

 ; RUN: opt -cost-model -analyze -mtriple=amdgcn-unknown-amdhsa < %s | FileCheck  --check-prefixes=ALL,SPEED %s
 ; RUN: opt -cost-model -cost-kind=code-size -analyze -mtriple=amdgcn-unknown-amdhsa < %s | FileCheck --check-prefixes=ALL,SIZE %s
 
 ; ALL-LABEL: 'test_br_cost'
 ; SPEED: estimated cost of 7 for instruction: br i1
 ; SPEED: estimated cost of 4 for instruction: br label
 ; SPEED: estimated cost of 1 for instruction: %phi = phi i32 [
 ; SPEED: estimated cost of 10 for instruction: ret void
 ; SIZE: estimated cost of 5 for instruction: br i1
 ; SIZE: estimated cost of 1 for instruction: br label
-; SIZE: estimated cost of 1 for instruction: %phi = phi i32 [
+; SIZE: estimated cost of 0 for instruction: %phi = phi i32 [
 ; SIZE: estimated cost of 1 for instruction: ret void
 define amdgpu_kernel void @test_br_cost(i32 addrspace(1)* %out, i32 addrspace(1)* %vaddr, i32 %b) #0 {
 bb0:
   br i1 undef, label %bb1, label %bb2
 
 bb1:
   %vec = load i32, i32 addrspace(1)* %vaddr
   %add = add i32 %vec, %b