[Mem2Reg] Use poison instead of undef for read of uninitialized memory

[nikic]

Summary

During mem2reg, make loads from uninitialized memory return a poison value rather than an undef value. Also clarify the alloca documentation in this regard.

[aqjune]

This is a big change because AFAIK clang intentionally encodes the value of uninitialized variables in a benign way.
For example: https://godbolt.org/z/EYjasxM1M is optimized to 0 even if it is undef ^ undef = undef. If poison is used, this won't work.
I think that to switch to poison reasonable performance benefit should be shown. I have a patch that makes poison propagate better, which will help this change.
BTW, do you have any idea about the failures happening at clang unit tests?

[nlopes]

I really look forward to the day that we can commit this patch! 😀 That's the goal, to get rid of undef.

However, there's still one issue we need to solve first: bit-fields. The lowering of bitfield stores in clang is something like:

v = load word
v' = mask v + combine with bitfield value to be stored
store v'

On the first bit-field store the memory is uninitialized but it is still combined with the value to be stored. If we change uninitialized memory to be poison, as this patch does, clang's lowering becomes wrong.
Two fixes are possible:

1. For bitfields on the stack, initialize the value to zero [possible optimization?]
2. For other bitfields, freeze the value after loading. This is sufficient to tame the initial poison from uninitialized memory. Subsequent loads don't need freeze (if clang can prove they touch a bitfield that has been initialized before) as even if some value becomes poison it's not problematic. In C/C++ if a value becomes poison then the program has already executed UB, so we can taint the whole word without a problem.

TL;DR: we need to add a freeze after load in clang's bitfield lowering before this patch can go in. @nikic do you have bandwidth for this work?
After that, I'm all for it! But we should probably send an email to the ML so that folks working on other frontends notice the IR semantics change.

[efriedma]

In D104648#2831212, @aqjune wrote:

This is a big change because AFAIK clang intentionally encodes the value of uninitialized variables in a benign way.
For example: https://godbolt.org/z/EYjasxM1M is optimized to 0 even if it is undef ^ undef = undef. If poison is used, this won't work.

I'm not sure what you're getting at here. This isn't a difference between undef and poison. It's perfectly legal to fold "poison ^ poison -> 0". And we probably should, just to avoid the hassle involved in diagnosing the issues that would result from changing this fold.

[nikic]

@aqjune I don't think performance is really relevant here: It's a necessary step to remove undef in the future. I think this is one of the main ways left in which we introduce undef in IR.

@nlopes Ugh, this is ugly. The fact that clang is using this also means that we can't just ignore bitcode autoupgrade. Adding a freeze on every load seems like a really big hammer, but I'm not sure what else could be done.

[nlopes]

@nlopes Ugh, this is ugly. The fact that clang is using this also means that we can't just ignore bitcode autoupgrade. Adding a freeze on every load seems like a really big hammer, but I'm not sure what else could be done.

It would be just loads for bitfields. They are not common, so I guess it's ok.

There are technically better solutions, but require more functionality in the IR. But I don't think it's worth it for such an uncommon feature.
A better solution come to mind:
Introduce "really packed" structs, where we push all the ABI work to the frontend. LLVM's packed structs still go through the ABI code and may get extra padding, while we would need something that bypasses the padding so we could encode bitfields precisely.
This solution doesn't require any freezing, but it's more complicated: requires additional IR features, backend work, etc. So the load+freeze for bitfields sounds better to me.

[aqjune]

Or, can we temporarily mark an alloca with !has_bitfield if it had bitfields in C & make mem2reg use poison only when uninitialized memory is read, for a while?

[nlopes]

In D104648#2836258, @aqjune wrote:

Or, can we temporarily mark an alloca with !has_bitfield if it had bitfields in C & make mem2reg use poison only when uninitialized memory is read, for a while?

Well, that doesn't help much. It's just a band-aid..
I would rather initialize all alloca'd bitfields with zero instead. Zero folds trivially with the bit-masking operations from bit-fields, so it's unlikely to disrupt anything.

[nikic]

Removing this from the review queue -- this change by itself is clearly not sufficient.

llvm/docs/LangRef.rst

 boundary compatible with the type.
 
 '``type``' may be any sized type.
 
 Semantics:
 """"""""""
 
 Memory is allocated; a pointer is returned. The allocated memory is
-uninitialized, and loading from uninitialized memory produces an undefined
-value. The operation itself is undefined if there is insufficient stack
-space for the allocation.'``alloca``'d memory is automatically released
+uninitialized, and loading from uninitialized memory produces a :ref:`poison
+value <poisonvalue>`. The operation itself is undefined if there is insufficient
+stack space for the allocation.'``alloca``'d memory is automatically released
 when the function returns. The '``alloca``' instruction is commonly used
 to represent automatic variables that must have an address available. When
 the function returns (either with the ``ret`` or ``resume`` instructions),
 the memory is reclaimed. Allocating zero bytes is legal, but the returned
 pointer may not be unique. The order in which memory is allocated (ie.,
 which way the stack grows) is not specified.
 
 Note that '``alloca``' outside of the alloca address space from the

llvm/lib/Transforms/Utils/PromoteMemoryToRegister.cpp

for (User *U : make_early_inc_range(AI->users())) {
 
     // Find the nearest store that has a lower index than this load.
     StoresByIndexTy::iterator I = llvm::lower_bound(
         StoresByIndex,
         std::make_pair(LoadIdx, static_cast<StoreInst *>(nullptr)),
         less_first());
     if (I == StoresByIndex.begin()) {
       if (StoresByIndex.empty())
-        // If there are no stores, the load takes the undef value.
-        LI->replaceAllUsesWith(UndefValue::get(LI->getType()));
+        // If there are no stores, the load takes the poison value.
+        LI->replaceAllUsesWith(PoisonValue::get(LI->getType()));
       else
         // There is no store before this load, bail out (load may be affected
         // by the following stores - see main comment).
         return false;
     } else {
       // Otherwise, there was a store before this load, the load takes its value.
       // Note, if the load was marked as nonnull we don't want to lose that
       // information when we erase it. So we preserve it with an assume.
for (BasicBlock *BB : PHIBlocks)
       QueuePhiNode(BB, AllocaNum, CurrentVersion);
   }
 
   if (Allocas.empty())
     return; // All of the allocas must have been trivial!
 
   LBI.clear();
 
-  // Set the incoming values for the basic block to be null values for all of
+  // Set the incoming values for the basic block to be poison values for all of
   // the alloca's.  We do this in case there is a load of a value that has not
-  // been stored yet.  In this case, it will get this null value.
+  // been stored yet.  In this case, it will get this poison value.
   RenamePassData::ValVector Values(Allocas.size());
   for (unsigned i = 0, e = Allocas.size(); i != e; ++i)
-    Values[i] = UndefValue::get(Allocas[i]->getAllocatedType());
+    Values[i] = PoisonValue::get(Allocas[i]->getAllocatedType());
 
   // When handling debug info, treat all incoming values as if they have unknown
   // locations until proven otherwise.
   RenamePassData::LocationVector Locations(Allocas.size());
 
   // Walks all basic blocks in the function performing the SSA rename algorithm
   // and inserting the phi nodes we marked as necessary
   std::vector<RenamePassData> RenamePassWorkList;
for (DenseMap<std::pair<unsigned, unsigned>, PHINode *>::iterator
     // At this point, the blocks left in the preds list must have dummy
     // entries inserted into every PHI nodes for the block.  Update all the phi
     // nodes in this block that we are inserting (there could be phis before
     // mem2reg runs).
     unsigned NumBadPreds = SomePHI->getNumIncomingValues();
     BasicBlock::iterator BBI = BB->begin();
     while ((SomePHI = dyn_cast<PHINode>(BBI++)) &&
            SomePHI->getNumIncomingValues() == NumBadPreds) {
-      Value *UndefVal = UndefValue::get(SomePHI->getType());
+      Value *PoisonVal = PoisonValue::get(SomePHI->getType());
       for (BasicBlock *Pred : Preds)
-        SomePHI->addIncoming(UndefVal, Pred);
+        SomePHI->addIncoming(PoisonVal, Pred);
     }
   }
 
   NewPhiNodes.clear();
 }
 
 /// Determine which blocks the value is live in.
 ///

llvm/test/CodeGen/AMDGPU/vector-alloca-bitcast.ll

entry:
   %tmp3 = load i32, i32 addrspace(5)* %tmp2
   store i32 %tmp3, i32 addrspace(1)* %out
   ret void
 }
 
 ; OPT-LABEL: @vector_write_read_bitcast_to_float(
 ; OPT-NOT:   alloca
 ; OPT: bb2:
-; OPT:  %tmp.sroa.0.0 = phi <6 x float> [ undef, %bb ], [ %0, %bb2 ]
+; OPT:  %tmp.sroa.0.0 = phi <6 x float> [ poison, %bb ], [ %0, %bb2 ]
 ; OPT:  %0 = insertelement <6 x float> %tmp.sroa.0.0, float %tmp73, i32 %tmp10
 ; OPT: .preheader:
 ; OPT:  %bc = bitcast <6 x float> %0 to <6 x i32>
 ; OPT:  %1 = extractelement <6 x i32> %bc, i32 %tmp20
 
 ; GCN-LABEL: {{^}}vector_write_read_bitcast_to_float:
 ; GCN-ALLOCA: buffer_store_dword
 
.preheader:                                       ; preds = %.preheader, %bb2
   %tmp27 = add nuw nsw i32 %tmp16, 1
   %tmp28 = icmp eq i32 %tmp27, 1000
   br i1 %tmp28, label %bb15, label %.preheader
 }
 
 ; OPT-LABEL: @vector_write_read_bitcast_to_double(
 ; OPT-NOT:   alloca
 ; OPT: bb2:
-; OPT:  %tmp.sroa.0.0 = phi <6 x double> [ undef, %bb ], [ %0, %bb2 ]
+; OPT:  %tmp.sroa.0.0 = phi <6 x double> [ poison, %bb ], [ %0, %bb2 ]
 ; OPT:  %0 = insertelement <6 x double> %tmp.sroa.0.0, double %tmp73, i32 %tmp10
 ; OPT: .preheader:
 ; OPT:  %bc = bitcast <6 x double> %0 to <6 x i64>
 ; OPT:  %1 = extractelement <6 x i64> %bc, i32 %tmp20
 
 ; GCN-LABEL: {{^}}vector_write_read_bitcast_to_double:
 
 ; GCN-ALLOCA-COUNT-2: buffer_store_dword
.preheader:                                       ; preds = %.preheader, %bb2
   %tmp27 = add nuw nsw i32 %tmp16, 1
   %tmp28 = icmp eq i32 %tmp27, 1000
   br i1 %tmp28, label %bb15, label %.preheader
 }
 
 ; OPT-LABEL: @vector_write_read_bitcast_to_i64(
 ; OPT-NOT:   alloca
 ; OPT: bb2:
-; OPT:  %tmp.sroa.0.0 = phi <6 x i64> [ undef, %bb ], [ %0, %bb2 ]
+; OPT:  %tmp.sroa.0.0 = phi <6 x i64> [ poison, %bb ], [ %0, %bb2 ]
 ; OPT:  %0 = insertelement <6 x i64> %tmp.sroa.0.0, i64 %tmp6, i32 %tmp9
 ; OPT: .preheader:
 ; OPT:  %1 = extractelement <6 x i64> %0, i32 %tmp18
 
 ; GCN-LABEL: {{^}}vector_write_read_bitcast_to_i64:
 
 ; GCN-ALLOCA-COUNT-2: buffer_store_dword
 ; GCN-PROMOTE-COUNT-2: v_movreld_b32_e32

llvm/test/Transforms/Mem2Reg/debug-alloca-vla-1.ll

 target triple = "x86_64-apple-macosx10.12.0"
 
 ; Function Attrs: nounwind ssp uwtable
 define void @scan() #0 !dbg !4 {
 ; CHECK-LABEL: @scan(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    br label [[FOR_COND:%.*]], !dbg [[DBG10:![0-9]+]]
 ; CHECK:       for.cond:
-; CHECK-NEXT:    [[VLA1_0:%.*]] = phi i32 [ undef, [[ENTRY:%.*]] ], [ [[T0:%.*]], [[FOR_COND]] ]
+; CHECK-NEXT:    [[VLA1_0:%.*]] = phi i32 [ poison, [[ENTRY:%.*]] ], [ [[T0:%.*]], [[FOR_COND]] ]
 ; CHECK-NEXT:    call void @llvm.dbg.value(metadata i32 [[VLA1_0]], metadata [[META11:![0-9]+]], metadata !DIExpression()), !dbg [[DBG19:![0-9]+]]
 ; CHECK-NEXT:    [[T0]] = add i32 [[VLA1_0]], 1
 ; CHECK-NEXT:    call void @llvm.dbg.value(metadata i32 [[T0]], metadata [[META11]], metadata !DIExpression()), !dbg [[DBG19]]
 ; CHECK-NEXT:    br label [[FOR_COND]], !dbg [[DBG10]]
 ;
 entry:
   %vla1 = alloca i32, i32 1, align 8
   call void @llvm.dbg.declare(metadata i32* %vla1, metadata !10, metadata !DIExpression()), !dbg !18

llvm/test/Transforms/Mem2Reg/debug-alloca-vla-2.ll

 target triple = "x86_64-apple-macosx10.12.0"
 
 ; Function Attrs: nounwind ssp uwtable
 define void @scan(i32 %n) #0 !dbg !4 {
 ; CHECK-LABEL: @scan(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    br label [[FOR_COND:%.*]], !dbg [[DBG10:![0-9]+]]
 ; CHECK:       for.cond:
-; CHECK-NEXT:    [[VLA1_0:%.*]] = phi i32 [ undef, [[ENTRY:%.*]] ], [ [[T0:%.*]], [[FOR_COND]] ]
+; CHECK-NEXT:    [[VLA1_0:%.*]] = phi i32 [ poison, [[ENTRY:%.*]] ], [ [[T0:%.*]], [[FOR_COND]] ]
 ; CHECK-NEXT:    [[T0]] = add i32 [[VLA1_0]], 1
 ; CHECK-NEXT:    call void @llvm.dbg.value(metadata i32 undef, metadata [[META11:![0-9]+]], metadata !DIExpression()), !dbg [[DBG19:![0-9]+]]
 ; CHECK-NEXT:    br label [[FOR_COND]], !dbg [[DBG10]]
 ;
 entry:
   %vla1 = alloca i32, i32 %n, align 8
   call void @llvm.dbg.declare(metadata i32* %vla1, metadata !10, metadata !DIExpression()), !dbg !18
   br label %for.cond, !dbg !18

llvm/test/Transforms/Mem2Reg/pr24179.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt -mem2reg < %s -S | FileCheck %s
 ; RUN: opt -passes=mem2reg < %s -S | FileCheck %s
 
 declare i32 @def(i32)
 declare i1 @use(i32)
 
 ; Special case of a single-BB alloca does not apply here since the load
 ; is affected by the following store. Expect this case to be identified
 ; and a PHI node to be created.
 define void @test1() {
 ; CHECK-LABEL: @test1(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    br label [[LOOP:%.*]]
 ; CHECK:       loop:
-; CHECK-NEXT:    [[T_0:%.*]] = phi i32 [ undef, [[ENTRY:%.*]] ], [ [[N:%.*]], [[LOOP]] ]
+; CHECK-NEXT:    [[T_0:%.*]] = phi i32 [ poison, [[ENTRY:%.*]] ], [ [[N:%.*]], [[LOOP]] ]
 ; CHECK-NEXT:    [[C:%.*]] = call i1 @use(i32 [[T_0]])
 ; CHECK-NEXT:    [[N]] = call i32 @def(i32 7)
 ; CHECK-NEXT:    br i1 [[C]], label [[LOOP]], label [[EXIT:%.*]]
 ; CHECK:       exit:
 ; CHECK-NEXT:    ret void
 ;
   entry:
   %t = alloca i32

 
 ; Same as above, except there is no following store. The alloca should just be
 ; replaced with an undef
 define void @test2() {
 ; CHECK-LABEL: @test2(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    br label [[LOOP:%.*]]
 ; CHECK:       loop:
-; CHECK-NEXT:    [[C:%.*]] = call i1 @use(i32 undef)
+; CHECK-NEXT:    [[C:%.*]] = call i1 @use(i32 poison)
 ; CHECK-NEXT:    br i1 [[C]], label [[LOOP]], label [[EXIT:%.*]]
 ; CHECK:       exit:
 ; CHECK-NEXT:    ret void
 ;
   entry:
   %t = alloca i32
   br label %loop
 
   loop:
   %v = load i32, i32* %t
   %c = call i1 @use(i32 %v)
   br i1 %c, label %loop, label %exit
 
   exit:
   ret void
 }

llvm/test/Transforms/Mem2Reg/undef-order.ll

 ; CHECK-NEXT:    br label [[JOIN]]
 ; CHECK:       Block14:
 ; CHECK-NEXT:    br label [[JOIN]]
 ; CHECK:       Block15:
 ; CHECK-NEXT:    br label [[JOIN]]
 ; CHECK:       Block16:
 ; CHECK-NEXT:    br label [[JOIN]]
 ; CHECK:       Join:
-; CHECK-NEXT:    [[VAL_0:%.*]] = phi i32 [ 1, [[STORE1]] ], [ 2, [[STORE2]] ], [ undef, [[BLOCK1:%.*]] ], [ undef, [[BLOCK2:%.*]] ], [ undef, [[BLOCK3:%.*]] ], [ undef, [[BLOCK4:%.*]] ], [ undef, [[BLOCK5:%.*]] ], [ undef, [[BLOCK6:%.*]] ], [ undef, [[BLOCK7:%.*]] ], [ undef, [[BLOCK8:%.*]] ], [ undef, [[BLOCK9:%.*]] ], [ undef, [[BLOCK10:%.*]] ], [ undef, [[BLOCK11:%.*]] ], [ undef, [[BLOCK12:%.*]] ], [ undef, [[BLOCK13:%.*]] ], [ undef, [[BLOCK14:%.*]] ], [ undef, [[BLOCK15:%.*]] ], [ undef, [[BLOCK16:%.*]] ]
+; CHECK-NEXT:    [[VAL_0:%.*]] = phi i32 [ 1, [[STORE1]] ], [ 2, [[STORE2]] ], [ poison, [[BLOCK1:%.*]] ], [ poison, [[BLOCK2:%.*]] ], [ poison, [[BLOCK3:%.*]] ], [ poison, [[BLOCK4:%.*]] ], [ poison, [[BLOCK5:%.*]] ], [ poison, [[BLOCK6:%.*]] ], [ poison, [[BLOCK7:%.*]] ], [ poison, [[BLOCK8:%.*]] ], [ poison, [[BLOCK9:%.*]] ], [ poison, [[BLOCK10:%.*]] ], [ poison, [[BLOCK11:%.*]] ], [ poison, [[BLOCK12:%.*]] ], [ poison, [[BLOCK13:%.*]] ], [ poison, [[BLOCK14:%.*]] ], [ poison, [[BLOCK15:%.*]] ], [ poison, [[BLOCK16:%.*]] ]
 ; CHECK-NEXT:    ret i32 [[VAL_0]]
 ;
 Entry:
   %val = alloca i32
   %c1 = call i1 @cond()
   br i1 %c1, label %Store1, label %Store2
 Block1:
   br label %Join

llvm/test/Transforms/PhaseOrdering/X86/nancvt.ll

 ; CHECK-NEXT:    store volatile i32 -1610612736, i32* @var, align 4
 ; CHECK-NEXT:    store volatile i32 2147027116, i32* @var, align 4
 ; CHECK-NEXT:    store volatile i32 -2147483648, i32* @var, align 4
 ; CHECK-NEXT:    store volatile i32 2147027116, i32* @var, align 4
 ; CHECK-NEXT:    store volatile i32 -1073741824, i32* @var, align 4
 ; CHECK-NEXT:    store volatile i32 2147228864, i32* @var, align 4
 ; CHECK-NEXT:    store volatile i32 2147228864, i32* @var, align 4
 ; CHECK-NEXT:    store volatile i32 2147228864, i32* @var, align 4
-; CHECK-NEXT:    ret i32 undef
+; CHECK-NEXT:    ret i32 poison
 ;
 entry:
   %retval = alloca i32, align 4
   %i = alloca i32, align 4
   %uf = alloca %struct..0anon, align 4
   %ud = alloca %struct..1anon, align 8
   %"alloca point" = bitcast i32 0 to i32
   store i32 0, i32* %i, align 4

llvm/test/Transforms/SROA/addrspacecast.ll

entry:
   %val = load i64, i64* %gep.bitcast
   ret i64 %val
 }
 
 ; Don't change the address space of a volatile operation
 define i64 @alloca_addrspacecast_bitcast_volatile_store(i64 %X) {
 ; CHECK-LABEL: @alloca_addrspacecast_bitcast_volatile_store(
 ; CHECK-NEXT:  entry:
-; CHECK-NEXT:    [[A:%.*]] = alloca [8 x i8]
+; CHECK-NEXT:    [[A:%.*]] = alloca [8 x i8], align 1
 ; CHECK-NEXT:    [[A_CAST:%.*]] = addrspacecast [8 x i8]* [[A]] to [8 x i8] addrspace(1)*
 ; CHECK-NEXT:    [[B:%.*]] = bitcast [8 x i8] addrspace(1)* [[A_CAST]] to i64 addrspace(1)*
-; CHECK-NEXT:    store volatile i64 [[X:%.*]], i64 addrspace(1)* [[B]]
-; CHECK-NEXT:    [[Z:%.*]] = load i64, i64 addrspace(1)* [[B]]
+; CHECK-NEXT:    store volatile i64 [[X:%.*]], i64 addrspace(1)* [[B]], align 4
+; CHECK-NEXT:    [[Z:%.*]] = load i64, i64 addrspace(1)* [[B]], align 4
 ; CHECK-NEXT:    ret i64 [[Z]]
 ;
 entry:
   %A = alloca [8 x i8]
   %A.cast = addrspacecast [8 x i8]* %A to [8 x i8] addrspace(1)*
   %B = bitcast [8 x i8] addrspace(1)* %A.cast to i64 addrspace(1)*
   store volatile i64 %X, i64 addrspace(1)* %B
   %Z = load i64, i64 addrspace(1)* %B
   ret i64 %Z
 }
 
 ; Don't change the address space of a volatile operation
 define i64 @alloca_addrspacecast_bitcast_volatile_load(i64 %X) {
 ; CHECK-LABEL: @alloca_addrspacecast_bitcast_volatile_load(
 ; CHECK-NEXT:  entry:
-; CHECK-NEXT:    [[A:%.*]] = alloca [8 x i8]
+; CHECK-NEXT:    [[A:%.*]] = alloca [8 x i8], align 1
 ; CHECK-NEXT:    [[A_CAST:%.*]] = addrspacecast [8 x i8]* [[A]] to [8 x i8] addrspace(1)*
 ; CHECK-NEXT:    [[B:%.*]] = bitcast [8 x i8] addrspace(1)* [[A_CAST]] to i64 addrspace(1)*
-; CHECK-NEXT:    store i64 [[X:%.*]], i64 addrspace(1)* [[B]]
-; CHECK-NEXT:    [[Z:%.*]] = load volatile i64, i64 addrspace(1)* [[B]]
+; CHECK-NEXT:    store i64 [[X:%.*]], i64 addrspace(1)* [[B]], align 4
+; CHECK-NEXT:    [[Z:%.*]] = load volatile i64, i64 addrspace(1)* [[B]], align 4
 ; CHECK-NEXT:    ret i64 [[Z]]
 ;
 entry:
   %A = alloca [8 x i8]
   %A.cast = addrspacecast [8 x i8]* %A to [8 x i8] addrspace(1)*
   %B = bitcast [8 x i8] addrspace(1)* %A.cast to i64 addrspace(1)*
   store i64 %X, i64 addrspace(1)* %B
   %Z = load volatile i64, i64 addrspace(1)* %B
   ret i64 %Z
 }
 
 declare void @llvm.memset.p1i8.i32(i8 addrspace(1)* nocapture, i8, i32, i1) nounwind
 
 ; Don't change the address space of a volatile operation
 define i32 @volatile_memset() {
 ; CHECK-LABEL: @volatile_memset(
 ; CHECK-NEXT:  entry:
-; CHECK-NEXT:    [[A:%.*]] = alloca [4 x i8]
+; CHECK-NEXT:    [[A:%.*]] = alloca [4 x i8], align 1
 ; CHECK-NEXT:    [[PTR:%.*]] = getelementptr [4 x i8], [4 x i8]* [[A]], i32 0, i32 0
 ; CHECK-NEXT:    [[ASC:%.*]] = addrspacecast i8* [[PTR]] to i8 addrspace(1)*
 ; CHECK-NEXT:    call void @llvm.memset.p1i8.i32(i8 addrspace(1)* [[ASC]], i8 42, i32 4, i1 true)
 ; CHECK-NEXT:    [[IPTR:%.*]] = bitcast i8* [[PTR]] to i32*
-; CHECK-NEXT:    [[VAL:%.*]] = load i32, i32* [[IPTR]]
+; CHECK-NEXT:    [[VAL:%.*]] = load i32, i32* [[IPTR]], align 4
 ; CHECK-NEXT:    ret i32 [[VAL]]
 ;
 entry:
   %a = alloca [4 x i8]
   %ptr = getelementptr [4 x i8], [4 x i8]* %a, i32 0, i32 0
   %asc = addrspacecast i8* %ptr to i8 addrspace(1)*
   call void @llvm.memset.p1i8.i32(i8 addrspace(1)* %asc, i8 42, i32 4, i1 true)
   %iptr = bitcast i8* %ptr to i32*
   %val = load i32, i32* %iptr
   ret i32 %val
 }
 
 ; Don't change the address space of a volatile operation
 define void @volatile_memcpy(i8* %src, i8* %dst) {
 ; CHECK-LABEL: @volatile_memcpy(
 ; CHECK-NEXT:  entry:
-; CHECK-NEXT:    [[A:%.*]] = alloca [4 x i8]
+; CHECK-NEXT:    [[A:%.*]] = alloca [4 x i8], align 1
 ; CHECK-NEXT:    [[PTR:%.*]] = getelementptr [4 x i8], [4 x i8]* [[A]], i32 0, i32 0
 ; CHECK-NEXT:    [[ASC:%.*]] = addrspacecast i8* [[PTR]] to i8 addrspace(1)*
-; CHECK-NEXT:    call void @llvm.memcpy.p1i8.p0i8.i32(i8 addrspace(1)* [[ASC]], i8* [[SRC:%.*]], i32 4, i1 true), !tbaa !0
-; CHECK-NEXT:    call void @llvm.memcpy.p0i8.p1i8.i32(i8* [[DST:%.*]], i8 addrspace(1)* [[ASC]], i32 4, i1 true), !tbaa !3
+; CHECK-NEXT:    call void @llvm.memcpy.p1i8.p0i8.i32(i8 addrspace(1)* [[ASC]], i8* [[SRC:%.*]], i32 4, i1 true), !tbaa [[TBAA0:![0-9]+]]
+; CHECK-NEXT:    call void @llvm.memcpy.p0i8.p1i8.i32(i8* [[DST:%.*]], i8 addrspace(1)* [[ASC]], i32 4, i1 true), !tbaa [[TBAA3:![0-9]+]]
 ; CHECK-NEXT:    ret void
 ;
 entry:
   %a = alloca [4 x i8]
   %ptr = getelementptr [4 x i8], [4 x i8]* %a, i32 0, i32 0
   %asc = addrspacecast i8* %ptr to i8 addrspace(1)*
   call void @llvm.memcpy.p1i8.p0i8.i32(i8 addrspace(1)* %asc, i8* %src, i32 4, i1 true), !tbaa !0
   call void @llvm.memcpy.p0i8.p1i8.i32(i8* %dst, i8 addrspace(1)* %asc, i32 4, i1 true), !tbaa !3

 
 ;; If this was external, we wouldn't be able to prove dereferenceability
 ;; of the location.
 @gv = addrspace(1) global i64 zeroinitializer
 
 define void @select_addrspacecast_gv(i1 %a, i1 %b) {
 ; CHECK-LABEL: @select_addrspacecast_gv(
 ; CHECK-NEXT:    [[COND_SROA_SPECULATE_LOAD_FALSE:%.*]] = load i64, i64 addrspace(1)* @gv, align 8
-; CHECK-NEXT:    [[COND_SROA_SPECULATED:%.*]] = select i1 undef, i64 undef, i64 [[COND_SROA_SPECULATE_LOAD_FALSE]]
+; CHECK-NEXT:    [[COND_SROA_SPECULATED:%.*]] = select i1 undef, i64 poison, i64 [[COND_SROA_SPECULATE_LOAD_FALSE]]
 ; CHECK-NEXT:    ret void
 ;
   %c = alloca i64, align 8
   %p.0.c = select i1 undef, i64* %c, i64* %c
   %asc = addrspacecast i64* %p.0.c to i64 addrspace(1)*
 
   %cond.in = select i1 undef, i64 addrspace(1)* %asc, i64 addrspace(1)* @gv
   %cond = load i64, i64 addrspace(1)* %cond.in, align 8
   ret void
 }
 
 define i8 @select_addrspacecast_i8() {
 ; CHECK-LABEL: @select_addrspacecast_i8(
-; CHECK-NEXT:    [[RET_SROA_SPECULATED:%.*]] = select i1 undef, i8 undef, i8 undef
+; CHECK-NEXT:    [[RET_SROA_SPECULATED:%.*]] = select i1 undef, i8 poison, i8 poison
 ; CHECK-NEXT:    ret i8 [[RET_SROA_SPECULATED]]
 ;
   %a = alloca i8
   %b = alloca i8
 
   %a.ptr = addrspacecast i8* %a to i8 addrspace(1)*
   %b.ptr = addrspacecast i8* %b to i8 addrspace(1)*
 

llvm/test/Transforms/SROA/basictest.ll

 ; registers. This in turn was missed as an optimization by SROA due to the
 ; partial loads and stores of integers to the double alloca we were trying to
 ; form and promote. The solution is to widen the integer operations to be
 ; whole-alloca operations, and perform the appropriate bitcasting on the
 ; *values* rather than the pointers. When this works, partial reads and writes
 ; via integers can be promoted away.
 ; CHECK-LABEL: @PR14059.1(
 ; CHECK-NEXT:  entry:
-; CHECK-NEXT:    [[TMP0:%.*]] = bitcast double undef to i64
+; CHECK-NEXT:    [[TMP0:%.*]] = bitcast double poison to i64
 ; CHECK-NEXT:    [[X_SROA_0_I_0_INSERT_MASK:%.*]] = and i64 [[TMP0]], -4294967296
 ; CHECK-NEXT:    [[TMP1:%.*]] = bitcast i64 [[X_SROA_0_I_0_INSERT_MASK]] to double
 ; CHECK-NEXT:    [[TMP2:%.*]] = bitcast double [[TMP1]] to i64
 ; CHECK-NEXT:    [[X_SROA_0_I_2_INSERT_MASK:%.*]] = and i64 [[TMP2]], -281474976645121
 ; CHECK-NEXT:    [[TMP3:%.*]] = bitcast i64 [[X_SROA_0_I_2_INSERT_MASK]] to double
 ; CHECK-NEXT:    [[TMP4:%.*]] = bitcast double [[TMP3]] to i64
 ; CHECK-NEXT:    [[X_SROA_0_I_4_D_RAW_SROA_CAST:%.*]] = bitcast double* [[D:%.*]] to i32*
 ; CHECK-NEXT:    [[X_SROA_0_I_4_COPYLOAD:%.*]] = load i32, i32* [[X_SROA_0_I_4_D_RAW_SROA_CAST]], align 1

 }
 
 define i32 @PR14572.2(<3 x i8> %x) {
 ; Ensure that a split integer load which is wider than the type size of the
 ; alloca (relying on the alloc size padding) doesn't trigger an assert.
 ; CHECK-LABEL: @PR14572.2(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[TMP0:%.*]] = bitcast <3 x i8> [[X:%.*]] to i24
-; CHECK-NEXT:    [[A_SROA_2_0_INSERT_EXT:%.*]] = zext i8 undef to i32
+; CHECK-NEXT:    [[A_SROA_2_0_INSERT_EXT:%.*]] = zext i8 poison to i32
 ; CHECK-NEXT:    [[A_SROA_2_0_INSERT_SHIFT:%.*]] = shl i32 [[A_SROA_2_0_INSERT_EXT]], 24
 ; CHECK-NEXT:    [[A_SROA_2_0_INSERT_MASK:%.*]] = and i32 undef, 16777215
 ; CHECK-NEXT:    [[A_SROA_2_0_INSERT_INSERT:%.*]] = or i32 [[A_SROA_2_0_INSERT_MASK]], [[A_SROA_2_0_INSERT_SHIFT]]
 ; CHECK-NEXT:    [[A_0_INSERT_EXT:%.*]] = zext i24 [[TMP0]] to i32
 ; CHECK-NEXT:    [[A_0_INSERT_MASK:%.*]] = and i32 [[A_SROA_2_0_INSERT_INSERT]], -16777216
 ; CHECK-NEXT:    [[A_0_INSERT_INSERT:%.*]] = or i32 [[A_0_INSERT_MASK]], [[A_0_INSERT_EXT]]
 ; CHECK-NEXT:    ret i32 [[A_0_INSERT_INSERT]]
 ;

 end:
   %tmp.raw = bitcast [4 x i8]* %tmp to i8*
   call void @llvm.memcpy.p0i8.p0i8.i32(i8* %data, i8* %tmp.raw, i32 %size, i1 false)
   ret void
 }
 
 define void @PR15805(i1 %a, i1 %b) {
 ; CHECK-LABEL: @PR15805(
-; CHECK-NEXT:    [[COND_SROA_SPECULATED:%.*]] = select i1 undef, i64 undef, i64 undef
+; CHECK-NEXT:    [[COND_SROA_SPECULATED:%.*]] = select i1 undef, i64 poison, i64 poison
 ; CHECK-NEXT:    ret void
 ;
 
   %c = alloca i64, align 8
   %p.0.c = select i1 undef, i64* %c, i64* %c
   %cond.in = select i1 undef, i64* %p.0.c, i64* %c
   %cond = load i64, i64* %cond.in, align 8
   ret void
 }
 
 define void @PR15805.1(i1 %a, i1 %b) {
 ; Same as the normal PR15805, but rigged to place the use before the def inside
 ; of looping unreachable code. This helps ensure that we aren't sensitive to the
 ; order in which the uses of the alloca are visited.
 ;
 ; CHECK-LABEL: @PR15805.1(
 ; CHECK-NEXT:    br label [[EXIT:%.*]]
 ; CHECK:       loop:
-; CHECK-NEXT:    [[COND_SROA_SPECULATED:%.*]] = select i1 undef, i64 undef, i64 undef
+; CHECK-NEXT:    [[COND_SROA_SPECULATED:%.*]] = select i1 undef, i64 poison, i64 poison
 ; CHECK-NEXT:    br i1 undef, label [[LOOP:%.*]], label [[EXIT]]
 ; CHECK:       exit:
 ; CHECK-NEXT:    ret void
 ;
 
   %c = alloca i64, align 8
   br label %exit
 

 ; this alloca we need to handle it specially to ensure the splits line up
 ; properly for rewriting.
 ;
 ; CHECK-LABEL: @PR22093(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[A_SROA_0:%.*]] = alloca i16, align 4
 ; CHECK-NEXT:    store volatile i16 42, i16* [[A_SROA_0]], align 4
 ; CHECK-NEXT:    [[A_SROA_0_0_A_SROA_0_0_LOAD:%.*]] = load i16, i16* [[A_SROA_0]], align 4
-; CHECK-NEXT:    [[A_SROA_3_0_INSERT_EXT:%.*]] = zext i16 undef to i32
+; CHECK-NEXT:    [[A_SROA_3_0_INSERT_EXT:%.*]] = zext i16 poison to i32
 ; CHECK-NEXT:    [[A_SROA_3_0_INSERT_SHIFT:%.*]] = shl i32 [[A_SROA_3_0_INSERT_EXT]], 16
 ; CHECK-NEXT:    [[A_SROA_3_0_INSERT_MASK:%.*]] = and i32 undef, 65535
 ; CHECK-NEXT:    [[A_SROA_3_0_INSERT_INSERT:%.*]] = or i32 [[A_SROA_3_0_INSERT_MASK]], [[A_SROA_3_0_INSERT_SHIFT]]
 ; CHECK-NEXT:    [[A_SROA_0_0_INSERT_EXT:%.*]] = zext i16 [[A_SROA_0_0_A_SROA_0_0_LOAD]] to i32
 ; CHECK-NEXT:    [[A_SROA_0_0_INSERT_MASK:%.*]] = and i32 [[A_SROA_3_0_INSERT_INSERT]], -65536
 ; CHECK-NEXT:    [[A_SROA_0_0_INSERT_INSERT:%.*]] = or i32 [[A_SROA_0_0_INSERT_MASK]], [[A_SROA_0_0_INSERT_EXT]]
 ; CHECK-NEXT:    [[A_SROA_0_0_EXTRACT_TRUNC:%.*]] = trunc i32 [[A_SROA_0_0_INSERT_INSERT]] to i16
 ; CHECK-NEXT:    store i16 [[A_SROA_0_0_EXTRACT_TRUNC]], i16* [[A_SROA_0]], align 4

 ; presplit.
 ;
 ; CHECK-LABEL: @PR22093.2(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[A_SROA_0:%.*]] = alloca i16, align 8
 ; CHECK-NEXT:    [[A_SROA_31:%.*]] = alloca i8, align 4
 ; CHECK-NEXT:    store volatile i16 42, i16* [[A_SROA_0]], align 8
 ; CHECK-NEXT:    [[A_SROA_0_0_A_SROA_0_0_LOAD:%.*]] = load i16, i16* [[A_SROA_0]], align 8
-; CHECK-NEXT:    [[A_SROA_3_0_INSERT_EXT:%.*]] = zext i16 undef to i32
+; CHECK-NEXT:    [[A_SROA_3_0_INSERT_EXT:%.*]] = zext i16 poison to i32
 ; CHECK-NEXT:    [[A_SROA_3_0_INSERT_SHIFT:%.*]] = shl i32 [[A_SROA_3_0_INSERT_EXT]], 16
 ; CHECK-NEXT:    [[A_SROA_3_0_INSERT_MASK:%.*]] = and i32 undef, 65535
 ; CHECK-NEXT:    [[A_SROA_3_0_INSERT_INSERT:%.*]] = or i32 [[A_SROA_3_0_INSERT_MASK]], [[A_SROA_3_0_INSERT_SHIFT]]
 ; CHECK-NEXT:    [[A_SROA_0_0_INSERT_EXT:%.*]] = zext i16 [[A_SROA_0_0_A_SROA_0_0_LOAD]] to i32
 ; CHECK-NEXT:    [[A_SROA_0_0_INSERT_MASK:%.*]] = and i32 [[A_SROA_3_0_INSERT_INSERT]], -65536
 ; CHECK-NEXT:    [[A_SROA_0_0_INSERT_INSERT:%.*]] = or i32 [[A_SROA_0_0_INSERT_MASK]], [[A_SROA_0_0_INSERT_EXT]]
 ; CHECK-NEXT:    [[A_SROA_0_0_EXTRACT_TRUNC:%.*]] = trunc i32 [[A_SROA_0_0_INSERT_INSERT]] to i16
 ; CHECK-NEXT:    store i16 [[A_SROA_0_0_EXTRACT_TRUNC]], i16* [[A_SROA_0]], align 8

 ; CHECK-NEXT:    [[TMP0:%.*]] = bitcast float* [[ARRAYIDX5]] to i32*
 ; CHECK-NEXT:    br label [[BB2:%.*]]
 ; CHECK:       bb2:
 ; CHECK-NEXT:    [[I_02:%.*]] = phi i32 [ [[NUM]], [[BB1]] ], [ [[SUB:%.*]], [[BB5:%.*]] ]
 ; CHECK-NEXT:    br i1 [[TOBOOL]], label [[BB3:%.*]], label [[BB4:%.*]]
 ; CHECK:       bb3:
 ; CHECK-NEXT:    br label [[BB5]]
 ; CHECK:       bb4:
-; CHECK-NEXT:    store i32 undef, i32* [[TMP0]], align 4
+; CHECK-NEXT:    store i32 poison, i32* [[TMP0]], align 4
 ; CHECK-NEXT:    br label [[BB5]]
 ; CHECK:       bb5:
 ; CHECK-NEXT:    [[SUB]] = add i32 [[I_02]], -1
 ; CHECK-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[SUB]], 0
 ; CHECK-NEXT:    br i1 [[CMP]], label [[BB2]], label [[BB6:%.*]]
 ; CHECK:       bb6:
 ; CHECK-NEXT:    br label [[BB7]]
 ; CHECK:       bb7:

llvm/test/Transforms/SROA/phi-and-select.ll

 ; CHECK-NEXT:    [[TEST:%.*]] = icmp ne i32 [[B:%.*]], 0
 ; CHECK-NEXT:    br i1 [[TEST]], label [[THEN:%.*]], label [[ELSE:%.*]]
 ; CHECK:       then:
 ; CHECK-NEXT:    [[PHI_SROA_SPECULATE_LOAD_THEN:%.*]] = load i32, i32* [[PTR:%.*]], align 4
 ; CHECK-NEXT:    br label [[EXIT:%.*]]
 ; CHECK:       else:
 ; CHECK-NEXT:    br label [[EXIT]]
 ; CHECK:       exit:
-; CHECK-NEXT:    [[PHI_SROA_SPECULATED:%.*]] = phi i32 [ undef, [[ELSE]] ], [ [[PHI_SROA_SPECULATE_LOAD_THEN]], [[THEN]] ]
+; CHECK-NEXT:    [[PHI_SROA_SPECULATED:%.*]] = phi i32 [ poison, [[ELSE]] ], [ [[PHI_SROA_SPECULATE_LOAD_THEN]], [[THEN]] ]
 ; CHECK-NEXT:    ret i32 [[PHI_SROA_SPECULATED]]
 ;
 
 entry:
   %f = alloca float
   %test = icmp ne i32 %b, 0
   br i1 %test, label %then, label %else
 

 
 define i32 @test9(i32 %b, i32* %ptr) {
 ; Same as @test8 but for a select rather than a PHI node.
 ; CHECK-LABEL: @test9(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    store i32 0, i32* [[PTR:%.*]], align 4
 ; CHECK-NEXT:    [[TEST:%.*]] = icmp ne i32 [[B:%.*]], 0
 ; CHECK-NEXT:    [[LOADED_SROA_SPECULATE_LOAD_FALSE:%.*]] = load i32, i32* [[PTR]], align 4
-; CHECK-NEXT:    [[LOADED_SROA_SPECULATED:%.*]] = select i1 [[TEST]], i32 undef, i32 [[LOADED_SROA_SPECULATE_LOAD_FALSE]]
+; CHECK-NEXT:    [[LOADED_SROA_SPECULATED:%.*]] = select i1 [[TEST]], i32 poison, i32 [[LOADED_SROA_SPECULATE_LOAD_FALSE]]
 ; CHECK-NEXT:    ret i32 [[LOADED_SROA_SPECULATED]]
 ;
 
 entry:
   %f = alloca float
   store i32 0, i32* %ptr
   %test = icmp ne i32 %b, 0
   %bitcast = bitcast float* %f to i32*

llvm/test/Transforms/SROA/phi-gep.ll

 ; CHECK-NEXT:    i32 3, label [[BB_4:%.*]]
 ; CHECK-NEXT:    i32 4, label [[BB_4]]
 ; CHECK-NEXT:    ]
 ; CHECK:       bb.2:
 ; CHECK-NEXT:    br label [[BB_4]]
 ; CHECK:       bb.3:
 ; CHECK-NEXT:    br label [[BB_4]]
 ; CHECK:       bb.4:
-; CHECK-NEXT:    [[PHI_SROA_PHI_SROA_SPECULATED:%.*]] = phi i32 [ undef, [[BB_3]] ], [ undef, [[BB_2]] ], [ undef, [[BB_1:%.*]] ], [ undef, [[BB_1]] ]
+; CHECK-NEXT:    [[PHI_SROA_PHI_SROA_SPECULATED:%.*]] = phi i32 [ poison, [[BB_3]] ], [ poison, [[BB_2]] ], [ poison, [[BB_1:%.*]] ], [ poison, [[BB_1]] ]
 ; CHECK-NEXT:    ret i32 [[PHI_SROA_PHI_SROA_SPECULATED]]
 ;
 bb.1:
   %a = alloca %pair, align 4
   %b = alloca %pair, align 4
   switch i32 %arg, label %bb.3 [
   i32 1, label %bb.2
   i32 2, label %bb.2

llvm/test/Transforms/SROA/phi-with-duplicate-pred.ll

 ; CHECK-NEXT:    [[G_0_SROA_SPECULATE_LOAD_CLEANUP:%.*]] = load i16, i16* @a, align 1
 ; CHECK-NEXT:    switch i32 2, label [[CLEANUP7:%.*]] [
 ; CHECK-NEXT:    i32 0, label [[LBL1:%.*]]
 ; CHECK-NEXT:    i32 2, label [[LBL1]]
 ; CHECK-NEXT:    ]
 ; CHECK:       if.else:
 ; CHECK-NEXT:    br label [[LBL1]]
 ; CHECK:       lbl1:
-; CHECK-NEXT:    [[G_0_SROA_SPECULATED:%.*]] = phi i16 [ [[G_0_SROA_SPECULATE_LOAD_CLEANUP]], [[CLEANUP]] ], [ [[G_0_SROA_SPECULATE_LOAD_CLEANUP]], [[CLEANUP]] ], [ undef, [[IF_ELSE]] ]
+; CHECK-NEXT:    [[G_0_SROA_SPECULATED:%.*]] = phi i16 [ [[G_0_SROA_SPECULATE_LOAD_CLEANUP]], [[CLEANUP]] ], [ [[G_0_SROA_SPECULATE_LOAD_CLEANUP]], [[CLEANUP]] ], [ poison, [[IF_ELSE]] ]
 ; CHECK-NEXT:    unreachable
 ; CHECK:       cleanup7:
 ; CHECK-NEXT:    ret void
 ;
 entry:
   %e = alloca i16, align 1
   br i1 undef, label %if.then, label %if.else
 

llvm/test/Transforms/SROA/pr37267.ll

; slice 4: [2,4)
 
   %rc = add i16 %_tmp13, %_tmp16
   ret i16 %rc
 }
 
 define i16 @f2() {
 ; CHECK-LABEL: @f2(
 ; CHECK-NEXT:  bb1:
-; CHECK-NEXT:    [[A_3_SROA_2_2_INSERT_EXT:%.*]] = zext i16 undef to i32
+; CHECK-NEXT:    [[A_3_SROA_2_2_INSERT_EXT:%.*]] = zext i16 poison to i32
 ; CHECK-NEXT:    [[A_3_SROA_2_2_INSERT_MASK:%.*]] = and i32 undef, -65536
 ; CHECK-NEXT:    [[A_3_SROA_2_2_INSERT_INSERT:%.*]] = or i32 [[A_3_SROA_2_2_INSERT_MASK]], [[A_3_SROA_2_2_INSERT_EXT]]
-; CHECK-NEXT:    [[A_3_SROA_0_2_INSERT_EXT:%.*]] = zext i16 undef to i32
+; CHECK-NEXT:    [[A_3_SROA_0_2_INSERT_EXT:%.*]] = zext i16 poison to i32
 ; CHECK-NEXT:    [[A_3_SROA_0_2_INSERT_SHIFT:%.*]] = shl i32 [[A_3_SROA_0_2_INSERT_EXT]], 16
 ; CHECK-NEXT:    [[A_3_SROA_0_2_INSERT_MASK:%.*]] = and i32 [[A_3_SROA_2_2_INSERT_INSERT]], 65535
 ; CHECK-NEXT:    [[A_3_SROA_0_2_INSERT_INSERT:%.*]] = or i32 [[A_3_SROA_0_2_INSERT_MASK]], [[A_3_SROA_0_2_INSERT_SHIFT]]
-; CHECK-NEXT:    [[RC:%.*]] = add i16 2, undef
+; CHECK-NEXT:    [[RC:%.*]] = add i16 2, poison
 ; CHECK-NEXT:    ret i16 [[RC]]
 ;
 
 bb1:
 ; This 12-byte alloca is split into partitions as [0,2), [2,4), [4,8), [8,10), [10, 12).
 ; The reported error happened when visitLoadInst rewrites a split tail of slice 1 for [4, 8) partition.
 ; alloca  012345678901
 ; slice 1:  RRRR

llvm/test/Transforms/SROA/scalable-vectors.ll

 
 ; When casting from VLA to VLS via memory check we bail out when producing a
 ; GEP where the element type is a scalable vector.
 define <vscale x 4 x i32> @cast_alloca_from_svint32_t() {
 ; CHECK-LABEL: @cast_alloca_from_svint32_t(
 ; CHECK-NEXT:    [[RETVAL_COERCE:%.*]] = alloca <vscale x 4 x i32>, align 16
 ; CHECK-NEXT:    [[TMP1:%.*]] = bitcast <vscale x 4 x i32>* [[RETVAL_COERCE]] to i8*
 ; CHECK-NEXT:    [[RETVAL_0__SROA_CAST:%.*]] = bitcast i8* [[TMP1]] to <16 x i32>*
-; CHECK-NEXT:    store <16 x i32> undef, <16 x i32>* [[RETVAL_0__SROA_CAST]], align 16
+; CHECK-NEXT:    store <16 x i32> poison, <16 x i32>* [[RETVAL_0__SROA_CAST]], align 16
 ; CHECK-NEXT:    [[TMP2:%.*]] = load <vscale x 4 x i32>, <vscale x 4 x i32>* [[RETVAL_COERCE]], align 16
 ; CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP2]]
 ;
   %retval = alloca <16 x i32>
   %retval.coerce = alloca <vscale x 4 x i32>
   %1 = bitcast <vscale x 4 x i32>* %retval.coerce to i8*
   %2 = bitcast <16 x i32>* %retval to i8*
   call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 16 %1, i8* align 16 %2, i64 64, i1 false)
   %3 = load <vscale x 4 x i32>, <vscale x 4 x i32>* %retval.coerce
   ret <vscale x 4 x i32> %3
 }
 
 declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i1) nounwind

llvm/test/Transforms/SROA/slice-width.ll

 ; PR18726: Check that SROA does not rewrite a 12-byte memcpy into a 16-byte
 ; vector store, hence accidentally putting gibberish onto the stack.
 define i32 @memcpy_vec3float_widening(%S.vec3float* %x) {
 ; CHECK-LABEL: @memcpy_vec3float_widening(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[TMP1_SROA_0_0_TMP1_SROA_0_0__SROA_CAST_SROA_CAST:%.*]] = bitcast %S.vec3float* [[X:%.*]] to <3 x float>*
 ; CHECK-NEXT:    [[TMP1_SROA_0_0_COPYLOAD:%.*]] = load <3 x float>, <3 x float>* [[TMP1_SROA_0_0_TMP1_SROA_0_0__SROA_CAST_SROA_CAST]], align 4
 ; CHECK-NEXT:    [[TMP1_SROA_0_0_VEC_EXPAND:%.*]] = shufflevector <3 x float> [[TMP1_SROA_0_0_COPYLOAD]], <3 x float> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 undef>
-; CHECK-NEXT:    [[TMP1_SROA_0_0_VECBLEND:%.*]] = select <4 x i1> <i1 true, i1 true, i1 true, i1 false>, <4 x float> [[TMP1_SROA_0_0_VEC_EXPAND]], <4 x float> undef
+; CHECK-NEXT:    [[TMP1_SROA_0_0_VECBLEND:%.*]] = select <4 x i1> <i1 true, i1 true, i1 true, i1 false>, <4 x float> [[TMP1_SROA_0_0_VEC_EXPAND]], <4 x float> poison
 ; CHECK-NEXT:    [[TMP2:%.*]] = alloca [[S_VEC3FLOAT:%.*]], align 4
 ; CHECK-NEXT:    [[TMP1_SROA_0_0_TMP1_SROA_0_0__SROA_CAST2_SROA_CAST:%.*]] = bitcast %S.vec3float* [[TMP2]] to <3 x float>*
 ; CHECK-NEXT:    [[TMP1_SROA_0_0_VEC_EXTRACT:%.*]] = shufflevector <4 x float> [[TMP1_SROA_0_0_VECBLEND]], <4 x float> poison, <3 x i32> <i32 0, i32 1, i32 2>
 ; CHECK-NEXT:    store <3 x float> [[TMP1_SROA_0_0_VEC_EXTRACT]], <3 x float>* [[TMP1_SROA_0_0_TMP1_SROA_0_0__SROA_CAST2_SROA_CAST]], align 4
 ; CHECK-NEXT:    [[RESULT:%.*]] = call i32 @memcpy_vec3float_helper(%S.vec3float* [[TMP2]])
 ; CHECK-NEXT:    ret i32 [[RESULT]]
 ;
 entry:

llvm/test/Transforms/SROA/vector-promotion.ll

; PR13254
   %addr = getelementptr inbounds { <4 x i64>, <4 x i64> }, { <4 x i64>, <4 x i64> }* %tmp, i32 0, i32 0, i64 %n
   %res = load i64, i64* %addr, align 4
   ret i64 %res
 }
 
 define <4 x i32> @test_subvec_store() {
 ; CHECK-LABEL: @test_subvec_store(
 ; CHECK-NEXT:  entry:
-; CHECK-NEXT:    [[A_0_VECBLEND:%.*]] = select <4 x i1> <i1 true, i1 true, i1 false, i1 false>, <4 x i32> <i32 0, i32 0, i32 undef, i32 undef>, <4 x i32> undef
+; CHECK-NEXT:    [[A_0_VECBLEND:%.*]] = select <4 x i1> <i1 true, i1 true, i1 false, i1 false>, <4 x i32> <i32 0, i32 0, i32 undef, i32 undef>, <4 x i32> poison
 ; CHECK-NEXT:    [[A_4_VECBLEND:%.*]] = select <4 x i1> <i1 false, i1 true, i1 true, i1 false>, <4 x i32> <i32 undef, i32 1, i32 1, i32 undef>, <4 x i32> [[A_0_VECBLEND]]
 ; CHECK-NEXT:    [[A_8_VECBLEND:%.*]] = select <4 x i1> <i1 false, i1 false, i1 true, i1 true>, <4 x i32> <i32 undef, i32 undef, i32 2, i32 2>, <4 x i32> [[A_4_VECBLEND]]
 ; CHECK-NEXT:    [[A_12_VEC_INSERT:%.*]] = insertelement <4 x i32> [[A_8_VECBLEND]], i32 3, i32 3
 ; CHECK-NEXT:    ret <4 x i32> [[A_12_VEC_INSERT]]
 ;
 entry:
   %a = alloca <4 x i32>
 
entry:
   ret <4 x i32> %ret
 }
 
 declare void @llvm.memset.p0i32.i32(i32* nocapture, i32, i32, i1) nounwind
 
 define <4 x float> @test_subvec_memset() {
 ; CHECK-LABEL: @test_subvec_memset(
 ; CHECK-NEXT:  entry:
-; CHECK-NEXT:    [[A_0_VECBLEND:%.*]] = select <4 x i1> <i1 true, i1 true, i1 false, i1 false>, <4 x float> <float 0.000000e+00, float 0.000000e+00, float undef, float undef>, <4 x float> undef
+; CHECK-NEXT:    [[A_0_VECBLEND:%.*]] = select <4 x i1> <i1 true, i1 true, i1 false, i1 false>, <4 x float> <float 0.000000e+00, float 0.000000e+00, float undef, float undef>, <4 x float> poison
 ; CHECK-NEXT:    [[A_4_VECBLEND:%.*]] = select <4 x i1> <i1 false, i1 true, i1 true, i1 false>, <4 x float> <float undef, float 0x3820202020000000, float 0x3820202020000000, float undef>, <4 x float> [[A_0_VECBLEND]]
 ; CHECK-NEXT:    [[A_8_VECBLEND:%.*]] = select <4 x i1> <i1 false, i1 false, i1 true, i1 true>, <4 x float> <float undef, float undef, float 0x3860606060000000, float 0x3860606060000000>, <4 x float> [[A_4_VECBLEND]]
 ; CHECK-NEXT:    [[A_12_VEC_INSERT:%.*]] = insertelement <4 x float> [[A_8_VECBLEND]], float 0x38E0E0E0E0000000, i32 3
 ; CHECK-NEXT:    ret <4 x float> [[A_12_VEC_INSERT]]
 ;
 entry:
   %a = alloca <4 x float>
 

 }
 
 define <4 x float> @test_subvec_memcpy(i8* %x, i8* %y, i8* %z, i8* %f, i8* %out) {
 ; CHECK-LABEL: @test_subvec_memcpy(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[A_0_X_SROA_CAST:%.*]] = bitcast i8* [[X:%.*]] to <2 x float>*
 ; CHECK-NEXT:    [[A_0_COPYLOAD:%.*]] = load <2 x float>, <2 x float>* [[A_0_X_SROA_CAST]], align 1
 ; CHECK-NEXT:    [[A_0_VEC_EXPAND:%.*]] = shufflevector <2 x float> [[A_0_COPYLOAD]], <2 x float> poison, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
-; CHECK-NEXT:    [[A_0_VECBLEND:%.*]] = select <4 x i1> <i1 true, i1 true, i1 false, i1 false>, <4 x float> [[A_0_VEC_EXPAND]], <4 x float> undef
+; CHECK-NEXT:    [[A_0_VECBLEND:%.*]] = select <4 x i1> <i1 true, i1 true, i1 false, i1 false>, <4 x float> [[A_0_VEC_EXPAND]], <4 x float> poison
 ; CHECK-NEXT:    [[A_4_Y_SROA_CAST:%.*]] = bitcast i8* [[Y:%.*]] to <2 x float>*
 ; CHECK-NEXT:    [[A_4_COPYLOAD:%.*]] = load <2 x float>, <2 x float>* [[A_4_Y_SROA_CAST]], align 1
 ; CHECK-NEXT:    [[A_4_VEC_EXPAND:%.*]] = shufflevector <2 x float> [[A_4_COPYLOAD]], <2 x float> poison, <4 x i32> <i32 undef, i32 0, i32 1, i32 undef>
 ; CHECK-NEXT:    [[A_4_VECBLEND:%.*]] = select <4 x i1> <i1 false, i1 true, i1 true, i1 false>, <4 x float> [[A_4_VEC_EXPAND]], <4 x float> [[A_0_VECBLEND]]
 ; CHECK-NEXT:    [[A_8_Z_SROA_CAST:%.*]] = bitcast i8* [[Z:%.*]] to <2 x float>*
 ; CHECK-NEXT:    [[A_8_COPYLOAD:%.*]] = load <2 x float>, <2 x float>* [[A_8_Z_SROA_CAST]], align 1
 ; CHECK-NEXT:    [[A_8_VEC_EXPAND:%.*]] = shufflevector <2 x float> [[A_8_COPYLOAD]], <2 x float> poison, <4 x i32> <i32 undef, i32 undef, i32 0, i32 1>
 ; CHECK-NEXT:    [[A_8_VECBLEND:%.*]] = select <4 x i1> <i1 false, i1 false, i1 true, i1 true>, <4 x float> [[A_8_VEC_EXPAND]], <4 x float> [[A_4_VECBLEND]]
entry:
 
   ret <4 x float> %ret
 }
 
 define i32 @PR14212() {
 ; CHECK-LABEL: @PR14212(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[TMP0:%.*]] = bitcast <3 x i8> undef to i24
-; CHECK-NEXT:    [[RETVAL_SROA_2_0_INSERT_EXT:%.*]] = zext i8 undef to i32
+; CHECK-NEXT:    [[RETVAL_SROA_2_0_INSERT_EXT:%.*]] = zext i8 poison to i32
 ; CHECK-NEXT:    [[RETVAL_SROA_2_0_INSERT_SHIFT:%.*]] = shl i32 [[RETVAL_SROA_2_0_INSERT_EXT]], 24
 ; CHECK-NEXT:    [[RETVAL_SROA_2_0_INSERT_MASK:%.*]] = and i32 undef, 16777215
 ; CHECK-NEXT:    [[RETVAL_SROA_2_0_INSERT_INSERT:%.*]] = or i32 [[RETVAL_SROA_2_0_INSERT_MASK]], [[RETVAL_SROA_2_0_INSERT_SHIFT]]
 ; CHECK-NEXT:    [[RETVAL_0_INSERT_EXT:%.*]] = zext i24 [[TMP0]] to i32
 ; CHECK-NEXT:    [[RETVAL_0_INSERT_MASK:%.*]] = and i32 [[RETVAL_SROA_2_0_INSERT_INSERT]], -16777216
 ; CHECK-NEXT:    [[RETVAL_0_INSERT_INSERT:%.*]] = or i32 [[RETVAL_0_INSERT_MASK]], [[RETVAL_0_INSERT_EXT]]
 ; CHECK-NEXT:    ret i32 [[RETVAL_0_INSERT_INSERT]]
 ;
entry:
 
   ret <2 x i8> %vec
 }
 
 define i32 @PR14349.2(<2 x i8> %x) {
 ; CHECK-LABEL: @PR14349.2(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[TMP0:%.*]] = bitcast <2 x i8> [[X:%.*]] to i16
-; CHECK-NEXT:    [[A_SROA_2_0_INSERT_EXT:%.*]] = zext i16 undef to i32
+; CHECK-NEXT:    [[A_SROA_2_0_INSERT_EXT:%.*]] = zext i16 poison to i32
 ; CHECK-NEXT:    [[A_SROA_2_0_INSERT_SHIFT:%.*]] = shl i32 [[A_SROA_2_0_INSERT_EXT]], 16
 ; CHECK-NEXT:    [[A_SROA_2_0_INSERT_MASK:%.*]] = and i32 undef, 65535
 ; CHECK-NEXT:    [[A_SROA_2_0_INSERT_INSERT:%.*]] = or i32 [[A_SROA_2_0_INSERT_MASK]], [[A_SROA_2_0_INSERT_SHIFT]]
 ; CHECK-NEXT:    [[A_SROA_0_0_INSERT_EXT:%.*]] = zext i16 [[TMP0]] to i32
 ; CHECK-NEXT:    [[A_SROA_0_0_INSERT_MASK:%.*]] = and i32 [[A_SROA_2_0_INSERT_INSERT]], -65536
 ; CHECK-NEXT:    [[A_SROA_0_0_INSERT_INSERT:%.*]] = or i32 [[A_SROA_0_0_INSERT_MASK]], [[A_SROA_0_0_INSERT_EXT]]
 ; CHECK-NEXT:    ret i32 [[A_SROA_0_0_INSERT_INSERT]]
 ;
entry:
   ret i32 %tmp4
 }
 
 define <2 x i32> @test9(i32 %x, i32 %y) {
 ; Ensure that we can promote an alloca that doesn't mention a vector type based
 ; on a single load with a vector type.
 ; CHECK-LABEL: @test9(
 ; CHECK-NEXT:  entry:
-; CHECK-NEXT:    [[A_SROA_0_0_VEC_INSERT:%.*]] = insertelement <2 x i32> undef, i32 [[X:%.*]], i32 0
+; CHECK-NEXT:    [[A_SROA_0_0_VEC_INSERT:%.*]] = insertelement <2 x i32> poison, i32 [[X:%.*]], i32 0
 ; CHECK-NEXT:    [[A_SROA_0_4_VEC_INSERT:%.*]] = insertelement <2 x i32> [[A_SROA_0_0_VEC_INSERT]], i32 [[Y:%.*]], i32 1
 ; CHECK-NEXT:    ret <2 x i32> [[A_SROA_0_4_VEC_INSERT]]
 ;
 entry:
   %a = alloca i64
   %a.vec = bitcast i64* %a to <2 x i32>*
   %a.i32 = bitcast i64* %a to i32*