[NFCI-ish][SimplifyCFGPass] Rework and generalize `ret` block tail-merging

[lebedev.ri]

Summary

This changes the approach taken to tail-merge the blocks
to always create a new block instead of trying to reuse some block,
and generalizes it to support dealing not with just the ret in the future.

This effectively lifts the CallBr restriction, although this isn't really intentional.
That is the only non-NFC change here, i'm not sure if it's reasonable/feasible to temporarily retain it.

Other restrictions of the transform remain.

[lebedev.ri]

Split off addresstaken fixes.

[rnk]

llvm/lib/Transforms/Scalar/SimplifyCFGPass.cpp

106

Oh boy, that's fun. This is the first I've learned of this verifier requirement. In the future, maybe there could be a way to generalize looking for musttail and looking for this intrinsic. I don't see a good way right now.

117–118

See, tokens are totally straightforward compared to the deoptimize intrinsic. All the features that I've helped design are totally clear and straightforward. =P Or, at least I've tried to do my best, anyway.

128–132

Can this be Term->getPrevNonDebugInstruction?

149

Maybe Phis is a better name?

180

In the end, the new instructions should carry the merged source location from the original instructions. You probably want to use DILocation::getMergedLocations for that. This is also worth testing.

[lebedev.ri]

@rkn thank you for taking a look!

llvm/lib/Transforms/Scalar/SimplifyCFGPass.cpp

106

Yep, this is super mismodelled.
@llvm.experimental_deoptimize should simply implicitly be musttail,
and then everything would just work.

[lebedev.ri]

Hopefully address review notes.

llvm/lib/Transforms/Scalar/SimplifyCFGPass.cpp

128–132

I'd rather not change existing code just because we can, this code goes away in the very next patch.

149

How about NewOps?

[lebedev.ri]

Move code out of the loop since it looks cleaner that way.

[rnk]

lgtm

llvm/lib/Transforms/Scalar/SimplifyCFGPass.cpp

128–132

Sounds good

[lebedev.ri]

In D104598#2834692, @rnk wrote:

lgtm

Thank you for the review!

llvm/lib/Transforms/Scalar/SimplifyCFGPass.cpp

 //   * Eliminates PHI nodes for basic blocks with a single predecessor.
 //   * Eliminates a basic block that only contains an unconditional branch.
 //   * Changes invoke instructions to nounwind functions to be calls.
 //   * Change things like "if (x) if (y)" into "if (x&y)".
 //   * etc..
 //
 //===----------------------------------------------------------------------===//
 
+#include "llvm/ADT/MapVector.h"
 #include "llvm/ADT/SmallPtrSet.h"
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/ADT/Statistic.h"
 #include "llvm/Analysis/AssumptionCache.h"
 #include "llvm/Analysis/CFG.h"
 #include "llvm/Analysis/DomTreeUpdater.h"
 #include "llvm/Analysis/GlobalsModRef.h"
 #include "llvm/Analysis/TargetTransformInfo.h"

 
 static cl::opt<bool> UserSinkCommonInsts(
     "sink-common-insts", cl::Hidden, cl::init(false),
     cl::desc("Sink common instructions (default = false)"));
 
 
 STATISTIC(NumSimpl, "Number of blocks simplified");
 
-/// If we have more than one empty (other than phi node) return blocks,
-/// merge them together to promote recursive block merging.
-static bool mergeEmptyReturnBlocks(Function &F, DomTreeUpdater *DTU) {
-  bool Changed = false;
+static bool tailMergeBlocksWithSimilarFunctionTerminators(Function &F,
+                                                          DomTreeUpdater *DTU) {
+  SmallMapVector<unsigned /*TerminatorOpcode*/, SmallVector<BasicBlock *, 2>, 4>
+      Structure;
 
-  std::vector<DominatorTree::UpdateType> Updates;
-  SmallVector<BasicBlock *, 8> DeadBlocks;
+  // Scan all the blocks in the function, record the interesting-ones.
+  for (BasicBlock &BB : F) {
+    if (DTU && DTU->isBBPendingDeletion(&BB))
+      continue;
 
-  BasicBlock *RetBlock = nullptr;
+    // We are only interested in function-terminating blocks.
+    if (!succ_empty(&BB))
+      continue;
 
-  // Scan all the blocks in the function, looking for empty return blocks.
-  for (BasicBlock &BB : make_early_inc_range(F)) {
-    if (DTU && DTU->isBBPendingDeletion(&BB))
+    auto *Term = BB.getTerminator();
+
+    // Fow now only support `ret` function terminators.
+    // FIXME: lift this restriction.
+    if (Term->getOpcode() != Instruction::Ret)
       continue;
 
-    // Only look at return blocks.
-    ReturnInst *Ret = dyn_cast<ReturnInst>(BB.getTerminator());
-    if (!Ret) continue;
+    // We can't tail-merge block that contains a musttail call.
+    if (BB.getTerminatingMustTailCall())
+      continue;
+
+    // Calls to experimental_deoptimize must be followed by a return
+    // of the value computed by experimental_deoptimize.
+    // I.e., we can not change `ret` to `br` for this block.
+    if (auto *CI =
+            dyn_cast_or_null<CallInst>(Term->getPrevNonDebugInstruction())) {
+      if (Function *F = CI->getCalledFunction())
+        if (Intrinsic::ID ID = F->getIntrinsicID())
+          if (ID == Intrinsic::experimental_deoptimize)
+            continue;
+    }
+
+    // PHI nodes cannot have token type, so if the terminator has an operand
+    // with token type, we can not tail-merge this kind of function terminators.
+    if (any_of(Term->operands(),
+               [](Value *Op) { return Op->getType()->isTokenTy(); }))
+      continue;
 
     // Only look at the block if it is empty or the only other thing in it is a
     // single PHI node that is the operand to the return.
-    if (Ret != &BB.front()) {
+    // FIXME: lift this restriction.
+    if (Term != &BB.front()) {
       // Check for something else in the block.
-      BasicBlock::iterator I(Ret);
+      BasicBlock::iterator I(Term);
       --I;
       // Skip over debug info.
       while (isa<DbgInfoIntrinsic>(I) && I != BB.begin())
         --I;
       if (!isa<DbgInfoIntrinsic>(I) &&
-          (!isa<PHINode>(I) || I != BB.begin() || Ret->getNumOperands() == 0 ||
-           Ret->getOperand(0) != &*I))
+          (!isa<PHINode>(I) || I != BB.begin() || Term->getNumOperands() == 0 ||
+           Term->getOperand(0) != &*I))
         continue;
     }
 
-    // If this is the first returning block, remember it and keep going.
-    if (!RetBlock) {
-      RetBlock = &BB;
-      continue;
-    }
+    // Canonical blocks are uniqued based on the terminator type (opcode).
+    Structure[Term->getOpcode()].emplace_back(&BB);
 
-    // Skip merging if this would result in a CallBr instruction with a
-    // duplicate destination. FIXME: See note in CodeGenPrepare.cpp.
-    bool SkipCallBr = false;
-    for (pred_iterator PI = pred_begin(&BB), E = pred_end(&BB);
-         PI != E && !SkipCallBr; ++PI) {
-      if (auto *CBI = dyn_cast<CallBrInst>((*PI)->getTerminator()))
-        for (unsigned i = 0, e = CBI->getNumSuccessors(); i != e; ++i)
-          if (RetBlock == CBI->getSuccessor(i)) {
-            SkipCallBr = true;
-            break;
-          }
-    }
-    if (SkipCallBr)
+  bool Changed = false;
+
+  std::vector<DominatorTree::UpdateType> Updates;
+
+  for (ArrayRef<BasicBlock *> BBs : make_second_range(Structure)) {
+    SmallVector<PHINode *, 1> NewOps;
+
+    // We don't want to change IR just because we can.
+    // Only do that if there are at least two blocks we'll tail-merge.
+    if (BBs.size() < 2)
       continue;
 
-    // Otherwise, we found a duplicate return block.  Merge the two.
     Changed = true;
 
-    // Case when there is no input to the return or when the returned values
-    // agree is trivial.  Note that they can't agree if there are phis in the
-    // blocks.
-    if (Ret->getNumOperands() == 0 ||
-        Ret->getOperand(0) ==
-          cast<ReturnInst>(RetBlock->getTerminator())->getOperand(0)) {
-      // All predecessors of BB should now branch to RetBlock instead.
-      if (DTU) {
-        SmallPtrSet<BasicBlock *, 2> PredsOfBB(pred_begin(&BB), pred_end(&BB));
-        SmallPtrSet<BasicBlock *, 2> PredsOfRetBlock(pred_begin(RetBlock),
-                                                     pred_end(RetBlock));
-        Updates.reserve(Updates.size() + 2 * PredsOfBB.size());
-        for (auto *Predecessor : PredsOfBB)
-          // But, iff Predecessor already branches to RetBlock,
-          // don't (re-)add DomTree edge, because it already exists.
-          if (!PredsOfRetBlock.contains(Predecessor))
-            Updates.push_back({DominatorTree::Insert, Predecessor, RetBlock});
-        for (auto *Predecessor : PredsOfBB)
-          Updates.push_back({DominatorTree::Delete, Predecessor, &BB});
-      }
-      BB.replaceAllUsesWith(RetBlock);
-      DeadBlocks.emplace_back(&BB);
-      continue;
-    }
+    if (DTU)
+      Updates.reserve(Updates.size() + BBs.size());
 
-    // If the canonical return block has no PHI node, create one now.
-    PHINode *RetBlockPHI = dyn_cast<PHINode>(RetBlock->begin());
-    if (!RetBlockPHI) {
-      Value *InVal = cast<ReturnInst>(RetBlock->getTerminator())->getOperand(0);
-      pred_iterator PB = pred_begin(RetBlock), PE = pred_end(RetBlock);
-      RetBlockPHI = PHINode::Create(Ret->getOperand(0)->getType(),
-                                    std::distance(PB, PE), "merge",
-                                    &RetBlock->front());
-
-      for (pred_iterator PI = PB; PI != PE; ++PI)
-        RetBlockPHI->addIncoming(InVal, *PI);
-      RetBlock->getTerminator()->setOperand(0, RetBlockPHI);
-    }
-
-    // Turn BB into a block that just unconditionally branches to the return
-    // block.  This handles the case when the two return blocks have a common
-    // predecessor but that return different things.
-    RetBlockPHI->addIncoming(Ret->getOperand(0), &BB);
-    BB.getTerminator()->eraseFromParent();
-    BranchInst::Create(RetBlock, &BB);
+    BasicBlock *CanonicalBB;
+    Instruction *CanonicalTerm;
+    {
+      auto *Term = BBs[0]->getTerminator();
+
+      // Create a canonical block for this function terminator type now,
+      // placing it *before* the first block that will branch to it.
+      CanonicalBB = BasicBlock::Create(
+          F.getContext(), Twine("common.") + Term->getOpcodeName(), &F, BBs[0]);
+      // We'll also need a PHI node per each operand of the terminator.
+      NewOps.resize(Term->getNumOperands());
+      for (auto I : zip(Term->operands(), NewOps)) {
+        std::get<1>(I) = PHINode::Create(std::get<0>(I)->getType(),
+                                         /*NumReservedValues=*/BBs.size(),
+                                         CanonicalBB->getName() + ".op");
+        CanonicalBB->getInstList().push_back(std::get<1>(I));
+      }
+      // Make it so that this canonical block actually has the right
+      // terminator.
+      CanonicalTerm = Term->clone();
+      CanonicalBB->getInstList().push_back(CanonicalTerm);
+      // If the canonical terminator has operands, rewrite it to take PHI's.
+      for (auto I : zip(NewOps, CanonicalTerm->operands()))
+        std::get<1>(I) = std::get<0>(I);
+    }
+
+    // Now, go through each block (with the current terminator type)
+    // we've recorded, and rewrite it to branch to the new common block.
+    const DILocation *CommonDebugLoc = nullptr;
+    for (BasicBlock *BB : BBs) {
+      auto *Term = BB->getTerminator();
+
+      // Aha, found a new non-canonical function terminator. If it has operands,
+      // forward them to the PHI nodes in the canonical block.
+      for (auto I : zip(Term->operands(), NewOps))
+        std::get<1>(I)->addIncoming(std::get<0>(I), BB);
+
+      // Compute the debug location common to all the original terminators.
+      if (!CommonDebugLoc)
+        CommonDebugLoc = Term->getDebugLoc();
+      else
+        CommonDebugLoc =
+            DILocation::getMergedLocation(CommonDebugLoc, Term->getDebugLoc());
+
+      // And turn BB into a block that just unconditionally branches
+      // to the canonical block.
+      Term->eraseFromParent();
+      BranchInst::Create(CanonicalBB, BB);
       if (DTU)
-      Updates.push_back({DominatorTree::Insert, &BB, RetBlock});
+        Updates.push_back({DominatorTree::Insert, BB, CanonicalBB});
+    }
+
+    CanonicalTerm->setDebugLoc(CommonDebugLoc);
   }
 
   if (DTU)
     DTU->applyUpdates(Updates);
 
-  DeleteDeadBlocks(DeadBlocks, DTU);
-
   return Changed;
 }
 
 /// Call SimplifyCFG on all the blocks in the function,
 /// iterating until no more changes are made.
 static bool iterativelySimplifyCFG(Function &F, const TargetTransformInfo &TTI,
                                    DomTreeUpdater *DTU,
                                    const SimplifyCFGOptions &Options) {

 }
 
 static bool simplifyFunctionCFGImpl(Function &F, const TargetTransformInfo &TTI,
                                     DominatorTree *DT,
                                     const SimplifyCFGOptions &Options) {
   DomTreeUpdater DTU(DT, DomTreeUpdater::UpdateStrategy::Eager);
 
   bool EverChanged = removeUnreachableBlocks(F, DT ? &DTU : nullptr);
-  EverChanged |= mergeEmptyReturnBlocks(F, DT ? &DTU : nullptr);
+  EverChanged |=
+      tailMergeBlocksWithSimilarFunctionTerminators(F, DT ? &DTU : nullptr);
   EverChanged |= iterativelySimplifyCFG(F, TTI, DT ? &DTU : nullptr, Options);
 
   // If neither pass changed anything, we're done.
   if (!EverChanged) return false;
 
   // iterativelySimplifyCFG can (rarely) make some loops dead.  If this happens,
   // removeUnreachableBlocks is needed to nuke them, which means we should
   // iterate between the two optimizations.  We structure the code like this to

llvm/test/CodeGen/ARM/speculation-hardening-sls.ll

 return:                                           ; preds = %entry, %l2
   %retval.0 = phi i32 [ 1, %l2 ], [ 0, %entry ]
   ret i32 %retval.0
 }
 
 define i32 @asmgoto() {
 ; NOHARDENARM-LABEL: asmgoto:
 ; NOHARDENARM:       @ %bb.0: @ %entry
+; NOHARDENARM-NEXT:    mov r0, #0
 ; NOHARDENARM-NEXT:    @APP
 ; NOHARDENARM-NEXT:    b .Ltmp2
 ; NOHARDENARM-NEXT:    @NO_APP
-; NOHARDENARM-NEXT:  @ %bb.1: @ %asm.fallthrough
-; NOHARDENARM-NEXT:    mov r0, #0
+; NOHARDENARM-NEXT:  @ %bb.1: @ %common.ret
 ; NOHARDENARM-NEXT:    bx lr
 ; NOHARDENARM-NEXT:  .Ltmp2: @ Block address taken
 ; NOHARDENARM-NEXT:  .LBB2_2: @ %d
 ; NOHARDENARM-NEXT:    mov r0, #1
 ; NOHARDENARM-NEXT:    bx lr
 ;
 ; NOHARDENTHUMB-LABEL: asmgoto:
 ; NOHARDENTHUMB:       @ %bb.0: @ %entry
 ; NOHARDENTHUMB-NEXT:    @APP
 ; NOHARDENTHUMB-NEXT:    b .Ltmp2
 ; NOHARDENTHUMB-NEXT:    @NO_APP
-; NOHARDENTHUMB-NEXT:  @ %bb.1: @ %asm.fallthrough
+; NOHARDENTHUMB-NEXT:  @ %bb.1:
 ; NOHARDENTHUMB-NEXT:    movs r0, #0
 ; NOHARDENTHUMB-NEXT:    bx lr
 ; NOHARDENTHUMB-NEXT:  .Ltmp2: @ Block address taken
 ; NOHARDENTHUMB-NEXT:  .LBB2_2: @ %d
 ; NOHARDENTHUMB-NEXT:    movs r0, #1
 ; NOHARDENTHUMB-NEXT:    bx lr
 entry:
   callbr void asm sideeffect "B $0", "X"(i8* blockaddress(@asmgoto, %d))

llvm/test/Transforms/LoopUnroll/ARM/upperbound.ll

 
 ; Larger test that is still fully unrolled, thanks in part to the constant data and the max upper bound.
 @data = internal constant [50 x i32] [i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31, i32 32, i32 33, i32 34, i32 35, i32 36, i32 37, i32 38, i32 39, i32 40, i32 41, i32 42, i32 43, i32 44, i32 45, i32 46, i32 47, i32 48, i32 49, i32 50], align 4
 define i32 @test2(i32 %l86) {
 ; CHECK-LABEL: @test2(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[L86_OFF:%.*]] = add i32 [[L86:%.*]], -1
 ; CHECK-NEXT:    [[SWITCH:%.*]] = icmp ult i32 [[L86_OFF]], 24
-; CHECK-NEXT:    br i1 [[SWITCH]], label [[FOR_END_I_IF_END8_I_CRIT_EDGE_I:%.*]], label [[FOR_INC_I_3_I_5:%.*]]
-; CHECK:       for.end.i.if.end8.i_crit_edge.i:
+; CHECK-NEXT:    br i1 [[SWITCH]], label [[COMMON_RET:%.*]], label [[FOR_INC_I_3_I_5:%.*]]
+; CHECK:       common.ret:
 ; CHECK-NEXT:    ret i32 0
 ; CHECK:       for.inc.i.3.i.5:
 ; CHECK-NEXT:    [[DOTNOT30:%.*]] = icmp ne i32 [[L86]], 25
 ; CHECK-NEXT:    [[SPEC_SELECT24:%.*]] = zext i1 [[DOTNOT30]] to i32
 ; CHECK-NEXT:    ret i32 [[SPEC_SELECT24]]
 ;
 entry:
   br label %for.body.i.i

llvm/test/Transforms/SimplifyCFG/2003-08-17-FoldSwitch.ll

Start:          ; preds = %0
   ]
 TheDest:
   ret i32 1234
 }
 
 ; Test folding switch -> branch
 define i32 @test4(i32 %C) {
 ; CHECK-LABEL: @test4(
-; CHECK-NEXT:  L1:
+; CHECK-NEXT:  common.ret:
 ; CHECK-NEXT:    [[COND:%.*]] = icmp eq i32 [[C:%.*]], 0
-; CHECK-NEXT:    [[SPEC_SELECT:%.*]] = select i1 [[COND]], i32 1, i32 0
-; CHECK-NEXT:    ret i32 [[SPEC_SELECT]]
+; CHECK-NEXT:    [[DOT:%.*]] = select i1 [[COND]], i32 1, i32 0
+; CHECK-NEXT:    ret i32 [[DOT]]
 ;
   switch i32 %C, label %L1 [
   i32 0, label %L2
   ]
 L1:
   ret i32 0
 L2:
   ret i32 1
 }
 
 ; Can fold into a cond branch!
 define i32 @test5(i32 %C) {
 ; CHECK-LABEL: @test5(
-; CHECK-NEXT:  L1:
+; CHECK-NEXT:  common.ret:
 ; CHECK-NEXT:    [[COND:%.*]] = icmp eq i32 [[C:%.*]], 0
-; CHECK-NEXT:    [[SPEC_SELECT:%.*]] = select i1 [[COND]], i32 1, i32 0
-; CHECK-NEXT:    ret i32 [[SPEC_SELECT]]
+; CHECK-NEXT:    [[DOT:%.*]] = select i1 [[COND]], i32 1, i32 0
+; CHECK-NEXT:    ret i32 [[DOT]]
 ;
   switch i32 %C, label %L1 [
   i32 0, label %L2
   i32 123, label %L1
   ]
 L1:
   ret i32 0
 L2:
   ret i32 1
 }
 

llvm/test/Transforms/SimplifyCFG/ConditionalTrappingConstantExpr.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt < %s -simplifycfg -simplifycfg-require-and-preserve-domtree=1 -S | FileCheck %s
 
 @G = extern_weak global i32
 
 ; PR3354
 ; Do not merge bb1 into the entry block, it might trap.
 
 define i32 @admiral(i32 %a, i32 %b) {
 ; CHECK-LABEL: @admiral(
 ; CHECK-NEXT:    [[C:%.*]] = icmp sle i32 [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT:    br i1 [[C]], label [[BB2:%.*]], label [[BB1:%.*]]
+; CHECK-NEXT:    br i1 [[C]], label [[COMMON_RET:%.*]], label [[BB1:%.*]]
 ; CHECK:       bb1:
 ; CHECK-NEXT:    [[D:%.*]] = icmp sgt i32 sdiv (i32 -32768, i32 ptrtoint (i32* @G to i32)), 0
 ; CHECK-NEXT:    [[SPEC_SELECT:%.*]] = select i1 [[D]], i32 927, i32 42
-; CHECK-NEXT:    br label [[BB2]]
-; CHECK:       bb2:
-; CHECK-NEXT:    [[MERGE:%.*]] = phi i32 [ 42, [[TMP0:%.*]] ], [ [[SPEC_SELECT]], [[BB1]] ]
-; CHECK-NEXT:    ret i32 [[MERGE]]
+; CHECK-NEXT:    br label [[COMMON_RET]]
+; CHECK:       common.ret:
+; CHECK-NEXT:    [[COMMON_RET_OP:%.*]] = phi i32 [ 42, [[TMP0:%.*]] ], [ [[SPEC_SELECT]], [[BB1]] ]
+; CHECK-NEXT:    ret i32 [[COMMON_RET_OP]]
 ;
   %c = icmp sle i32 %a, %b
   br i1 %c, label %bb2, label %bb1
 bb1:
   %d = icmp sgt i32 sdiv (i32 -32768, i32 ptrtoint (i32* @G to i32)), 0
   br i1 %d, label %bb6, label %bb2
 bb2:
   ret i32 42
 bb6:
   ret i32 927
 }
 
 define i32 @ackbar(i1 %c) {
 ; CHECK-LABEL: @ackbar(
-; CHECK-NEXT:    br i1 [[C:%.*]], label [[BB5:%.*]], label [[BB6:%.*]]
+; CHECK-NEXT:    br i1 [[C:%.*]], label [[BB5:%.*]], label [[COMMON_RET:%.*]]
 ; CHECK:       bb5:
 ; CHECK-NEXT:    [[SPEC_SELECT:%.*]] = select i1 icmp sgt (i32 sdiv (i32 32767, i32 ptrtoint (i32* @G to i32)), i32 0), i32 42, i32 927
-; CHECK-NEXT:    br label [[BB6]]
-; CHECK:       bb6:
-; CHECK-NEXT:    [[MERGE:%.*]] = phi i32 [ 42, [[TMP0:%.*]] ], [ [[SPEC_SELECT]], [[BB5]] ]
-; CHECK-NEXT:    ret i32 [[MERGE]]
+; CHECK-NEXT:    br label [[COMMON_RET]]
+; CHECK:       common.ret:
+; CHECK-NEXT:    [[COMMON_RET_OP:%.*]] = phi i32 [ 42, [[TMP0:%.*]] ], [ [[SPEC_SELECT]], [[BB5]] ]
+; CHECK-NEXT:    ret i32 [[COMMON_RET_OP]]
 ;
   br i1 %c, label %bb5, label %bb6
 bb5:
   br i1 icmp sgt (i32 sdiv (i32 32767, i32 ptrtoint (i32* @G to i32)), i32 0), label %bb6, label %bb7
 bb6:
   ret i32 42
 bb7:
   ret i32 927
 }
 
 ; FP ops don't trap by default, so this is safe to hoist.
 
 define i32 @tarp(i1 %c) {
 ; CHECK-LABEL: @tarp(
-; CHECK-NEXT:  bb9:
-; CHECK-NEXT:    [[SPEC_SELECT:%.*]] = select i1 fcmp oeq (float fdiv (float 3.000000e+00, float sitofp (i32 ptrtoint (i32* @G to i32) to float)), float 1.000000e+00), i32 42, i32 927
-; CHECK-NEXT:    [[MERGE:%.*]] = select i1 [[C:%.*]], i32 [[SPEC_SELECT]], i32 42
-; CHECK-NEXT:    ret i32 [[MERGE]]
+; CHECK-NEXT:  common.ret:
+; CHECK-NEXT:    [[C_NOT:%.*]] = xor i1 [[C:%.*]], true
+; CHECK-NEXT:    [[BRMERGE:%.*]] = or i1 [[C_NOT]], fcmp oeq (float fdiv (float 3.000000e+00, float sitofp (i32 ptrtoint (i32* @G to i32) to float)), float 1.000000e+00)
+; CHECK-NEXT:    [[COMMON_RET_OP:%.*]] = select i1 [[BRMERGE]], i32 42, i32 927
+; CHECK-NEXT:    ret i32 [[COMMON_RET_OP]]
 ;
   br i1 %c, label %bb8, label %bb9
 bb8:
   br i1 fcmp oeq (float fdiv (float 3.0, float sitofp (i32 ptrtoint (i32* @G to i32) to float)), float 1.0), label %bb9, label %bb10
 bb9:
   ret i32 42
 bb10:
   ret i32 927
 }

llvm/test/Transforms/SimplifyCFG/FoldValueComparisonIntoPredecessors-domtree-preservation-edgecase.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt -S -simplifycfg -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck %s
 
 define dso_local i32 @readCBPandCoeffsFromNAL(i1 %c, i32 %x, i32 %y) local_unnamed_addr {
 ; CHECK-LABEL: @readCBPandCoeffsFromNAL(
 ; CHECK-NEXT:  if.end:
-; CHECK-NEXT:    br i1 [[C:%.*]], label [[IF_END80:%.*]], label [[IF_THEN64:%.*]]
-; CHECK:       if.then64:
-; CHECK-NEXT:    [[MERGE:%.*]] = phi i32 [ [[Y:%.*]], [[IF_END:%.*]] ], [ 1, [[IF_END172237:%.*]] ], [ 0, [[IF_END80]] ], [ 0, [[IF_END80]] ]
-; CHECK-NEXT:    ret i32 [[MERGE]]
+; CHECK-NEXT:    br i1 [[C:%.*]], label [[IF_END80:%.*]], label [[COMMON_RET:%.*]]
+; CHECK:       common.ret:
+; CHECK-NEXT:    [[COMMON_RET_OP:%.*]] = phi i32 [ [[Y:%.*]], [[IF_END:%.*]] ], [ 1, [[IF_END172237:%.*]] ], [ 0, [[IF_END80]] ], [ 0, [[IF_END80]] ]
+; CHECK-NEXT:    ret i32 [[COMMON_RET_OP]]
 ; CHECK:       if.end80:
 ; CHECK-NEXT:    switch i32 [[X:%.*]], label [[INFLOOP:%.*]] [
 ; CHECK-NEXT:    i32 10, label [[IF_END172237]]
 ; CHECK-NEXT:    i32 14, label [[IF_END172237]]
-; CHECK-NEXT:    i32 9, label [[IF_THEN64]]
-; CHECK-NEXT:    i32 12, label [[IF_THEN64]]
+; CHECK-NEXT:    i32 9, label [[COMMON_RET]]
+; CHECK-NEXT:    i32 12, label [[COMMON_RET]]
 ; CHECK-NEXT:    ]
 ; CHECK:       if.end172237:
-; CHECK-NEXT:    br label [[IF_THEN64]]
+; CHECK-NEXT:    br label [[COMMON_RET]]
 ; CHECK:       infloop:
 ; CHECK-NEXT:    br label [[INFLOOP]]
 ;
 if.end:
   br i1 %c, label %if.end80, label %if.then64
 
 if.then64:                                        ; preds = %if.end
   ret i32 %y

llvm/test/Transforms/SimplifyCFG/FoldValueComparisonIntoPredecessors-no-new-successors.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt -S -simplifycfg -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck %s
 
 define void @widget(i32 %arg) {
 ; CHECK-LABEL: @widget(
 ; CHECK-NEXT:  bb:
 ; CHECK-NEXT:    [[SWITCH:%.*]] = icmp ult i32 [[ARG:%.*]], 2
-; CHECK-NEXT:    br i1 [[SWITCH]], label [[BB2:%.*]], label [[INFLOOP:%.*]]
-; CHECK:       bb2:
+; CHECK-NEXT:    br i1 [[SWITCH]], label [[COMMON_RET:%.*]], label [[INFLOOP:%.*]]
+; CHECK:       common.ret:
 ; CHECK-NEXT:    ret void
 ; CHECK:       infloop:
 ; CHECK-NEXT:    br label [[INFLOOP]]
 ;
 bb:
   %tmp = icmp eq i32 %arg, 0
   br i1 %tmp, label %bb2, label %bb1
 

llvm/test/Transforms/SimplifyCFG/SimplifyEqualityComparisonWithOnlyPredecessor-domtree-preservation-edgecase.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt -S -simplifycfg -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck %s
 
 declare void @zzz()
 
 define i32 @lex(i1 %c0, i1 %c1, i32 %r0, i32 %r1, i32 %v) {
 ; CHECK-LABEL: @lex(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[C0_NOT:%.*]] = xor i1 [[C0:%.*]], true
 ; CHECK-NEXT:    [[C1_NOT:%.*]] = xor i1 [[C1:%.*]], true
 ; CHECK-NEXT:    [[BRMERGE:%.*]] = select i1 [[C0_NOT]], i1 true, i1 [[C1_NOT]]
 ; CHECK-NEXT:    [[R0_MUX:%.*]] = select i1 [[C0_NOT]], i32 [[R0:%.*]], i32 [[R1:%.*]]
-; CHECK-NEXT:    br i1 [[BRMERGE]], label [[IF_THEN:%.*]], label [[DO_BODY:%.*]]
-; CHECK:       if.then:
-; CHECK-NEXT:    [[MERGE:%.*]] = phi i32 [ [[R0_MUX]], [[ENTRY:%.*]] ], [ [[R1]], [[DO_BODY]] ]
-; CHECK-NEXT:    ret i32 [[MERGE]]
+; CHECK-NEXT:    br i1 [[BRMERGE]], label [[COMMON_RET:%.*]], label [[DO_BODY:%.*]]
+; CHECK:       common.ret:
+; CHECK-NEXT:    [[COMMON_RET_OP:%.*]] = phi i32 [ [[R0_MUX]], [[ENTRY:%.*]] ], [ [[R1]], [[DO_BODY]] ]
+; CHECK-NEXT:    ret i32 [[COMMON_RET_OP]]
 ; CHECK:       do.body:
 ; CHECK-NEXT:    call void @zzz()
-; CHECK-NEXT:    switch i32 [[V:%.*]], label [[IF_THEN]] [
+; CHECK-NEXT:    switch i32 [[V:%.*]], label [[COMMON_RET]] [
 ; CHECK-NEXT:    i32 10, label [[DO_BODY]]
 ; CHECK-NEXT:    i32 32, label [[DO_BODY]]
 ; CHECK-NEXT:    i32 9, label [[DO_BODY]]
 ; CHECK-NEXT:    ]
 ;
 entry:
   br i1 %c0, label %if.end, label %if.then
 

llvm/test/Transforms/SimplifyCFG/basictest.ll

untaken:
   ret void
 }
 
 declare void @foo()
 
 ; PR5795
 define void @test5(i32 %A) {
 ; CHECK-LABEL: @test5(
+; CHECK-NEXT:  common.ret:
 ; CHECK-NEXT:    ret void
 ;
   switch i32 %A, label %return [
   i32 2, label %1
   i32 10, label %2
   ]
 
   ret void

llvm/test/Transforms/SimplifyCFG/hoist-dbgvalue.ll

 define i16 @hoist_with_debug3_pr49982(i32 %x, i1 %c.2) !dbg !26 {
 ; CHECK-LABEL: @hoist_with_debug3_pr49982(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    br label [[FOR_COND:%.*]]
 ; CHECK:       for.cond:
 ; CHECK-NEXT:    [[C_0:%.*]] = icmp sgt i32 [[X:%.*]], 0
 ; CHECK-NEXT:    [[BRMERGE:%.*]] = select i1 [[C_0]], i1 true, i1 [[C_2:%.*]]
 ; CHECK-NEXT:    [[DOTMUX:%.*]] = select i1 [[C_0]], i16 0, i16 20
-; CHECK-NEXT:    br i1 [[BRMERGE]], label [[EXIT_1:%.*]], label [[FOR_COND]]
-; CHECK:       exit.1:
+; CHECK-NEXT:    br i1 [[BRMERGE]], label [[COMMON_RET:%.*]], label [[FOR_COND]]
+; CHECK:       common.ret:
 ; CHECK-NEXT:    ret i16 [[DOTMUX]]
 ;
 entry:
   br label %for.cond
 
 for.cond:
   %c.0 = icmp sgt i32 %x, 0
   br i1 %c.0, label %check, label %latch

llvm/test/Transforms/SimplifyCFG/pr48778-sdiv-speculation.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt -simplifycfg -S < %s | FileCheck %s
 
 ; sdiv INT_MIN / -1 should not be speculated.
 define i32 @test(i1 %cmp) {
 ; CHECK-LABEL: @test(
-; CHECK-NEXT:    br i1 [[CMP:%.*]], label [[IF:%.*]], label [[ELSE:%.*]]
+; CHECK-NEXT:    br i1 [[CMP:%.*]], label [[IF:%.*]], label [[COMMON_RET:%.*]]
 ; CHECK:       if:
 ; CHECK-NEXT:    [[DIV:%.*]] = sdiv i32 -2147483648, -1
 ; CHECK-NEXT:    [[CMP2:%.*]] = icmp ne i32 [[DIV]], 0
 ; CHECK-NEXT:    [[SPEC_SELECT:%.*]] = select i1 [[CMP2]], i32 1, i32 0
-; CHECK-NEXT:    br label [[ELSE]]
-; CHECK:       else:
-; CHECK-NEXT:    [[MERGE:%.*]] = phi i32 [ 0, [[TMP0:%.*]] ], [ [[SPEC_SELECT]], [[IF]] ]
-; CHECK-NEXT:    ret i32 [[MERGE]]
+; CHECK-NEXT:    br label [[COMMON_RET]]
+; CHECK:       common.ret:
+; CHECK-NEXT:    [[COMMON_RET_OP:%.*]] = phi i32 [ 0, [[TMP0:%.*]] ], [ [[SPEC_SELECT]], [[IF]] ]
+; CHECK-NEXT:    ret i32 [[COMMON_RET_OP]]
 ;
   br i1 %cmp, label %if, label %else
 
 if:
   %div = sdiv i32 -2147483648, -1
   %cmp2 = icmp ne i32 %div, 0
   br i1 %cmp2, label %end, label %else
 
 else:
   ret i32 0
 
 end:
   ret i32 1
 }

llvm/test/Transforms/SimplifyCFG/rangereduce.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt < %s -simplifycfg -simplifycfg-require-and-preserve-domtree=1 -switch-to-lookup -S | FileCheck %s
 ; RUN: opt < %s -passes='simplify-cfg<switch-to-lookup>' -S | FileCheck %s
 
 target datalayout = "e-n32"
 
 define i32 @test1(i32 %a) {
 ; CHECK-LABEL: @test1(
 ; CHECK-NEXT:    [[TMP1:%.*]] = sub i32 [[A:%.*]], 97
 ; CHECK-NEXT:    [[TMP2:%.*]] = lshr i32 [[TMP1]], 2
 ; CHECK-NEXT:    [[TMP3:%.*]] = shl i32 [[TMP1]], 30
 ; CHECK-NEXT:    [[TMP4:%.*]] = or i32 [[TMP2]], [[TMP3]]
-; CHECK-NEXT:    switch i32 [[TMP4]], label [[DEF:%.*]] [
+; CHECK-NEXT:    switch i32 [[TMP4]], label [[COMMON_RET:%.*]] [
 ; CHECK-NEXT:    i32 0, label [[ONE:%.*]]
 ; CHECK-NEXT:    i32 1, label [[TWO:%.*]]
 ; CHECK-NEXT:    i32 2, label [[THREE:%.*]]
 ; CHECK-NEXT:    i32 3, label [[THREE]]
 ; CHECK-NEXT:    ]
-; CHECK:       def:
-; CHECK-NEXT:    [[MERGE:%.*]] = phi i32 [ 8867, [[TMP0:%.*]] ], [ 11984, [[ONE]] ], [ 1143, [[TWO]] ], [ 99783, [[THREE]] ]
-; CHECK-NEXT:    ret i32 [[MERGE]]
+; CHECK:       common.ret:
+; CHECK-NEXT:    [[COMMON_RET_OP:%.*]] = phi i32 [ 11984, [[ONE]] ], [ 1143, [[TWO]] ], [ 99783, [[THREE]] ], [ 8867, [[TMP0:%.*]] ]
+; CHECK-NEXT:    ret i32 [[COMMON_RET_OP]]
 ; CHECK:       one:
-; CHECK-NEXT:    br label [[DEF]]
+; CHECK-NEXT:    br label [[COMMON_RET]]
 ; CHECK:       two:
-; CHECK-NEXT:    br label [[DEF]]
+; CHECK-NEXT:    br label [[COMMON_RET]]
 ; CHECK:       three:
-; CHECK-NEXT:    br label [[DEF]]
+; CHECK-NEXT:    br label [[COMMON_RET]]
 ;
   switch i32 %a, label %def [
   i32 97, label %one
   i32 101, label %two
   i32 105, label %three
   i32 109, label %three
   ]
 
 def:
   ret i32 8867
 
 one:
   ret i32 11984
 two:
   ret i32 1143
 three:
   ret i32 99783
 }
 
 ; Optimization shouldn't trigger; bitwidth > 64
 define i128 @test2(i128 %a) {
 ; CHECK-LABEL: @test2(
-; CHECK-NEXT:    switch i128 [[A:%.*]], label [[DEF:%.*]] [
+; CHECK-NEXT:    switch i128 [[A:%.*]], label [[COMMON_RET:%.*]] [
 ; CHECK-NEXT:    i128 97, label [[ONE:%.*]]
 ; CHECK-NEXT:    i128 101, label [[TWO:%.*]]
 ; CHECK-NEXT:    i128 105, label [[THREE:%.*]]
 ; CHECK-NEXT:    i128 109, label [[THREE]]
 ; CHECK-NEXT:    ]
-; CHECK:       def:
-; CHECK-NEXT:    [[MERGE:%.*]] = phi i128 [ 8867, [[TMP0:%.*]] ], [ 11984, [[ONE]] ], [ 1143, [[TWO]] ], [ 99783, [[THREE]] ]
-; CHECK-NEXT:    ret i128 [[MERGE]]
+; CHECK:       common.ret:
+; CHECK-NEXT:    [[COMMON_RET_OP:%.*]] = phi i128 [ 11984, [[ONE]] ], [ 1143, [[TWO]] ], [ 99783, [[THREE]] ], [ 8867, [[TMP0:%.*]] ]
+; CHECK-NEXT:    ret i128 [[COMMON_RET_OP]]
 ; CHECK:       one:
-; CHECK-NEXT:    br label [[DEF]]
+; CHECK-NEXT:    br label [[COMMON_RET]]
 ; CHECK:       two:
-; CHECK-NEXT:    br label [[DEF]]
+; CHECK-NEXT:    br label [[COMMON_RET]]
 ; CHECK:       three:
-; CHECK-NEXT:    br label [[DEF]]
+; CHECK-NEXT:    br label [[COMMON_RET]]
 ;
   switch i128 %a, label %def [
   i128 97, label %one
   i128 101, label %two
   i128 105, label %three
   i128 109, label %three
   ]
 
 def:
   ret i128 8867
 
 one:
   ret i128 11984
 two:
   ret i128 1143
 three:
   ret i128 99783
 }
 
 ; Optimization shouldn't trigger; no holes present
 define i32 @test3(i32 %a) {
 ; CHECK-LABEL: @test3(
-; CHECK-NEXT:    switch i32 [[A:%.*]], label [[DEF:%.*]] [
+; CHECK-NEXT:    switch i32 [[A:%.*]], label [[COMMON_RET:%.*]] [
 ; CHECK-NEXT:    i32 97, label [[ONE:%.*]]
 ; CHECK-NEXT:    i32 98, label [[TWO:%.*]]
 ; CHECK-NEXT:    i32 99, label [[THREE:%.*]]
 ; CHECK-NEXT:    ]
-; CHECK:       def:
-; CHECK-NEXT:    [[MERGE:%.*]] = phi i32 [ 8867, [[TMP0:%.*]] ], [ 11984, [[ONE]] ], [ 1143, [[TWO]] ], [ 99783, [[THREE]] ]
-; CHECK-NEXT:    ret i32 [[MERGE]]
+; CHECK:       common.ret:
+; CHECK-NEXT:    [[COMMON_RET_OP:%.*]] = phi i32 [ 11984, [[ONE]] ], [ 1143, [[TWO]] ], [ 99783, [[THREE]] ], [ 8867, [[TMP0:%.*]] ]
+; CHECK-NEXT:    ret i32 [[COMMON_RET_OP]]
 ; CHECK:       one:
-; CHECK-NEXT:    br label [[DEF]]
+; CHECK-NEXT:    br label [[COMMON_RET]]
 ; CHECK:       two:
-; CHECK-NEXT:    br label [[DEF]]
+; CHECK-NEXT:    br label [[COMMON_RET]]
 ; CHECK:       three:
-; CHECK-NEXT:    br label [[DEF]]
+; CHECK-NEXT:    br label [[COMMON_RET]]
 ;
   switch i32 %a, label %def [
   i32 97, label %one
   i32 98, label %two
   i32 99, label %three
   ]
 
 def:
   ret i32 8867
 
 one:
   ret i32 11984
 two:
   ret i32 1143
 three:
   ret i32 99783
 }
 
 ; Optimization shouldn't trigger; not an arithmetic progression
 define i32 @test4(i32 %a) {
 ; CHECK-LABEL: @test4(
-; CHECK-NEXT:    switch i32 [[A:%.*]], label [[DEF:%.*]] [
+; CHECK-NEXT:    switch i32 [[A:%.*]], label [[COMMON_RET:%.*]] [
 ; CHECK-NEXT:    i32 97, label [[ONE:%.*]]
 ; CHECK-NEXT:    i32 102, label [[TWO:%.*]]
 ; CHECK-NEXT:    i32 105, label [[THREE:%.*]]
 ; CHECK-NEXT:    i32 109, label [[THREE]]
 ; CHECK-NEXT:    ]
-; CHECK:       def:
-; CHECK-NEXT:    [[MERGE:%.*]] = phi i32 [ 8867, [[TMP0:%.*]] ], [ 11984, [[ONE]] ], [ 1143, [[TWO]] ], [ 99783, [[THREE]] ]
-; CHECK-NEXT:    ret i32 [[MERGE]]
+; CHECK:       common.ret:
+; CHECK-NEXT:    [[COMMON_RET_OP:%.*]] = phi i32 [ 11984, [[ONE]] ], [ 1143, [[TWO]] ], [ 99783, [[THREE]] ], [ 8867, [[TMP0:%.*]] ]
+; CHECK-NEXT:    ret i32 [[COMMON_RET_OP]]
 ; CHECK:       one:
-; CHECK-NEXT:    br label [[DEF]]
+; CHECK-NEXT:    br label [[COMMON_RET]]
 ; CHECK:       two:
-; CHECK-NEXT:    br label [[DEF]]
+; CHECK-NEXT:    br label [[COMMON_RET]]
 ; CHECK:       three:
-; CHECK-NEXT:    br label [[DEF]]
+; CHECK-NEXT:    br label [[COMMON_RET]]
 ;
   switch i32 %a, label %def [
   i32 97, label %one
   i32 102, label %two
   i32 105, label %three
   i32 109, label %three
   ]
 
 def:
   ret i32 8867
 
 one:
   ret i32 11984
 two:
   ret i32 1143
 three:
   ret i32 99783
 }
 
 ; Optimization shouldn't trigger; not a power of two
 define i32 @test5(i32 %a) {
 ; CHECK-LABEL: @test5(
-; CHECK-NEXT:    switch i32 [[A:%.*]], label [[DEF:%.*]] [
+; CHECK-NEXT:    switch i32 [[A:%.*]], label [[COMMON_RET:%.*]] [
 ; CHECK-NEXT:    i32 97, label [[ONE:%.*]]
 ; CHECK-NEXT:    i32 102, label [[TWO:%.*]]
 ; CHECK-NEXT:    i32 107, label [[THREE:%.*]]
 ; CHECK-NEXT:    i32 112, label [[THREE]]
 ; CHECK-NEXT:    ]
-; CHECK:       def:
-; CHECK-NEXT:    [[MERGE:%.*]] = phi i32 [ 8867, [[TMP0:%.*]] ], [ 11984, [[ONE]] ], [ 1143, [[TWO]] ], [ 99783, [[THREE]] ]
-; CHECK-NEXT:    ret i32 [[MERGE]]
+; CHECK:       common.ret:
+; CHECK-NEXT:    [[COMMON_RET_OP:%.*]] = phi i32 [ 11984, [[ONE]] ], [ 1143, [[TWO]] ], [ 99783, [[THREE]] ], [ 8867, [[TMP0:%.*]] ]
+; CHECK-NEXT:    ret i32 [[COMMON_RET_OP]]
 ; CHECK:       one:
-; CHECK-NEXT:    br label [[DEF]]
+; CHECK-NEXT:    br label [[COMMON_RET]]
 ; CHECK:       two:
-; CHECK-NEXT:    br label [[DEF]]
+; CHECK-NEXT:    br label [[COMMON_RET]]
 ; CHECK:       three:
-; CHECK-NEXT:    br label [[DEF]]
+; CHECK-NEXT:    br label [[COMMON_RET]]
 ;
   switch i32 %a, label %def [
   i32 97, label %one
   i32 102, label %two
   i32 107, label %three
   i32 112, label %three
   ]
 

 }
 
 define i32 @test6(i32 %a) optsize {
 ; CHECK-LABEL: @test6(
 ; CHECK-NEXT:    [[TMP1:%.*]] = sub i32 [[A:%.*]], -109
 ; CHECK-NEXT:    [[TMP2:%.*]] = lshr i32 [[TMP1]], 2
 ; CHECK-NEXT:    [[TMP3:%.*]] = shl i32 [[TMP1]], 30
 ; CHECK-NEXT:    [[TMP4:%.*]] = or i32 [[TMP2]], [[TMP3]]
-; CHECK-NEXT:    switch i32 [[TMP4]], label [[DEF:%.*]] [
+; CHECK-NEXT:    switch i32 [[TMP4]], label [[COMMON_RET:%.*]] [
 ; CHECK-NEXT:    i32 3, label [[ONE:%.*]]
 ; CHECK-NEXT:    i32 2, label [[TWO:%.*]]
 ; CHECK-NEXT:    i32 1, label [[THREE:%.*]]
 ; CHECK-NEXT:    i32 0, label [[THREE]]
 ; CHECK-NEXT:    ]
-; CHECK:       def:
-; CHECK-NEXT:    [[MERGE:%.*]] = phi i32 [ 8867, [[TMP0:%.*]] ], [ 11984, [[ONE]] ], [ 1143, [[TWO]] ], [ 99783, [[THREE]] ]
-; CHECK-NEXT:    ret i32 [[MERGE]]
+; CHECK:       common.ret:
+; CHECK-NEXT:    [[COMMON_RET_OP:%.*]] = phi i32 [ 11984, [[ONE]] ], [ 1143, [[TWO]] ], [ 99783, [[THREE]] ], [ 8867, [[TMP0:%.*]] ]
+; CHECK-NEXT:    ret i32 [[COMMON_RET_OP]]
 ; CHECK:       one:
-; CHECK-NEXT:    br label [[DEF]]
+; CHECK-NEXT:    br label [[COMMON_RET]]
 ; CHECK:       two:
-; CHECK-NEXT:    br label [[DEF]]
+; CHECK-NEXT:    br label [[COMMON_RET]]
 ; CHECK:       three:
-; CHECK-NEXT:    br label [[DEF]]
+; CHECK-NEXT:    br label [[COMMON_RET]]
 ;
   switch i32 %a, label %def [
   i32 -97, label %one
   i32 -101, label %two
   i32 -105, label %three
   i32 -109, label %three
   ]
 

 
 define i8 @test7(i8 %a) optsize {
 ; CHECK-LABEL: @test7(
 ; CHECK-NEXT:    [[TMP1:%.*]] = sub i8 [[A:%.*]], -36
 ; CHECK-NEXT:    [[TMP2:%.*]] = lshr i8 [[TMP1]], 2
 ; CHECK-NEXT:    [[TMP3:%.*]] = shl i8 [[TMP1]], 6
 ; CHECK-NEXT:    [[TMP4:%.*]] = or i8 [[TMP2]], [[TMP3]]
 ; CHECK-NEXT:    [[TMP5:%.*]] = icmp ult i8 [[TMP4]], 4
-; CHECK-NEXT:    br i1 [[TMP5]], label [[SWITCH_LOOKUP:%.*]], label [[DEF:%.*]]
+; CHECK-NEXT:    br i1 [[TMP5]], label [[SWITCH_LOOKUP:%.*]], label [[COMMON_RET:%.*]]
 ; CHECK:       switch.lookup:
 ; CHECK-NEXT:    [[SWITCH_CAST:%.*]] = zext i8 [[TMP4]] to i32
 ; CHECK-NEXT:    [[SWITCH_SHIFTAMT:%.*]] = mul i32 [[SWITCH_CAST]], 8
 ; CHECK-NEXT:    [[SWITCH_DOWNSHIFT:%.*]] = lshr i32 -943228976, [[SWITCH_SHIFTAMT]]
 ; CHECK-NEXT:    [[SWITCH_MASKED:%.*]] = trunc i32 [[SWITCH_DOWNSHIFT]] to i8
 ; CHECK-NEXT:    ret i8 [[SWITCH_MASKED]]
-; CHECK:       def:
+; CHECK:       common.ret:
 ; CHECK-NEXT:    ret i8 -93
 ;
   switch i8 %a, label %def [
   i8 220, label %one
   i8 224, label %two
   i8 228, label %three
   i8 232, label %three
   ]

 }
 
 define i32 @test8(i32 %a) optsize {
 ; CHECK-LABEL: @test8(
 ; CHECK-NEXT:    [[TMP1:%.*]] = sub i32 [[A:%.*]], 97
 ; CHECK-NEXT:    [[TMP2:%.*]] = lshr i32 [[TMP1]], 2
 ; CHECK-NEXT:    [[TMP3:%.*]] = shl i32 [[TMP1]], 30
 ; CHECK-NEXT:    [[TMP4:%.*]] = or i32 [[TMP2]], [[TMP3]]
-; CHECK-NEXT:    switch i32 [[TMP4]], label [[DEF:%.*]] [
+; CHECK-NEXT:    switch i32 [[TMP4]], label [[COMMON_RET:%.*]] [
 ; CHECK-NEXT:    i32 0, label [[ONE:%.*]]
 ; CHECK-NEXT:    i32 1, label [[TWO:%.*]]
 ; CHECK-NEXT:    i32 2, label [[THREE:%.*]]
 ; CHECK-NEXT:    i32 4, label [[THREE]]
 ; CHECK-NEXT:    ]
-; CHECK:       def:
-; CHECK-NEXT:    [[MERGE:%.*]] = phi i32 [ 8867, [[TMP0:%.*]] ], [ 11984, [[ONE]] ], [ 1143, [[TWO]] ], [ 99783, [[THREE]] ]
-; CHECK-NEXT:    ret i32 [[MERGE]]
+; CHECK:       common.ret:
+; CHECK-NEXT:    [[COMMON_RET_OP:%.*]] = phi i32 [ 11984, [[ONE]] ], [ 1143, [[TWO]] ], [ 99783, [[THREE]] ], [ 8867, [[TMP0:%.*]] ]
+; CHECK-NEXT:    ret i32 [[COMMON_RET_OP]]
 ; CHECK:       one:
-; CHECK-NEXT:    br label [[DEF]]
+; CHECK-NEXT:    br label [[COMMON_RET]]
 ; CHECK:       two:
-; CHECK-NEXT:    br label [[DEF]]
+; CHECK-NEXT:    br label [[COMMON_RET]]
 ; CHECK:       three:
-; CHECK-NEXT:    br label [[DEF]]
+; CHECK-NEXT:    br label [[COMMON_RET]]
 ;
   switch i32 %a, label %def [
   i32 97, label %one
   i32 101, label %two
   i32 105, label %three
   i32 113, label %three
   ]
 

 }
 
 define i32 @test9(i32 %a) {
 ; CHECK-LABEL: @test9(
 ; CHECK-NEXT:    [[TMP1:%.*]] = sub i32 [[A:%.*]], 6
 ; CHECK-NEXT:    [[TMP2:%.*]] = lshr i32 [[TMP1]], 1
 ; CHECK-NEXT:    [[TMP3:%.*]] = shl i32 [[TMP1]], 31
 ; CHECK-NEXT:    [[TMP4:%.*]] = or i32 [[TMP2]], [[TMP3]]
-; CHECK-NEXT:    switch i32 [[TMP4]], label [[DEF:%.*]] [
+; CHECK-NEXT:    switch i32 [[TMP4]], label [[COMMON_RET:%.*]] [
 ; CHECK-NEXT:    i32 6, label [[ONE:%.*]]
 ; CHECK-NEXT:    i32 7, label [[TWO:%.*]]
 ; CHECK-NEXT:    i32 0, label [[THREE:%.*]]
 ; CHECK-NEXT:    i32 2, label [[THREE]]
 ; CHECK-NEXT:    ]
-; CHECK:       def:
-; CHECK-NEXT:    [[MERGE:%.*]] = phi i32 [ 8867, [[TMP0:%.*]] ], [ 11984, [[ONE]] ], [ 1143, [[TWO]] ], [ 99783, [[THREE]] ]
-; CHECK-NEXT:    ret i32 [[MERGE]]
+; CHECK:       common.ret:
+; CHECK-NEXT:    [[COMMON_RET_OP:%.*]] = phi i32 [ 11984, [[ONE]] ], [ 1143, [[TWO]] ], [ 99783, [[THREE]] ], [ 8867, [[TMP0:%.*]] ]
+; CHECK-NEXT:    ret i32 [[COMMON_RET_OP]]
 ; CHECK:       one:
-; CHECK-NEXT:    br label [[DEF]]
+; CHECK-NEXT:    br label [[COMMON_RET]]
 ; CHECK:       two:
-; CHECK-NEXT:    br label [[DEF]]
+; CHECK-NEXT:    br label [[COMMON_RET]]
 ; CHECK:       three:
-; CHECK-NEXT:    br label [[DEF]]
+; CHECK-NEXT:    br label [[COMMON_RET]]
 ;
   switch i32 %a, label %def [
   i32 18, label %one
   i32 20, label %two
   i32 6, label %three
   i32 10, label %three
   ]
 

llvm/test/Transforms/SimplifyCFG/return-merge.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt < %s -simplifycfg -simplifycfg-require-and-preserve-domtree=1 -S | FileCheck --check-prefixes=CHECK %s
 ; RUN: opt < %s -debugify -simplifycfg -simplifycfg-require-and-preserve-domtree=1 -S | FileCheck --check-prefixes=DBGINFO %s
 
 define i32 @test1(i1 %C) {
 ; CHECK-LABEL: @test1(
 ; CHECK-NEXT:  entry:
-; CHECK-NEXT:    [[SPEC_SELECT:%.*]] = select i1 [[C:%.*]], i32 1, i32 0
-; CHECK-NEXT:    ret i32 [[SPEC_SELECT]]
+; CHECK-NEXT:    [[DOT:%.*]] = select i1 [[C:%.*]], i32 1, i32 0
+; CHECK-NEXT:    ret i32 [[DOT]]
 ;
 ; DBGINFO-LABEL: @test1(
 ; DBGINFO-NEXT:  entry:
 ; DBGINFO-NEXT:    call void @llvm.dbg.value(metadata i32 0, metadata [[META9:![0-9]+]], metadata !DIExpression()), !dbg [[DBG11:![0-9]+]]
-; DBGINFO-NEXT:    [[SPEC_SELECT:%.*]] = select i1 [[C:%.*]], i32 1, i32 0, !dbg [[DBG11]]
-; DBGINFO-NEXT:    ret i32 [[SPEC_SELECT]], !dbg [[DBG12:![0-9]+]]
+; DBGINFO-NEXT:    [[DOT:%.*]] = select i1 [[C:%.*]], i32 1, i32 0
+; DBGINFO-NEXT:    ret i32 [[DOT]], !dbg [[DBG12:![0-9]+]]
 ;
 entry:
   br i1 %C, label %T, label %F
 T:              ; preds = %entry
   ret i32 1
 F:              ; preds = %entry
   ret i32 0
 }
 
 define void @test2(i1 %C) {
 ; CHECK-LABEL: @test2(
-; CHECK-NEXT:  T:
+; CHECK-NEXT:  common.ret:
 ; CHECK-NEXT:    ret void
 ;
 ; DBGINFO-LABEL: @test2(
-; DBGINFO-NEXT:  T:
+; DBGINFO-NEXT:  common.ret:
 ; DBGINFO-NEXT:    call void @llvm.dbg.value(metadata i32 0, metadata [[META15:![0-9]+]], metadata !DIExpression()), !dbg [[DBG16:![0-9]+]]
 ; DBGINFO-NEXT:    ret void, !dbg [[DBG17:![0-9]+]]
 ;
   br i1 %C, label %T, label %F
 T:              ; preds = %0
   ret void
 F:              ; preds = %0
   ret void
 }
 

llvm/test/Transforms/SimplifyCFG/suppress-zero-branch-weights.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt -S -simplifycfg -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck %s
 
 ; We're sign extending an 8-bit value.
 ; The switch condition must be in the range [-128, 127], so any cases outside of that range must be dead.
 ; Only the first case has a non-zero weight, but that gets eliminated. Note
 ; that this shouldn't have been the case in the first place, but the test here
 ; ensures that all-zero branch weights are not attached causing problems downstream.
 
 define i1 @repeated_signbits(i8 %condition) {
 ; CHECK-LABEL: @repeated_signbits(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[SEXT:%.*]] = sext i8 [[CONDITION:%.*]] to i32
 ; CHECK-NEXT:    switch i32 [[SEXT]], label [[DEFAULT:%.*]] [
-; CHECK-NEXT:    i32 0, label [[A:%.*]]
-; CHECK-NEXT:    i32 127, label [[A]]
-; CHECK-NEXT:    i32 -128, label [[A]]
-; CHECK-NEXT:    i32 -1, label [[A]]
+; CHECK-NEXT:    i32 0, label [[COMMON_RET:%.*]]
+; CHECK-NEXT:    i32 127, label [[COMMON_RET]]
+; CHECK-NEXT:    i32 -128, label [[COMMON_RET]]
+; CHECK-NEXT:    i32 -1, label [[COMMON_RET]]
 ; CHECK-NEXT:    ]
-; CHECK:       a:
-; CHECK-NEXT:    [[MERGE:%.*]] = phi i1 [ true, [[ENTRY:%.*]] ], [ true, [[ENTRY]] ], [ true, [[ENTRY]] ], [ true, [[ENTRY]] ], [ false, [[DEFAULT]] ]
-; CHECK-NEXT:    ret i1 [[MERGE]]
+; CHECK:       common.ret:
+; CHECK-NEXT:    [[COMMON_RET_OP:%.*]] = phi i1 [ false, [[DEFAULT]] ], [ true, [[ENTRY:%.*]] ], [ true, [[ENTRY]] ], [ true, [[ENTRY]] ], [ true, [[ENTRY]] ]
+; CHECK-NEXT:    ret i1 [[COMMON_RET_OP]]
 ; CHECK:       default:
-; CHECK-NEXT:    br label [[A]]
+; CHECK-NEXT:    br label [[COMMON_RET]]
 ;
 entry:
   %sext = sext i8 %condition to i32
   switch i32 %sext, label %default [
   i32 -2147483648, label %a
   i32 -129, label %a
   i32 -128, label %a
   i32 -1, label %a

llvm/test/Transforms/SimplifyCFG/switch-masked-bits.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt -S -simplifycfg -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck %s
 
 define i32 @test1(i32 %x) nounwind {
 ; CHECK-LABEL: @test1(
-; CHECK-NEXT:  a:
+; CHECK-NEXT:  common.ret:
 ; CHECK-NEXT:    [[I:%.*]] = shl i32 [[X:%.*]], 1
 ; CHECK-NEXT:    [[COND:%.*]] = icmp eq i32 [[I]], 24
-; CHECK-NEXT:    [[SPEC_SELECT:%.*]] = select i1 [[COND]], i32 5, i32 0
-; CHECK-NEXT:    ret i32 [[SPEC_SELECT]]
+; CHECK-NEXT:    [[DOT:%.*]] = select i1 [[COND]], i32 5, i32 0
+; CHECK-NEXT:    ret i32 [[DOT]]
 ;
   %i = shl i32 %x, 1
   switch i32 %i, label %a [
   i32 21, label %b
   i32 24, label %c
   ]
 
 a:

 ; We're sign extending an 8-bit value.
 ; The switch condition must be in the range [-128, 127], so any cases outside of that range must be dead.
 
 define i1 @repeated_signbits(i8 %condition) {
 ; CHECK-LABEL: @repeated_signbits(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[SEXT:%.*]] = sext i8 [[CONDITION:%.*]] to i32
 ; CHECK-NEXT:    switch i32 [[SEXT]], label [[DEFAULT:%.*]] [
-; CHECK-NEXT:    i32 0, label [[A:%.*]]
-; CHECK-NEXT:    i32 127, label [[A]]
-; CHECK-NEXT:    i32 -128, label [[A]]
-; CHECK-NEXT:    i32 -1, label [[A]]
+; CHECK-NEXT:    i32 0, label [[COMMON_RET:%.*]]
+; CHECK-NEXT:    i32 127, label [[COMMON_RET]]
+; CHECK-NEXT:    i32 -128, label [[COMMON_RET]]
+; CHECK-NEXT:    i32 -1, label [[COMMON_RET]]
 ; CHECK-NEXT:    ]
-; CHECK:       a:
-; CHECK-NEXT:    [[MERGE:%.*]] = phi i1 [ true, [[ENTRY:%.*]] ], [ true, [[ENTRY]] ], [ true, [[ENTRY]] ], [ true, [[ENTRY]] ], [ false, [[DEFAULT]] ]
-; CHECK-NEXT:    ret i1 [[MERGE]]
+; CHECK:       common.ret:
+; CHECK-NEXT:    [[COMMON_RET_OP:%.*]] = phi i1 [ false, [[DEFAULT]] ], [ true, [[ENTRY:%.*]] ], [ true, [[ENTRY]] ], [ true, [[ENTRY]] ], [ true, [[ENTRY]] ]
+; CHECK-NEXT:    ret i1 [[COMMON_RET_OP]]
 ; CHECK:       default:
-; CHECK-NEXT:    br label [[A]]
+; CHECK-NEXT:    br label [[COMMON_RET]]
 ;
 entry:
   %sext = sext i8 %condition to i32
   switch i32 %sext, label %default [
   i32 -2147483648, label %a
   i32 -129, label %a
   i32 -128, label %a
   i32 -1, label %a