[NFCI][X86] Drop "atom"/"slm" target tuning "features", derive them from CPU string

[lebedev.ri]

Summary

It isn't obvious to me why these have to be features?
We know the cpu name, and as the not-failing tests show,
that is enough for X86Subtarget::isSLM()/X86Subtarget::isAtom().

[RKSimon]

I've no objections, but really I'd like to see the isAtom() and isSLM() methods removed entirely - both appear to have been added as perf regression hacks over the years, and then reused where proper feature flags should have been added instead.

[lebedev.ri]

In D104107#2813077, @RKSimon wrote:

I've no objections, but really I'd like to see the isAtom() and isSLM() methods removed entirely - both appear to have been added as perf regression hacks over the years, and then reused where proper feature flags should have been added instead.

At least some of their uses are to pick CPU-specific cost model over the generic worst-case one.
I'm not sure if this is something that can be just dropped.

[craig.topper]

llvm/lib/Target/X86/X86Subtarget.h

810

Don’t we also accept “bonnell”?

811

Don’t we also accept “silvermont”?

[lebedev.ri]

Oh i see. Thanks.

llvm/lib/Target/X86/X86.td

 def FeatureUseGLMDivSqrtCosts
     : SubtargetFeature<"use-glm-div-sqrt-costs", "UseGLMDivSqrtCosts", "true",
         "Use Goldmont specific floating point div/sqrt costs">;
 
 // Enable use of alias analysis during code generation.
 def FeatureUseAA : SubtargetFeature<"use-aa", "UseAA", "true",
                                     "Use alias analysis during codegen">;
 
-// Bonnell
-def ProcIntelAtom : SubtargetFeature<"", "X86ProcFamily", "IntelAtom", "">;
-// Silvermont
-def ProcIntelSLM  : SubtargetFeature<"", "X86ProcFamily", "IntelSLM", "">;
-
 //===----------------------------------------------------------------------===//
 // Register File Description
 //===----------------------------------------------------------------------===//
 
 include "X86RegisterInfo.td"
 include "X86RegisterBanks.td"
 
 //===----------------------------------------------------------------------===//
list<SubtargetFeature> AtomFeatures = [FeatureX87,
                                          FeatureMMX,
                                          FeatureSSSE3,
                                          FeatureFXSR,
                                          FeatureNOPL,
                                          Feature64Bit,
                                          FeatureCMPXCHG16B,
                                          FeatureMOVBE,
                                          FeatureLAHFSAHF];
-  list<SubtargetFeature> AtomTuning = [ProcIntelAtom,
-                                       FeatureSlowUAMem16,
+  list<SubtargetFeature> AtomTuning = [FeatureSlowUAMem16,
                                        FeatureLEAForSP,
                                        FeatureSlowDivide32,
                                        FeatureSlowDivide64,
                                        FeatureSlowTwoMemOps,
                                        FeatureLEAUsesAG,
                                        FeaturePadShortFunctions,
                                        FeatureInsertVZEROUPPER];
 
   // Silvermont
   list<SubtargetFeature> SLMAdditionalFeatures = [FeatureSSE42,
                                                   FeaturePOPCNT,
                                                   FeaturePCLMUL,
                                                   FeaturePRFCHW,
                                                   FeatureRDRAND];
-  list<SubtargetFeature> SLMTuning = [ProcIntelSLM,
-                                      FeatureSlowTwoMemOps,
+  list<SubtargetFeature> SLMTuning = [FeatureSlowTwoMemOps,
                                       FeatureSlowLEA,
                                       FeatureSlowIncDec,
                                       FeatureSlowDivide64,
                                       FeatureSlowPMULLD,
                                       FeatureFast7ByteNOP,
                                       FeatureFastMOVBE,
                                       FeaturePOPCNTFalseDeps,
                                       FeatureInsertVZEROUPPER];

llvm/lib/Target/X86/X86Subtarget.h

enum class Style {
   GOT,              // Used on 32 bit elf on when in pic mode.
   RIPRel,           // Used on X86-64 when in pic mode.
   None              // Set when not in pic mode.
 };
 
 } // end namespace PICStyles
 
 class X86Subtarget final : public X86GenSubtargetInfo {
-  // NOTE: Do not add anything new to this list. Coarse, CPU name based flags
-  // are not a good idea. We should be migrating away from these.
-  enum X86ProcFamilyEnum {
-    Others,
-    IntelAtom,
-    IntelSLM
-  };
-
   enum X86SSEEnum {
     NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F
   };
 
   enum X863DNowEnum {
     NoThreeDNow, MMX, ThreeDNow, ThreeDNowA
   };
 
-  /// X86 processor family: Intel Atom, and others
-  X86ProcFamilyEnum X86ProcFamily = Others;
-
   /// Which PIC style to use
   PICStyles::Style PICStyle;
 
   const TargetMachine &TM;
 
   /// SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, or none supported.
   X86SSEEnum X86SSELevel = NoSSE;
 
public:
 
   bool useBWIRegs() const {
     return hasBWI() && useAVX512Regs();
   }
 
   bool isXRaySupported() const override { return is64Bit(); }
 
   /// TODO: to be removed later and replaced with suitable properties
-  bool isAtom() const { return X86ProcFamily == IntelAtom; }
-  bool isSLM() const { return X86ProcFamily == IntelSLM; }
+  bool isAtom() const { return getTuneCPU() == "atom"; }
+  bool isSLM() const { return getTuneCPU() == "slm"; }
   bool useSoftFloat() const { return UseSoftFloat; }
   bool useAA() const override { return UseAA; }
 
   /// Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
   /// no-sse2). There isn't any reason to disable it if the target processor
   /// supports it.
   bool hasMFence() const { return hasSSE2() || is64Bit(); }
 

llvm/lib/Target/X86/X86TargetTransformInfo.h

const FeatureBitset InlineFeatureIgnoreList = {
 
       // Perf-tuning flags.
       X86::FeatureHasFastGather,
       X86::FeatureSlowUAMem32,
 
       // Based on whether user set the -mprefer-vector-width command line.
       X86::FeaturePrefer128Bit,
       X86::FeaturePrefer256Bit,
-
-      // CPU name enums. These just follow CPU string.
-      X86::ProcIntelAtom,
-      X86::ProcIntelSLM,
   };
 
 public:
   explicit X86TTIImpl(const X86TargetMachine *TM, const Function &F)
       : BaseT(TM, F.getParent()->getDataLayout()), ST(TM->getSubtargetImpl(F)),
         TLI(ST->getTargetLowering()) {}
 
   /// \name Scalar TTI Implementations