[AMDGPU][MC][NFC] Fixed typos in parser

[foad]

Looks obvious!

llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

if (OpIdx < 0)
     return -1;
 
   const MCOperand &Op = Inst.getOperand(OpIdx);
   if (!Op.isReg())
     return -1;
 
   unsigned Sub = MRI->getSubReg(Op.getReg(), AMDGPU::sub0);
   auto Reg = Sub ? Sub : Op.getReg();
-  const MCRegisterClass &AGRP32 = MRI->getRegClass(AMDGPU::AGPR_32RegClassID);
-  return AGRP32.contains(Reg) ? 1 : 0;
+  const MCRegisterClass &AGPR32 = MRI->getRegClass(AMDGPU::AGPR_32RegClassID);
+  return AGPR32.contains(Reg) ? 1 : 0;
 }
 
 bool AMDGPUAsmParser::validateAGPRLdSt(const MCInst &Inst) const {
   uint64_t TSFlags = MII.get(Inst.getOpcode()).TSFlags;
   if ((TSFlags & (SIInstrFlags::FLAT | SIInstrFlags::MUBUF |
                   SIInstrFlags::MTBUF | SIInstrFlags::MIMG |
                   SIInstrFlags::DS)) == 0)
     return true;

 }
 
 bool AMDGPUAsmParser::validateVGPRAlign(const MCInst &Inst) const {
   auto FB = getFeatureBits();
   if (!FB[AMDGPU::FeatureGFX90AInsts])
     return true;
 
   const MCRegisterInfo *MRI = getMRI();
-  const MCRegisterClass &VGRP32 = MRI->getRegClass(AMDGPU::VGPR_32RegClassID);
-  const MCRegisterClass &AGRP32 = MRI->getRegClass(AMDGPU::AGPR_32RegClassID);
+  const MCRegisterClass &VGPR32 = MRI->getRegClass(AMDGPU::VGPR_32RegClassID);
+  const MCRegisterClass &AGPR32 = MRI->getRegClass(AMDGPU::AGPR_32RegClassID);
   for (unsigned I = 0, E = Inst.getNumOperands(); I != E; ++I) {
     const MCOperand &Op = Inst.getOperand(I);
     if (!Op.isReg())
       continue;
 
     unsigned Sub = MRI->getSubReg(Op.getReg(), AMDGPU::sub0);
     if (!Sub)
       continue;
 
-    if (VGRP32.contains(Sub) && ((Sub - AMDGPU::VGPR0) & 1))
+    if (VGPR32.contains(Sub) && ((Sub - AMDGPU::VGPR0) & 1))
       return false;
-    if (AGRP32.contains(Sub) && ((Sub - AMDGPU::AGPR0) & 1))
+    if (AGPR32.contains(Sub) && ((Sub - AMDGPU::AGPR0) & 1))
       return false;
   }
 
   return true;
 }
 
 // gfx90a has an undocumented limitation:
 // DS_GWS opcodes must use even aligned registers.
 bool AMDGPUAsmParser::validateGWS(const MCInst &Inst,
                                   const OperandVector &Operands) {
   if (!getFeatureBits()[AMDGPU::FeatureGFX90AInsts])
     return true;
 
   int Opc = Inst.getOpcode();
   if (Opc != AMDGPU::DS_GWS_INIT_vi && Opc != AMDGPU::DS_GWS_BARRIER_vi &&
       Opc != AMDGPU::DS_GWS_SEMA_BR_vi)
     return true;
 
   const MCRegisterInfo *MRI = getMRI();
-  const MCRegisterClass &VGRP32 = MRI->getRegClass(AMDGPU::VGPR_32RegClassID);
+  const MCRegisterClass &VGPR32 = MRI->getRegClass(AMDGPU::VGPR_32RegClassID);
   int Data0Pos =
       AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::data0);
   assert(Data0Pos != -1);
   auto Reg = Inst.getOperand(Data0Pos).getReg();
-  auto RegIdx = Reg - (VGRP32.contains(Reg) ? AMDGPU::VGPR0 : AMDGPU::AGPR0);
+  auto RegIdx = Reg - (VGPR32.contains(Reg) ? AMDGPU::VGPR0 : AMDGPU::AGPR0);
   if (RegIdx & 1) {
     SMLoc RegLoc = getRegLoc(Reg, Operands);
     Error(RegLoc, "vgpr must be even aligned");
     return false;
   }
 
   return true;
 }