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Differential D103498

[AArch64][GlobalISel] Use PackedVectorAllTypeList for G_SHUFFLE_VECTOR
Needs ReviewPublic

Authored by paquette on Jun 1 2021, 5:29 PM.

Details

Reviewers
aemerson
jroelofs
Summary

We were missing a few types here which would cause us to fall back on some low-hanging fruit (e.g. v4s16)

Reimplement the legal rule for G_SHUFFLE_VECTOR using existing LegalityPredicate stuff, and add a helper that checks if two type indices are the same type.

Diff Detail

Unit TestsFailed

TimeTest
120 msx64 debian > LLVM.CodeGen/AArch64::arm64-rev.ll
200 msx64 windows > LLVM.CodeGen/AArch64::arm64-rev.ll

Event Timeline

paquette created this revision.Jun 1 2021, 5:29 PM
Herald added subscribers: danielkiss, hiraditya, kristof.beyls, rovka. · View Herald TranscriptJun 1 2021, 5:29 PM
paquette requested review of this revision.Jun 1 2021, 5:29 PM
Herald added a project: Restricted Project. · View Herald TranscriptJun 1 2021, 5:29 PM
Harbormaster completed remote builds in B107160: Diff 349144.Jun 1 2021, 6:32 PM
aemerson added inline comments.Jun 11 2021, 4:00 PM
llvm/test/CodeGen/AArch64/GlobalISel/select-shuffle-vector.mir
45

These lines need to stay because the test needs to check the tbl values.

150

And likewise, new tests need the constant pool values.

242

This isn't using a shuffle vector.

Revision Contents

PathSize
llvm/
include/
llvm/
CodeGen/
GlobalISel/
3 lines
lib/
CodeGen/
GlobalISel/
8 lines
Target/
AArch64/
GISel/
16 lines
test/
CodeGen/
AArch64/
GlobalISel/
61 lines
125 lines

Diff 349144

llvm/include/llvm/CodeGen/GlobalISel/LegalizerInfo.h

Show First 20 Lines • Show All 277 Lines • ▼ Show 20 Lines
LegalityPredicate scalarOrEltSizeNotPow2(unsigned TypeIdx); LegalityPredicate scalarOrEltSizeNotPow2(unsigned TypeIdx);
/// True if the total bitwidth of the specified type index is \p Size bits. /// True if the total bitwidth of the specified type index is \p Size bits.
LegalityPredicate sizeIs(unsigned TypeIdx, unsigned Size); LegalityPredicate sizeIs(unsigned TypeIdx, unsigned Size);
/// True iff the specified type indices are both the same bit size. /// True iff the specified type indices are both the same bit size.
LegalityPredicate sameSize(unsigned TypeIdx0, unsigned TypeIdx1); LegalityPredicate sameSize(unsigned TypeIdx0, unsigned TypeIdx1);
/// True iff all specified types are identical.
LegalityPredicate sameType(unsigned TypeIdx0, unsigned TypeIdx1);
/// True iff the first type index has a larger total bit size than second type /// True iff the first type index has a larger total bit size than second type
/// index. /// index.
LegalityPredicate largerThan(unsigned TypeIdx0, unsigned TypeIdx1); LegalityPredicate largerThan(unsigned TypeIdx0, unsigned TypeIdx1);
/// True iff the first type index has a smaller total bit size than second type /// True iff the first type index has a smaller total bit size than second type
/// index. /// index.
LegalityPredicate smallerThan(unsigned TypeIdx0, unsigned TypeIdx1); LegalityPredicate smallerThan(unsigned TypeIdx0, unsigned TypeIdx1);
▲ Show 20 Lines • Show All 1,211 Lines • Show Last 20 Lines

llvm/lib/CodeGen/GlobalISel/LegalityPredicates.cpp

Show First 20 Lines • Show All 168 Lines • ▼ Show 20 Lines
LegalityPredicate LegalityPredicates::sameSize(unsigned TypeIdx0, LegalityPredicate LegalityPredicates::sameSize(unsigned TypeIdx0,
unsigned TypeIdx1) { unsigned TypeIdx1) {
return [=](const LegalityQuery &Query) { return [=](const LegalityQuery &Query) {
return Query.Types[TypeIdx0].getSizeInBits() == return Query.Types[TypeIdx0].getSizeInBits() ==
Query.Types[TypeIdx1].getSizeInBits(); Query.Types[TypeIdx1].getSizeInBits();
}; };
} }
LegalityPredicate LegalityPredicates::sameType(unsigned TypeIdx0,
unsigned TypeIdx1) {
return [=](const LegalityQuery &Query) {
return Query.Types[TypeIdx0] ==
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-    return Query.Types[TypeIdx0] ==
-           Query.Types[TypeIdx1];
+    return Query.Types[TypeIdx0] == Query.Types[TypeIdx1];
Lint: Pre-merge checks: clang-format: please reformat the code ``` - return Query.Types[TypeIdx0] ==…
Query.Types[TypeIdx1];
};
}
LegalityPredicate LegalityPredicates::memSizeInBytesNotPow2(unsigned MMOIdx) { LegalityPredicate LegalityPredicates::memSizeInBytesNotPow2(unsigned MMOIdx) {
return [=](const LegalityQuery &Query) { return [=](const LegalityQuery &Query) {
return !isPowerOf2_32(Query.MMODescrs[MMOIdx].SizeInBits / 8); return !isPowerOf2_32(Query.MMODescrs[MMOIdx].SizeInBits / 8);
}; };
} }
LegalityPredicate LegalityPredicates::numElementsNotPow2(unsigned TypeIdx) { LegalityPredicate LegalityPredicates::numElementsNotPow2(unsigned TypeIdx) {
return [=](const LegalityQuery &Query) { return [=](const LegalityQuery &Query) {
Show All 11 Lines

llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp

Show First 20 Lines • Show All 663 Lines • ▼ Show 20 LinesAArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
getActionDefinitionsBuilder(G_CTLZ) getActionDefinitionsBuilder(G_CTLZ)
.legalForCartesianProduct( .legalForCartesianProduct(
{s32, s64, v8s8, v16s8, v4s16, v8s16, v2s32, v4s32}) {s32, s64, v8s8, v16s8, v4s16, v8s16, v2s32, v4s32})
.scalarize(1); .scalarize(1);
getActionDefinitionsBuilder(G_CTLZ_ZERO_UNDEF).lower(); getActionDefinitionsBuilder(G_CTLZ_ZERO_UNDEF).lower();
getActionDefinitionsBuilder(G_SHUFFLE_VECTOR) getActionDefinitionsBuilder(G_SHUFFLE_VECTOR)
.legalIf([=](const LegalityQuery &Query) {
const LLT &DstTy = Query.Types[0];
const LLT &SrcTy = Query.Types[1];
// For now just support the TBL2 variant which needs the source vectors // For now just support the TBL2 variant which needs the source vectors
// to be the same size as the dest. // to be the same size as the dest.
if (DstTy != SrcTy) .legalIf(all(typeInSet(0, PackedVectorAllTypeList), sameType(0, 1)))
return false;
for (auto &Ty : {v2s32, v4s32, v2s64, v2p0, v16s8, v8s16}) {
if (DstTy == Ty)
return true;
}
return false;
})
// G_SHUFFLE_VECTOR can have scalar sources (from 1 x s vectors), we // G_SHUFFLE_VECTOR can have scalar sources (from 1 x s vectors), we
// just want those lowered into G_BUILD_VECTOR // just want those lowered into G_BUILD_VECTOR
.lowerIf([=](const LegalityQuery &Query) { .lowerIf([=](const LegalityQuery &Query) {
return !Query.Types[1].isVector(); return !Query.Types[1].isVector();
}) })
.clampNumElements(0, v4s32, v4s32) .clampNumElements(0, v4s32, v4s32)
.clampNumElements(0, v2s64, v2s64); .clampNumElements(0, v2s64, v2s64);
▲ Show 20 Lines • Show All 463 Lines • Show Last 20 Lines

llvm/test/CodeGen/AArch64/GlobalISel/legalize-shuffle-vector.mir

Show First 20 Lines • Show All 206 Lines • ▼ Show 20 Lines bb.1:
%6:_(<4 x s32>) = COPY $q3 %6:_(<4 x s32>) = COPY $q3
%1:_(<8 x s32>) = G_CONCAT_VECTORS %5(<4 x s32>), %6(<4 x s32>) %1:_(<8 x s32>) = G_CONCAT_VECTORS %5(<4 x s32>), %6(<4 x s32>)
%2:_(p0) = COPY $x0 %2:_(p0) = COPY $x0
%7:_(<8 x s32>) = G_SHUFFLE_VECTOR %0(<8 x s32>), %1, shufflemask(0, 5, 10, 15, 6, 2, 1, 7) %7:_(<8 x s32>) = G_SHUFFLE_VECTOR %0(<8 x s32>), %1, shufflemask(0, 5, 10, 15, 6, 2, 1, 7)
G_STORE %7(<8 x s32>), %2(p0) :: (store 32) G_STORE %7(<8 x s32>), %2(p0) :: (store 32)
RET_ReallyLR RET_ReallyLR
... ...
---
name: shuffle_v4i16
alignment: 4
tracksRegLiveness: true
body: |
bb.1:
liveins: $d0, $d1
; CHECK-LABEL: name: shuffle_v4i16
; CHECK: liveins: $d0, $d1
; CHECK: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0
; CHECK: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $d1
; CHECK: [[SHUF:%[0-9]+]]:_(<4 x s16>) = G_SHUFFLE_VECTOR [[COPY]](<4 x s16>), [[COPY1]], shufflemask(0, 0, 0, 0)
; CHECK: $d0 = COPY [[SHUF]](<4 x s16>)
; CHECK: RET_ReallyLR implicit $d0
%0:_(<4 x s16>) = COPY $d0
%1:_(<4 x s16>) = COPY $d1
%2:_(<4 x s16>) = G_SHUFFLE_VECTOR %0(<4 x s16>), %1, shufflemask(0, 0, 0, 0)
$d0 = COPY %2(<4 x s16>)
RET_ReallyLR implicit $d0
...
---
name: shuffle_v8i8
alignment: 4
tracksRegLiveness: true
body: |
bb.1:
liveins: $d0, $d1
; CHECK-LABEL: name: shuffle_v8i8
; CHECK: liveins: $d0, $d1
; CHECK: [[COPY:%[0-9]+]]:_(<8 x s8>) = COPY $d0
; CHECK: [[COPY1:%[0-9]+]]:_(<8 x s8>) = COPY $d1
; CHECK: [[SHUF:%[0-9]+]]:_(<8 x s8>) = G_SHUFFLE_VECTOR [[COPY]](<8 x s8>), [[COPY1]], shufflemask(0, 0, 0, 0, 0, 0, 0, 0)
; CHECK: $d0 = COPY [[SHUF]](<8 x s8>)
; CHECK: RET_ReallyLR implicit $d0
%0:_(<8 x s8>) = COPY $d0
%1:_(<8 x s8>) = COPY $d1
%2:_(<8 x s8>) = G_SHUFFLE_VECTOR %0(<8 x s8>), %1, shufflemask(0, 0, 0, 0, 0, 0, 0, 0)
$d0 = COPY %2(<8 x s8>)
RET_ReallyLR implicit $d0
...
---
name: shuffle_v2i32
alignment: 4
tracksRegLiveness: true
body: |
bb.1:
liveins: $d0, $d1
; CHECK-LABEL: name: shuffle_v2i32
; CHECK: liveins: $d0, $d1
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $d1
; CHECK: [[SHUF:%[0-9]+]]:_(<2 x s32>) = G_SHUFFLE_VECTOR [[COPY]](<2 x s32>), [[COPY1]], shufflemask(0, 0)
; CHECK: $d0 = COPY [[SHUF]](<2 x s32>)
; CHECK: RET_ReallyLR implicit $d0
%0:_(<2 x s32>) = COPY $d0
%1:_(<2 x s32>) = COPY $d1
%2:_(<2 x s32>) = G_SHUFFLE_VECTOR %0(<2 x s32>), %1, shufflemask(0, 0)
$d0 = COPY %2(<2 x s32>)
RET_ReallyLR implicit $d0

llvm/test/CodeGen/AArch64/GlobalISel/select-shuffle-vector.mir

Show All 21 Lines define <4 x i32> @shuffle_tbl_v4i32(<4 x i32> %a, <4 x i32> %b) {
ret <4 x i32> %shuf ret <4 x i32> %shuf
} }
define <2 x i64> @shuffle_v2i64(<2 x i64> %a, <2 x i64> %b) { define <2 x i64> @shuffle_v2i64(<2 x i64> %a, <2 x i64> %b) {
%shuf = shufflevector <2 x i64> %a, <2 x i64> %b, <2 x i32> zeroinitializer %shuf = shufflevector <2 x i64> %a, <2 x i64> %b, <2 x i32> zeroinitializer
ret <2 x i64> %shuf ret <2 x i64> %shuf
} }
define void @shuffle_v4i16() { unreachable }
define void @shuffle_v8i8() { unreachable }
define void @shuffle_v2i32() { unreachable }
... ...
--- ---
name: shuffle_v2f32 name: shuffle_v2f32
alignment: 4 alignment: 4
legalized: true legalized: true
regBankSelected: true regBankSelected: true
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.1 (%ir-block.0): bb.1 (%ir-block.0):
liveins: $d0, $d1 liveins: $d0, $d1
; CHECK-LABEL: name: shuffle_v2f32 ; CHECK-LABEL: name: shuffle_v2f32
; CHECK: constants:
; CHECK: - id: 0
; CHECK: value: '<8 x i8> <i8 4, i8 5, i8 6, i8 7, i8 0, i8 1, i8 2, i8 3>'
; CHECK: alignment: 8
aemersonUnsubmitted
Not Done
ReplyInline Actions

These lines need to stay because the test needs to check the tbl values.

aemerson: These lines need to stay because the test needs to check the tbl values.
; CHECK: liveins: $d0, $d1 ; CHECK: liveins: $d0, $d1
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
; CHECK: [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) %const.0 ; CHECK: [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) %const.0
; CHECK: [[LDRDui:%[0-9]+]]:fpr64 = LDRDui [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) %const.0 ; CHECK: [[LDRDui:%[0-9]+]]:fpr64 = LDRDui [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) %const.0 :: (load 8 from constant-pool)
; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF ; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.dsub ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.dsub
; CHECK: [[DEF1:%[0-9]+]]:fpr128 = IMPLICIT_DEF ; CHECK: [[DEF1:%[0-9]+]]:fpr128 = IMPLICIT_DEF
; CHECK: [[INSERT_SUBREG1:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF1]], [[COPY1]], %subreg.dsub ; CHECK: [[INSERT_SUBREG1:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF1]], [[COPY1]], %subreg.dsub
; CHECK: [[INSvi64lane:%[0-9]+]]:fpr128 = INSvi64lane [[INSERT_SUBREG]], 1, [[INSERT_SUBREG1]], 0 ; CHECK: [[INSvi64lane:%[0-9]+]]:fpr128 = INSvi64lane [[INSERT_SUBREG]], 1, [[INSERT_SUBREG1]], 0
; CHECK: [[DEF2:%[0-9]+]]:fpr128 = IMPLICIT_DEF ; CHECK: [[DEF2:%[0-9]+]]:fpr128 = IMPLICIT_DEF
; CHECK: [[INSERT_SUBREG2:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF2]], [[LDRDui]], %subreg.dsub ; CHECK: [[INSERT_SUBREG2:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF2]], [[LDRDui]], %subreg.dsub
; CHECK: [[TBLv16i8One:%[0-9]+]]:fpr128 = TBLv16i8One [[INSvi64lane]], [[INSERT_SUBREG2]] ; CHECK: [[TBLv16i8One:%[0-9]+]]:fpr128 = TBLv16i8One [[INSvi64lane]], [[INSERT_SUBREG2]]
Show All 13 Lines
legalized: true legalized: true
regBankSelected: true regBankSelected: true
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.1 (%ir-block.0): bb.1 (%ir-block.0):
liveins: $q0, $q1 liveins: $q0, $q1
; CHECK-LABEL: name: shuffle_v4i32 ; CHECK-LABEL: name: shuffle_v4i32
; CHECK: constants:
; CHECK: value: '<16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 12, i8 13, i8 14, i8 15, i8 0, i8 1, i8 2, i8 3>'
; CHECK: alignment: 16
; CHECK: isTargetSpecific: false
; CHECK: liveins: $q0, $q1 ; CHECK: liveins: $q0, $q1
; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
; CHECK: [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) %const.0 ; CHECK: [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) %const.0
; CHECK: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) %const.0 ; CHECK: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) %const.0 :: (load 16 from constant-pool)
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:qq = REG_SEQUENCE [[COPY]], %subreg.qsub0, [[COPY1]], %subreg.qsub1 ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:qq = REG_SEQUENCE [[COPY]], %subreg.qsub0, [[COPY1]], %subreg.qsub1
; CHECK: [[TBLv16i8Two:%[0-9]+]]:fpr128 = TBLv16i8Two [[REG_SEQUENCE]], [[LDRQui]] ; CHECK: [[TBLv16i8Two:%[0-9]+]]:fpr128 = TBLv16i8Two [[REG_SEQUENCE]], [[LDRQui]]
; CHECK: $q0 = COPY [[TBLv16i8Two]] ; CHECK: $q0 = COPY [[TBLv16i8Two]]
; CHECK: RET_ReallyLR implicit $q0 ; CHECK: RET_ReallyLR implicit $q0
%0:fpr(<4 x s32>) = COPY $q0 %0:fpr(<4 x s32>) = COPY $q0
%1:fpr(<4 x s32>) = COPY $q1 %1:fpr(<4 x s32>) = COPY $q1
%2:fpr(<4 x s32>) = G_SHUFFLE_VECTOR %0(<4 x s32>), %1, shufflemask(0, 1, 3, 0) %2:fpr(<4 x s32>) = G_SHUFFLE_VECTOR %0(<4 x s32>), %1, shufflemask(0, 1, 3, 0)
$q0 = COPY %2(<4 x s32>) $q0 = COPY %2(<4 x s32>)
RET_ReallyLR implicit $q0 RET_ReallyLR implicit $q0
... ...
--- ---
name: shuffle_tbl_v4i32 name: shuffle_tbl_v4i32
alignment: 4 alignment: 4
legalized: true legalized: true
regBankSelected: true regBankSelected: true
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.1 (%ir-block.0): bb.1 (%ir-block.0):
liveins: $q0, $q1 liveins: $q0, $q1
; CHECK-LABEL: name: shuffle_tbl_v4i32 ; CHECK-LABEL: name: shuffle_tbl_v4i32
; CHECK: constants:
; CHECK: value: '<16 x i8> <i8 20, i8 21, i8 22, i8 23, i8 28, i8 29, i8 30, i8 31, i8 4, i8 5, i8 6, i8 7, i8 0, i8 1, i8 2, i8 3>'
; CHECK: alignment: 16
; CHECK: isTargetSpecific: false
; CHECK: liveins: $q0, $q1 ; CHECK: liveins: $q0, $q1
; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
; CHECK: [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) %const.0 ; CHECK: [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) %const.0
; CHECK: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) %const.0 ; CHECK: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) %const.0 :: (load 16 from constant-pool)
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:qq = REG_SEQUENCE [[COPY]], %subreg.qsub0, [[COPY1]], %subreg.qsub1 ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:qq = REG_SEQUENCE [[COPY]], %subreg.qsub0, [[COPY1]], %subreg.qsub1
; CHECK: [[TBLv16i8Two:%[0-9]+]]:fpr128 = TBLv16i8Two [[REG_SEQUENCE]], [[LDRQui]] ; CHECK: [[TBLv16i8Two:%[0-9]+]]:fpr128 = TBLv16i8Two [[REG_SEQUENCE]], [[LDRQui]]
; CHECK: $q0 = COPY [[TBLv16i8Two]] ; CHECK: $q0 = COPY [[TBLv16i8Two]]
; CHECK: RET_ReallyLR implicit $q0 ; CHECK: RET_ReallyLR implicit $q0
%0:fpr(<4 x s32>) = COPY $q0 %0:fpr(<4 x s32>) = COPY $q0
%1:fpr(<4 x s32>) = COPY $q1 %1:fpr(<4 x s32>) = COPY $q1
%2:fpr(<4 x s32>) = G_SHUFFLE_VECTOR %0(<4 x s32>), %1, shufflemask(5, 7, 1, 0) %2:fpr(<4 x s32>) = G_SHUFFLE_VECTOR %0(<4 x s32>), %1, shufflemask(5, 7, 1, 0)
$q0 = COPY %2(<4 x s32>) $q0 = COPY %2(<4 x s32>)
RET_ReallyLR implicit $q0 RET_ReallyLR implicit $q0
... ...
--- ---
name: shuffle_v2i64 name: shuffle_v2i64
alignment: 4 alignment: 4
legalized: true legalized: true
regBankSelected: true regBankSelected: true
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.1 (%ir-block.0): bb.1 (%ir-block.0):
liveins: $q0, $q1 liveins: $q0, $q1
; CHECK-LABEL: name: shuffle_v2i64 ; CHECK-LABEL: name: shuffle_v2i64
; CHECK: constants:
; CHECK: value: '<16 x i8> <i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7>'
; CHECK: alignment: 16
; CHECK: isTargetSpecific: false
; CHECK: liveins: $q0, $q1 ; CHECK: liveins: $q0, $q1
; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
; CHECK: [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) %const.0 ; CHECK: [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) %const.0
; CHECK: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) %const.0 ; CHECK: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) %const.0 :: (load 16 from constant-pool)
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:qq = REG_SEQUENCE [[COPY]], %subreg.qsub0, [[COPY1]], %subreg.qsub1 ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:qq = REG_SEQUENCE [[COPY]], %subreg.qsub0, [[COPY1]], %subreg.qsub1
; CHECK: [[TBLv16i8Two:%[0-9]+]]:fpr128 = TBLv16i8Two [[REG_SEQUENCE]], [[LDRQui]] ; CHECK: [[TBLv16i8Two:%[0-9]+]]:fpr128 = TBLv16i8Two [[REG_SEQUENCE]], [[LDRQui]]
; CHECK: $q0 = COPY [[TBLv16i8Two]] ; CHECK: $q0 = COPY [[TBLv16i8Two]]
; CHECK: RET_ReallyLR implicit $q0 ; CHECK: RET_ReallyLR implicit $q0
%0:fpr(<2 x s64>) = COPY $q0 %0:fpr(<2 x s64>) = COPY $q0
%1:fpr(<2 x s64>) = COPY $q1 %1:fpr(<2 x s64>) = COPY $q1
%2:fpr(<2 x s64>) = G_SHUFFLE_VECTOR %0(<2 x s64>), %1, shufflemask(1, 0) %2:fpr(<2 x s64>) = G_SHUFFLE_VECTOR %0(<2 x s64>), %1, shufflemask(1, 0)
$q0 = COPY %2(<2 x s64>) $q0 = COPY %2(<2 x s64>)
RET_ReallyLR implicit $q0 RET_ReallyLR implicit $q0
... ...
---
name: shuffle_v4i16
aemersonUnsubmitted
Not Done
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And likewise, new tests need the constant pool values.

aemerson: And likewise, new tests need the constant pool values.
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
machineFunctionInfo: {}
body: |
bb.0:
liveins: $d0, $d1
; CHECK-LABEL: name: shuffle_v4i16
; CHECK: liveins: $d0, $d1
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
; CHECK: [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) %const.0
; CHECK: [[LDRDui:%[0-9]+]]:fpr64 = LDRDui [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) %const.0 :: (load 8 from constant-pool)
; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.dsub
; CHECK: [[DEF1:%[0-9]+]]:fpr128 = IMPLICIT_DEF
; CHECK: [[INSERT_SUBREG1:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF1]], [[COPY1]], %subreg.dsub
; CHECK: [[INSvi64lane:%[0-9]+]]:fpr128 = INSvi64lane [[INSERT_SUBREG]], 1, [[INSERT_SUBREG1]], 0
; CHECK: [[DEF2:%[0-9]+]]:fpr128 = IMPLICIT_DEF
; CHECK: [[INSERT_SUBREG2:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF2]], [[LDRDui]], %subreg.dsub
; CHECK: [[TBLv16i8One:%[0-9]+]]:fpr128 = TBLv16i8One [[INSvi64lane]], [[INSERT_SUBREG2]]
; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY [[TBLv16i8One]].dsub
; CHECK: $d0 = COPY [[COPY2]]
; CHECK: RET_ReallyLR implicit $d0
%0:fpr(<4 x s16>) = COPY $d0
%1:fpr(<4 x s16>) = COPY $d1
%2:fpr(<4 x s16>) = G_SHUFFLE_VECTOR %0(<4 x s16>), %1, shufflemask(0, 0, 0, 0)
$d0 = COPY %2(<4 x s16>)
RET_ReallyLR implicit $d0
...
---
name: shuffle_v8i8
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
machineFunctionInfo: {}
body: |
bb.0:
liveins: $d0, $d1
; CHECK-LABEL: name: shuffle_v8i8
; CHECK: liveins: $d0, $d1
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
; CHECK: [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) %const.0
; CHECK: [[LDRDui:%[0-9]+]]:fpr64 = LDRDui [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) %const.0 :: (load 8 from constant-pool)
; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.dsub
; CHECK: [[DEF1:%[0-9]+]]:fpr128 = IMPLICIT_DEF
; CHECK: [[INSERT_SUBREG1:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF1]], [[COPY1]], %subreg.dsub
; CHECK: [[INSvi64lane:%[0-9]+]]:fpr128 = INSvi64lane [[INSERT_SUBREG]], 1, [[INSERT_SUBREG1]], 0
; CHECK: [[DEF2:%[0-9]+]]:fpr128 = IMPLICIT_DEF
; CHECK: [[INSERT_SUBREG2:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF2]], [[LDRDui]], %subreg.dsub
; CHECK: [[TBLv16i8One:%[0-9]+]]:fpr128 = TBLv16i8One [[INSvi64lane]], [[INSERT_SUBREG2]]
; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY [[TBLv16i8One]].dsub
; CHECK: $d0 = COPY [[COPY2]]
; CHECK: RET_ReallyLR implicit $d0
%0:fpr(<8 x s8>) = COPY $d0
%1:fpr(<8 x s8>) = COPY $d1
%2:fpr(<8 x s8>) = G_SHUFFLE_VECTOR %0(<8 x s8>), %1, shufflemask(0, 0, 0, 0, 0, 0, 0, 0)
$d0 = COPY %2(<8 x s8>)
RET_ReallyLR implicit $d0
...
---
name: shuffle_v2i32
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
machineFunctionInfo: {}
body: |
bb.0:
liveins: $d0, $d1
; CHECK-LABEL: name: shuffle_v2i32
; CHECK: liveins: $d0, $d1
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.dsub
; CHECK: [[DUPv2i32lane:%[0-9]+]]:fpr64 = DUPv2i32lane [[INSERT_SUBREG]], 0
; CHECK: $d0 = COPY [[DUPv2i32lane]]
; CHECK: RET_ReallyLR implicit $d0
%0:fpr(<2 x s32>) = COPY $d0
%4:fpr(<2 x s32>) = G_IMPLICIT_DEF
%5:fpr(<4 x s32>) = G_CONCAT_VECTORS %0(<2 x s32>), %4(<2 x s32>)
%3:gpr(s64) = G_CONSTANT i64 0
%2:fpr(<2 x s32>) = G_DUPLANE32 %5, %3(s64)
aemersonUnsubmitted
Not Done
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This isn't using a shuffle vector.

aemerson: This isn't using a shuffle vector.
$d0 = COPY %2(<2 x s32>)
RET_ReallyLR implicit $d0
...