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Differential D103185

[AMDGPU][MC][GFX90A] Corrected DS_GWS opcodes
ClosedPublic

Authored by dp on May 26 2021, 10:08 AM.

Details

Reviewers
rampitec
Commits
rG13c6568c6e20: [AMDGPU][MC][GFX90A] Corrected DS_GWS opcodes
Summary

It turned out that DS_GWS opcodes must use even aligned registers.

A separate change is needed to address the issue in codegen.

Diff Detail

Event Timeline

dp created this revision.May 26 2021, 10:08 AM
Herald added subscribers: foad, kerbowa, hiraditya and 8 others. · View Herald TranscriptMay 26 2021, 10:08 AM
dp requested review of this revision.May 26 2021, 10:08 AM
Herald added a project: Restricted Project. · View Herald TranscriptMay 26 2021, 10:08 AM
Herald added subscribers: llvm-commits, wdng. · View Herald Transcript
rampitec accepted this revision.May 26 2021, 10:12 AM

LGTM. I am finishing the patch for the copdegen.

This revision is now accepted and ready to land.May 26 2021, 10:12 AM
Harbormaster completed remote builds in B106322: Diff 348010.May 26 2021, 10:35 AM
This revision was landed with ongoing or failed builds.May 26 2021, 11:32 AM
Closed by commit rG13c6568c6e20: [AMDGPU][MC][GFX90A] Corrected DS_GWS opcodes (authored by dp). · Explain Why
This revision was automatically updated to reflect the committed changes.
dp added a commit: rG13c6568c6e20: [AMDGPU][MC][GFX90A] Corrected DS_GWS opcodes.
foad added inline comments.May 27 2021, 1:47 AM
llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
4125

Typo "VGRP". I guess it was copied from elsewhere in this file.

dp marked an inline comment as done.May 27 2021, 5:48 AM
dp added inline comments.
llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
4125

Thanks Jay! I'll fix these typos on next commit.

Revision Contents

PathSize
llvm/
lib/
Target/
AMDGPU/
AsmParser/
33 lines
test/
MC/
AMDGPU/
18 lines
9 lines
60 lines
Disassembler/
AMDGPU/
60 lines

Diff 348010

llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 1,540 Lines • ▼ Show 20 Linesprivate:
bool validateMIMGMSAA(const MCInst &Inst); bool validateMIMGMSAA(const MCInst &Inst);
bool validateOpSel(const MCInst &Inst); bool validateOpSel(const MCInst &Inst);
bool validateDPP(const MCInst &Inst, const OperandVector &Operands); bool validateDPP(const MCInst &Inst, const OperandVector &Operands);
bool validateVccOperand(unsigned Reg) const; bool validateVccOperand(unsigned Reg) const;
bool validateVOP3Literal(const MCInst &Inst, const OperandVector &Operands); bool validateVOP3Literal(const MCInst &Inst, const OperandVector &Operands);
bool validateMAIAccWrite(const MCInst &Inst, const OperandVector &Operands); bool validateMAIAccWrite(const MCInst &Inst, const OperandVector &Operands);
bool validateAGPRLdSt(const MCInst &Inst) const; bool validateAGPRLdSt(const MCInst &Inst) const;
bool validateVGPRAlign(const MCInst &Inst) const; bool validateVGPRAlign(const MCInst &Inst) const;
bool validateGWS(const MCInst &Inst, const OperandVector &Operands);
bool validateDivScale(const MCInst &Inst); bool validateDivScale(const MCInst &Inst);
bool validateCoherencyBits(const MCInst &Inst, const OperandVector &Operands, bool validateCoherencyBits(const MCInst &Inst, const OperandVector &Operands,
const SMLoc &IDLoc); const SMLoc &IDLoc);
Optional<StringRef> validateLdsDirect(const MCInst &Inst); Optional<StringRef> validateLdsDirect(const MCInst &Inst);
unsigned getConstantBusLimit(unsigned Opcode) const; unsigned getConstantBusLimit(unsigned Opcode) const;
bool usesConstantBus(const MCInst &Inst, unsigned OpIdx); bool usesConstantBus(const MCInst &Inst, unsigned OpIdx);
bool isInlineConstant(const MCInst &Inst, unsigned OpIdx) const; bool isInlineConstant(const MCInst &Inst, unsigned OpIdx) const;
unsigned findImplicitSGPRReadInVOP(const MCInst &Inst) const; unsigned findImplicitSGPRReadInVOP(const MCInst &Inst) const;
▲ Show 20 Lines • Show All 2,546 Lines • ▼ Show 20 Lines if (VGRP32.contains(Sub) && ((Sub - AMDGPU::VGPR0) & 1))
return false; return false;
if (AGRP32.contains(Sub) && ((Sub - AMDGPU::AGPR0) & 1)) if (AGRP32.contains(Sub) && ((Sub - AMDGPU::AGPR0) & 1))
return false; return false;
} }
return true; return true;
} }
// gfx90a has an undocumented limitation:
// DS_GWS opcodes must use even aligned registers.
bool AMDGPUAsmParser::validateGWS(const MCInst &Inst,
const OperandVector &Operands) {
if (!getFeatureBits()[AMDGPU::FeatureGFX90AInsts])
return true;
int Opc = Inst.getOpcode();
if (Opc != AMDGPU::DS_GWS_INIT_vi &&
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-  if (Opc != AMDGPU::DS_GWS_INIT_vi &&
-      Opc != AMDGPU::DS_GWS_BARRIER_vi &&
+  if (Opc != AMDGPU::DS_GWS_INIT_vi && Opc != AMDGPU::DS_GWS_BARRIER_vi &&
Lint: Pre-merge checks: clang-format: please reformat the code ``` - if (Opc != AMDGPU::DS_GWS_INIT_vi && - Opc !
Opc != AMDGPU::DS_GWS_BARRIER_vi &&
Opc != AMDGPU::DS_GWS_SEMA_BR_vi)
return true;
const MCRegisterInfo *MRI = getMRI();
foadUnsubmitted
Not Done
ReplyInline Actions

Typo "VGRP". I guess it was copied from elsewhere in this file.

foad: Typo "VGRP". I guess it was copied from elsewhere in this file.
dpAuthorUnsubmitted
Done
ReplyInline Actions

Thanks Jay! I'll fix these typos on next commit.

dp: Thanks Jay! I'll fix these typos on next commit.
const MCRegisterClass &VGRP32 = MRI->getRegClass(AMDGPU::VGPR_32RegClassID);
int Data0Pos = AMDGPU::getNamedOperandIdx(Inst.getOpcode(),
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-  int Data0Pos = AMDGPU::getNamedOperandIdx(Inst.getOpcode(),
-                                            AMDGPU::OpName::data0);
+  int Data0Pos =
+      AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::data0);
Lint: Pre-merge checks: clang-format: please reformat the code ``` - int Data0Pos = AMDGPU::getNamedOperandIdx(Inst.
AMDGPU::OpName::data0);
assert(Data0Pos != -1);
auto Reg = Inst.getOperand(Data0Pos).getReg();
auto RegIdx = Reg - (VGRP32.contains(Reg) ? AMDGPU::VGPR0 : AMDGPU::AGPR0);
if (RegIdx & 1) {
SMLoc RegLoc = getRegLoc(Reg, Operands);
Error(RegLoc, "vgpr must be even aligned");
return false;
}
return true;
}
bool AMDGPUAsmParser::validateCoherencyBits(const MCInst &Inst, bool AMDGPUAsmParser::validateCoherencyBits(const MCInst &Inst,
const OperandVector &Operands, const OperandVector &Operands,
const SMLoc &IDLoc) { const SMLoc &IDLoc) {
int CPolPos = AMDGPU::getNamedOperandIdx(Inst.getOpcode(), int CPolPos = AMDGPU::getNamedOperandIdx(Inst.getOpcode(),
AMDGPU::OpName::cpol); AMDGPU::OpName::cpol);
if (CPolPos == -1) if (CPolPos == -1)
return true; return true;
▲ Show 20 Lines • Show All 127 Lines • ▼ Show 20 Lines if (!validateAGPRLdSt(Inst)) {
); );
return false; return false;
} }
if (!validateVGPRAlign(Inst)) { if (!validateVGPRAlign(Inst)) {
Error(IDLoc, Error(IDLoc,
"invalid register class: vgpr tuples must be 64 bit aligned"); "invalid register class: vgpr tuples must be 64 bit aligned");
return false; return false;
} }
if (!validateGWS(Inst, Operands)) {
return false;
}
if (!validateDivScale(Inst)) { if (!validateDivScale(Inst)) {
Error(IDLoc, "ABS not allowed in VOP3B instructions"); Error(IDLoc, "ABS not allowed in VOP3B instructions");
return false; return false;
} }
if (!validateCoherencyBits(Inst, Operands, IDLoc)) { if (!validateCoherencyBits(Inst, Operands, IDLoc)) {
return false; return false;
} }
▲ Show 20 Lines • Show All 4,045 Lines • Show Last 20 Lines

llvm/test/MC/AMDGPU/gfx90a_err.s

Show First 20 Lines • Show All 254 Lines • ▼ Show 20 Lines
v_add_f32_sdwa v5, v1, lds_direct dst_sel:DWORD v_add_f32_sdwa v5, v1, lds_direct dst_sel:DWORD
// GFX90A: error: lds_direct is not supported on this GPU // GFX90A: error: lds_direct is not supported on this GPU
v_ashrrev_i16 v0, lds_direct, v0 v_ashrrev_i16 v0, lds_direct, v0
// GFX90A: error: lds_direct is not supported on this GPU // GFX90A: error: lds_direct is not supported on this GPU
v_add_f32 v5, v1, lds_direct v_add_f32 v5, v1, lds_direct
// GFX90A: error: lds_direct is not supported on this GPU // GFX90A: error: lds_direct is not supported on this GPU
ds_gws_init a1 offset:65535 gds
// GFX90A: error: vgpr must be even aligned
ds_gws_init a255 offset:65535 gds
// GFX90A: error: vgpr must be even aligned
ds_gws_sema_br v1 offset:65535 gds
// GFX90A: error: vgpr must be even aligned
ds_gws_sema_br v255 offset:65535 gds
// GFX90A: error: vgpr must be even aligned
ds_gws_barrier a3 offset:4 gds
// GFX90A: error: vgpr must be even aligned
ds_gws_barrier a255 offset:4 gds
// GFX90A: error: vgpr must be even aligned

llvm/test/MC/AMDGPU/gfx90a_err_pos.s

  • This file was added.
// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx90a %s 2>&1 | FileCheck %s --implicit-check-not=error: --strict-whitespace
//==============================================================================
// vgpr must be even aligned
ds_gws_init a1 offset:65535 gds
// CHECK: error: vgpr must be even aligned
// CHECK-NEXT:{{^}}ds_gws_init a1 offset:65535 gds
// CHECK-NEXT:{{^}} ^

llvm/test/MC/AMDGPU/gfx90a_ldst_acc.s

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 10,219 Lines • ▼ Show 20 Lines
// GFX90A: ds_condxchg32_rtn_b64 a[6:7], v1, a[2:3] offset:4 ; encoding: [0x04,0x00,0xfc,0xda,0x01,0x02,0x00,0x06] // GFX90A: ds_condxchg32_rtn_b64 a[6:7], v1, a[2:3] offset:4 ; encoding: [0x04,0x00,0xfc,0xda,0x01,0x02,0x00,0x06]
// NOT-GFX90A: error: invalid register class: agpr loads and stores not supported on this GPU // NOT-GFX90A: error: invalid register class: agpr loads and stores not supported on this GPU
ds_condxchg32_rtn_b64 a[6:7], v1, a[2:3] offset:4 ds_condxchg32_rtn_b64 a[6:7], v1, a[2:3] offset:4
// GFX90A: ds_condxchg32_rtn_b64 a[6:7], v1, a[2:3] offset:65535 gds ; encoding: [0xff,0xff,0xfd,0xda,0x01,0x02,0x00,0x06] // GFX90A: ds_condxchg32_rtn_b64 a[6:7], v1, a[2:3] offset:65535 gds ; encoding: [0xff,0xff,0xfd,0xda,0x01,0x02,0x00,0x06]
// NOT-GFX90A: error: invalid register class: agpr loads and stores not supported on this GPU // NOT-GFX90A: error: invalid register class: agpr loads and stores not supported on this GPU
ds_condxchg32_rtn_b64 a[6:7], v1, a[2:3] offset:65535 gds ds_condxchg32_rtn_b64 a[6:7], v1, a[2:3] offset:65535 gds
// GFX90A: ds_gws_init a1 offset:65535 gds ; encoding: [0xff,0xff,0x33,0xdb,0x01,0x00,0x00,0x00] // GFX90A: ds_gws_init a0 offset:65535 gds ; encoding: [0xff,0xff,0x33,0xdb,0x00,0x00,0x00,0x00]
// NOT-GFX90A: error: invalid register class: agpr loads and stores not supported on this GPU // NOT-GFX90A: error: invalid register class: agpr loads and stores not supported on this GPU
ds_gws_init a1 offset:65535 gds ds_gws_init a0 offset:65535 gds
// GFX90A: ds_gws_init a255 offset:65535 gds ; encoding: [0xff,0xff,0x33,0xdb,0xff,0x00,0x00,0x00] // GFX90A: ds_gws_init a254 offset:65535 gds ; encoding: [0xff,0xff,0x33,0xdb,0xfe,0x00,0x00,0x00]
// NOT-GFX90A: error: invalid register class: agpr loads and stores not supported on this GPU // NOT-GFX90A: error: invalid register class: agpr loads and stores not supported on this GPU
ds_gws_init a255 offset:65535 gds ds_gws_init a254 offset:65535 gds
// GFX90A: ds_gws_init a1 gds ; encoding: [0x00,0x00,0x33,0xdb,0x01,0x00,0x00,0x00] // GFX90A: ds_gws_init a2 gds ; encoding: [0x00,0x00,0x33,0xdb,0x02,0x00,0x00,0x00]
// NOT-GFX90A: error: invalid register class: agpr loads and stores not supported on this GPU // NOT-GFX90A: error: invalid register class: agpr loads and stores not supported on this GPU
ds_gws_init a1 gds ds_gws_init a2 gds
// GFX90A: ds_gws_init a1 gds ; encoding: [0x00,0x00,0x33,0xdb,0x01,0x00,0x00,0x00] // GFX90A: ds_gws_init a0 gds ; encoding: [0x00,0x00,0x33,0xdb,0x00,0x00,0x00,0x00]
// NOT-GFX90A: error: invalid register class: agpr loads and stores not supported on this GPU // NOT-GFX90A: error: invalid register class: agpr loads and stores not supported on this GPU
ds_gws_init a1 gds ds_gws_init a0 gds
// GFX90A: ds_gws_init a1 offset:4 gds ; encoding: [0x04,0x00,0x33,0xdb,0x01,0x00,0x00,0x00] // GFX90A: ds_gws_init a0 offset:4 gds ; encoding: [0x04,0x00,0x33,0xdb,0x00,0x00,0x00,0x00]
// NOT-GFX90A: error: invalid register class: agpr loads and stores not supported on this GPU // NOT-GFX90A: error: invalid register class: agpr loads and stores not supported on this GPU
ds_gws_init a1 offset:4 gds ds_gws_init a0 offset:4 gds
// GFX90A: ds_gws_sema_br a1 offset:65535 gds ; encoding: [0xff,0xff,0x37,0xdb,0x01,0x00,0x00,0x00] // GFX90A: ds_gws_sema_br a2 offset:65535 gds ; encoding: [0xff,0xff,0x37,0xdb,0x02,0x00,0x00,0x00]
// NOT-GFX90A: error: invalid register class: agpr loads and stores not supported on this GPU // NOT-GFX90A: error: invalid register class: agpr loads and stores not supported on this GPU
ds_gws_sema_br a1 offset:65535 gds ds_gws_sema_br a2 offset:65535 gds
// GFX90A: ds_gws_sema_br a255 offset:65535 gds ; encoding: [0xff,0xff,0x37,0xdb,0xff,0x00,0x00,0x00] // GFX90A: ds_gws_sema_br a254 offset:65535 gds ; encoding: [0xff,0xff,0x37,0xdb,0xfe,0x00,0x00,0x00]
// NOT-GFX90A: error: invalid register class: agpr loads and stores not supported on this GPU // NOT-GFX90A: error: invalid register class: agpr loads and stores not supported on this GPU
ds_gws_sema_br a255 offset:65535 gds ds_gws_sema_br a254 offset:65535 gds
// GFX90A: ds_gws_sema_br a1 gds ; encoding: [0x00,0x00,0x37,0xdb,0x01,0x00,0x00,0x00] // GFX90A: ds_gws_sema_br a0 gds ; encoding: [0x00,0x00,0x37,0xdb,0x00,0x00,0x00,0x00]
// NOT-GFX90A: error: invalid register class: agpr loads and stores not supported on this GPU // NOT-GFX90A: error: invalid register class: agpr loads and stores not supported on this GPU
ds_gws_sema_br a1 gds ds_gws_sema_br a0 gds
// GFX90A: ds_gws_sema_br a1 gds ; encoding: [0x00,0x00,0x37,0xdb,0x01,0x00,0x00,0x00] // GFX90A: ds_gws_sema_br a2 gds ; encoding: [0x00,0x00,0x37,0xdb,0x02,0x00,0x00,0x00]
// NOT-GFX90A: error: invalid register class: agpr loads and stores not supported on this GPU // NOT-GFX90A: error: invalid register class: agpr loads and stores not supported on this GPU
ds_gws_sema_br a1 gds ds_gws_sema_br a2 gds
// GFX90A: ds_gws_sema_br a1 offset:4 gds ; encoding: [0x04,0x00,0x37,0xdb,0x01,0x00,0x00,0x00] // GFX90A: ds_gws_sema_br a0 offset:4 gds ; encoding: [0x04,0x00,0x37,0xdb,0x00,0x00,0x00,0x00]
// NOT-GFX90A: error: invalid register class: agpr loads and stores not supported on this GPU // NOT-GFX90A: error: invalid register class: agpr loads and stores not supported on this GPU
ds_gws_sema_br a1 offset:4 gds ds_gws_sema_br a0 offset:4 gds
// GFX90A: ds_gws_barrier a1 offset:65535 gds ; encoding: [0xff,0xff,0x3b,0xdb,0x01,0x00,0x00,0x00] // GFX90A: ds_gws_barrier a2 offset:65535 gds ; encoding: [0xff,0xff,0x3b,0xdb,0x02,0x00,0x00,0x00]
// NOT-GFX90A: error: invalid register class: agpr loads and stores not supported on this GPU // NOT-GFX90A: error: invalid register class: agpr loads and stores not supported on this GPU
ds_gws_barrier a1 offset:65535 gds ds_gws_barrier a2 offset:65535 gds
// GFX90A: ds_gws_barrier a255 offset:65535 gds ; encoding: [0xff,0xff,0x3b,0xdb,0xff,0x00,0x00,0x00] // GFX90A: ds_gws_barrier a254 offset:65535 gds ; encoding: [0xff,0xff,0x3b,0xdb,0xfe,0x00,0x00,0x00]
// NOT-GFX90A: error: invalid register class: agpr loads and stores not supported on this GPU // NOT-GFX90A: error: invalid register class: agpr loads and stores not supported on this GPU
ds_gws_barrier a255 offset:65535 gds ds_gws_barrier a254 offset:65535 gds
// GFX90A: ds_gws_barrier a1 gds ; encoding: [0x00,0x00,0x3b,0xdb,0x01,0x00,0x00,0x00] // GFX90A: ds_gws_barrier a0 gds ; encoding: [0x00,0x00,0x3b,0xdb,0x00,0x00,0x00,0x00]
// NOT-GFX90A: error: invalid register class: agpr loads and stores not supported on this GPU // NOT-GFX90A: error: invalid register class: agpr loads and stores not supported on this GPU
ds_gws_barrier a1 gds ds_gws_barrier a0 gds
// GFX90A: ds_gws_barrier a1 gds ; encoding: [0x00,0x00,0x3b,0xdb,0x01,0x00,0x00,0x00] // GFX90A: ds_gws_barrier a2 gds ; encoding: [0x00,0x00,0x3b,0xdb,0x02,0x00,0x00,0x00]
// NOT-GFX90A: error: invalid register class: agpr loads and stores not supported on this GPU // NOT-GFX90A: error: invalid register class: agpr loads and stores not supported on this GPU
ds_gws_barrier a1 gds ds_gws_barrier a2 gds
// GFX90A: ds_gws_barrier a1 offset:4 gds ; encoding: [0x04,0x00,0x3b,0xdb,0x01,0x00,0x00,0x00] // GFX90A: ds_gws_barrier a0 offset:4 gds ; encoding: [0x04,0x00,0x3b,0xdb,0x00,0x00,0x00,0x00]
// NOT-GFX90A: error: invalid register class: agpr loads and stores not supported on this GPU // NOT-GFX90A: error: invalid register class: agpr loads and stores not supported on this GPU
ds_gws_barrier a1 offset:4 gds ds_gws_barrier a0 offset:4 gds
// GFX90A: ds_consume a5 offset:65535 ; encoding: [0xff,0xff,0x7a,0xdb,0x00,0x00,0x00,0x05] // GFX90A: ds_consume a5 offset:65535 ; encoding: [0xff,0xff,0x7a,0xdb,0x00,0x00,0x00,0x05]
// NOT-GFX90A: error: invalid register class: agpr loads and stores not supported on this GPU // NOT-GFX90A: error: invalid register class: agpr loads and stores not supported on this GPU
ds_consume a5 offset:65535 ds_consume a5 offset:65535
// GFX90A: ds_consume a255 offset:65535 ; encoding: [0xff,0xff,0x7a,0xdb,0x00,0x00,0x00,0xff] // GFX90A: ds_consume a255 offset:65535 ; encoding: [0xff,0xff,0x7a,0xdb,0x00,0x00,0x00,0xff]
// NOT-GFX90A: error: invalid register class: agpr loads and stores not supported on this GPU // NOT-GFX90A: error: invalid register class: agpr loads and stores not supported on this GPU
ds_consume a255 offset:65535 ds_consume a255 offset:65535
▲ Show 20 Lines • Show All 900 Lines • Show Last 20 Lines

llvm/test/MC/Disassembler/AMDGPU/gfx90a_ldst_acc.txt

Show First 20 Lines • Show All 7,662 Lines • ▼ Show 20 Lines
0x00,0x00,0xfc,0xda,0x01,0x02,0x00,0x06 0x00,0x00,0xfc,0xda,0x01,0x02,0x00,0x06
# GFX90A: ds_condxchg32_rtn_b64 a[6:7], v1, a[2:3] offset:4 ; encoding: [0x04,0x00,0xfc,0xda,0x01,0x02,0x00,0x06] # GFX90A: ds_condxchg32_rtn_b64 a[6:7], v1, a[2:3] offset:4 ; encoding: [0x04,0x00,0xfc,0xda,0x01,0x02,0x00,0x06]
0x04,0x00,0xfc,0xda,0x01,0x02,0x00,0x06 0x04,0x00,0xfc,0xda,0x01,0x02,0x00,0x06
# GFX90A: ds_condxchg32_rtn_b64 a[6:7], v1, a[2:3] offset:65535 gds ; encoding: [0xff,0xff,0xfd,0xda,0x01,0x02,0x00,0x06] # GFX90A: ds_condxchg32_rtn_b64 a[6:7], v1, a[2:3] offset:65535 gds ; encoding: [0xff,0xff,0xfd,0xda,0x01,0x02,0x00,0x06]
0xff,0xff,0xfd,0xda,0x01,0x02,0x00,0x06 0xff,0xff,0xfd,0xda,0x01,0x02,0x00,0x06
# GFX90A: ds_gws_init a1 offset:65535 gds ; encoding: [0xff,0xff,0x33,0xdb,0x01,0x00,0x00,0x00] # GFX90A: ds_gws_init a2 offset:65535 gds ; encoding: [0xff,0xff,0x33,0xdb,0x02,0x00,0x00,0x00]
0xff,0xff,0x33,0xdb,0x01,0x00,0x00,0x00 0xff,0xff,0x33,0xdb,0x02,0x00,0x00,0x00
# GFX90A: ds_gws_init a255 offset:65535 gds ; encoding: [0xff,0xff,0x33,0xdb,0xff,0x00,0x00,0x00] # GFX90A: ds_gws_init a254 offset:65535 gds ; encoding: [0xff,0xff,0x33,0xdb,0xfe,0x00,0x00,0x00]
0xff,0xff,0x33,0xdb,0xff,0x00,0x00,0x00 0xff,0xff,0x33,0xdb,0xfe,0x00,0x00,0x00
# GFX90A: ds_gws_init a1 gds ; encoding: [0x00,0x00,0x33,0xdb,0x01,0x00,0x00,0x00] # GFX90A: ds_gws_init a0 gds ; encoding: [0x00,0x00,0x33,0xdb,0x00,0x00,0x00,0x00]
0x00,0x00,0x33,0xdb,0x01,0x00,0x00,0x00 0x00,0x00,0x33,0xdb,0x00,0x00,0x00,0x00
# GFX90A: ds_gws_init a1 gds ; encoding: [0x00,0x00,0x33,0xdb,0x01,0x00,0x00,0x00] # GFX90A: ds_gws_init a0 gds ; encoding: [0x00,0x00,0x33,0xdb,0x00,0x00,0x00,0x00]
0x00,0x00,0x33,0xdb,0x01,0x00,0x00,0x00 0x00,0x00,0x33,0xdb,0x00,0x00,0x00,0x00
# GFX90A: ds_gws_init a1 offset:4 gds ; encoding: [0x04,0x00,0x33,0xdb,0x01,0x00,0x00,0x00] # GFX90A: ds_gws_init a2 offset:4 gds ; encoding: [0x04,0x00,0x33,0xdb,0x02,0x00,0x00,0x00]
0x04,0x00,0x33,0xdb,0x01,0x00,0x00,0x00 0x04,0x00,0x33,0xdb,0x02,0x00,0x00,0x00
# GFX90A: ds_gws_sema_br a1 offset:65535 gds ; encoding: [0xff,0xff,0x37,0xdb,0x01,0x00,0x00,0x00] # GFX90A: ds_gws_sema_br a2 offset:65535 gds ; encoding: [0xff,0xff,0x37,0xdb,0x02,0x00,0x00,0x00]
0xff,0xff,0x37,0xdb,0x01,0x00,0x00,0x00 0xff,0xff,0x37,0xdb,0x02,0x00,0x00,0x00
# GFX90A: ds_gws_sema_br a255 offset:65535 gds ; encoding: [0xff,0xff,0x37,0xdb,0xff,0x00,0x00,0x00] # GFX90A: ds_gws_sema_br a254 offset:65535 gds ; encoding: [0xff,0xff,0x37,0xdb,0xfe,0x00,0x00,0x00]
0xff,0xff,0x37,0xdb,0xff,0x00,0x00,0x00 0xff,0xff,0x37,0xdb,0xfe,0x00,0x00,0x00
# GFX90A: ds_gws_sema_br a1 gds ; encoding: [0x00,0x00,0x37,0xdb,0x01,0x00,0x00,0x00] # GFX90A: ds_gws_sema_br a0 gds ; encoding: [0x00,0x00,0x37,0xdb,0x00,0x00,0x00,0x00]
0x00,0x00,0x37,0xdb,0x01,0x00,0x00,0x00 0x00,0x00,0x37,0xdb,0x00,0x00,0x00,0x00
# GFX90A: ds_gws_sema_br a1 gds ; encoding: [0x00,0x00,0x37,0xdb,0x01,0x00,0x00,0x00] # GFX90A: ds_gws_sema_br a2 gds ; encoding: [0x00,0x00,0x37,0xdb,0x02,0x00,0x00,0x00]
0x00,0x00,0x37,0xdb,0x01,0x00,0x00,0x00 0x00,0x00,0x37,0xdb,0x02,0x00,0x00,0x00
# GFX90A: ds_gws_sema_br a1 offset:4 gds ; encoding: [0x04,0x00,0x37,0xdb,0x01,0x00,0x00,0x00] # GFX90A: ds_gws_sema_br a0 offset:4 gds ; encoding: [0x04,0x00,0x37,0xdb,0x00,0x00,0x00,0x00]
0x04,0x00,0x37,0xdb,0x01,0x00,0x00,0x00 0x04,0x00,0x37,0xdb,0x00,0x00,0x00,0x00
# GFX90A: ds_gws_barrier a1 offset:65535 gds ; encoding: [0xff,0xff,0x3b,0xdb,0x01,0x00,0x00,0x00] # GFX90A: ds_gws_barrier a2 offset:65535 gds ; encoding: [0xff,0xff,0x3b,0xdb,0x02,0x00,0x00,0x00]
0xff,0xff,0x3b,0xdb,0x01,0x00,0x00,0x00 0xff,0xff,0x3b,0xdb,0x02,0x00,0x00,0x00
# GFX90A: ds_gws_barrier a255 offset:65535 gds ; encoding: [0xff,0xff,0x3b,0xdb,0xff,0x00,0x00,0x00] # GFX90A: ds_gws_barrier a254 offset:65535 gds ; encoding: [0xff,0xff,0x3b,0xdb,0xfe,0x00,0x00,0x00]
0xff,0xff,0x3b,0xdb,0xff,0x00,0x00,0x00 0xff,0xff,0x3b,0xdb,0xfe,0x00,0x00,0x00
# GFX90A: ds_gws_barrier a1 gds ; encoding: [0x00,0x00,0x3b,0xdb,0x01,0x00,0x00,0x00] # GFX90A: ds_gws_barrier a0 gds ; encoding: [0x00,0x00,0x3b,0xdb,0x00,0x00,0x00,0x00]
0x00,0x00,0x3b,0xdb,0x01,0x00,0x00,0x00 0x00,0x00,0x3b,0xdb,0x00,0x00,0x00,0x00
# GFX90A: ds_gws_barrier a1 gds ; encoding: [0x00,0x00,0x3b,0xdb,0x01,0x00,0x00,0x00] # GFX90A: ds_gws_barrier a2 gds ; encoding: [0x00,0x00,0x3b,0xdb,0x02,0x00,0x00,0x00]
0x00,0x00,0x3b,0xdb,0x01,0x00,0x00,0x00 0x00,0x00,0x3b,0xdb,0x02,0x00,0x00,0x00
# GFX90A: ds_gws_barrier a1 offset:4 gds ; encoding: [0x04,0x00,0x3b,0xdb,0x01,0x00,0x00,0x00] # GFX90A: ds_gws_barrier a2 offset:4 gds ; encoding: [0x04,0x00,0x3b,0xdb,0x02,0x00,0x00,0x00]
0x04,0x00,0x3b,0xdb,0x01,0x00,0x00,0x00 0x04,0x00,0x3b,0xdb,0x02,0x00,0x00,0x00
# GFX90A: ds_consume a5 offset:65535 ; encoding: [0xff,0xff,0x7a,0xdb,0x00,0x00,0x00,0x05] # GFX90A: ds_consume a5 offset:65535 ; encoding: [0xff,0xff,0x7a,0xdb,0x00,0x00,0x00,0x05]
0xff,0xff,0x7a,0xdb,0x00,0x00,0x00,0x05 0xff,0xff,0x7a,0xdb,0x00,0x00,0x00,0x05
# GFX90A: ds_consume a255 offset:65535 ; encoding: [0xff,0xff,0x7a,0xdb,0x00,0x00,0x00,0xff] # GFX90A: ds_consume a255 offset:65535 ; encoding: [0xff,0xff,0x7a,0xdb,0x00,0x00,0x00,0xff]
0xff,0xff,0x7a,0xdb,0x00,0x00,0x00,0xff 0xff,0xff,0x7a,0xdb,0x00,0x00,0x00,0xff
# GFX90A: ds_consume a5 ; encoding: [0x00,0x00,0x7a,0xdb,0x00,0x00,0x00,0x05] # GFX90A: ds_consume a5 ; encoding: [0x00,0x00,0x7a,0xdb,0x00,0x00,0x00,0x05]
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