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[AMDGPU][MC][GFX90A] Corrected DS_GWS opcodes
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Authored by dp on May 26 2021, 10:08 AM.

Details

Summary

It turned out that DS_GWS opcodes must use even aligned registers.

A separate change is needed to address the issue in codegen.

Diff Detail

Event Timeline

dp created this revision.May 26 2021, 10:08 AM
dp requested review of this revision.May 26 2021, 10:08 AM
Herald added a project: Restricted Project. · View Herald TranscriptMay 26 2021, 10:08 AM
rampitec accepted this revision.May 26 2021, 10:12 AM

LGTM. I am finishing the patch for the copdegen.

This revision is now accepted and ready to land.May 26 2021, 10:12 AM
This revision was landed with ongoing or failed builds.May 26 2021, 11:32 AM
This revision was automatically updated to reflect the committed changes.
foad added inline comments.May 27 2021, 1:47 AM
llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
4125

Typo "VGRP". I guess it was copied from elsewhere in this file.

dp marked an inline comment as done.May 27 2021, 5:48 AM
dp added inline comments.
llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
4125

Thanks Jay! I'll fix these typos on next commit.