[MSan] Set zeroext on call arguments to msan functions with zeroext parameter attribute

[aeubanks]

Summary

ABI attributes need to match between the caller and callee.

[rnk]

lgtm

llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp

1184

I suggest CB->addParamAttr as a shorter spelling for the same stuff. I noticed DFSan does it that way.

llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp

void storeOrigin(IRBuilder<> &IRB, Value *Addr, Value *Shadow, Value *Origin,
     }
 
     unsigned TypeSizeInBits = DL.getTypeSizeInBits(ConvertedShadow->getType());
     unsigned SizeIndex = TypeSizeToSizeIndex(TypeSizeInBits);
     if (AsCall && SizeIndex < kNumberOfAccessSizes && !MS.CompileKernel) {
       FunctionCallee Fn = MS.MaybeStoreOriginFn[SizeIndex];
       Value *ConvertedShadow2 =
           IRB.CreateZExt(ConvertedShadow, IRB.getIntNTy(8 * (1 << SizeIndex)));
-      IRB.CreateCall(Fn,
-                     {ConvertedShadow2,
-                      IRB.CreatePointerCast(Addr, IRB.getInt8PtrTy()), Origin});
+      CallBase *CB = IRB.CreateCall(
+          Fn, {ConvertedShadow2,
+      CB->addAttribute(AttributeList::FirstArgIndex, Attribute::ZExt);
+      CB->addAttribute(AttributeList::FirstArgIndex + 2, Attribute::ZExt);
     } else {
       Value *Cmp = convertToBool(ConvertedShadow, IRB, "_mscmp");
       Instruction *CheckTerm = SplitBlockAndInsertIfThen(
           Cmp, &*IRB.GetInsertPoint(), false, MS.OriginStoreWeights);
       IRBuilder<> IRBNew(CheckTerm);
       paintOrigin(IRBNew, updateOrigin(Origin, IRBNew), OriginPtr, StoreSize,
                   OriginAlignment);
     }
void materializeOneCheck(Instruction *OrigIns, Value *Shadow, Value *Origin,
     const DataLayout &DL = OrigIns->getModule()->getDataLayout();
 
     unsigned TypeSizeInBits = DL.getTypeSizeInBits(ConvertedShadow->getType());
     unsigned SizeIndex = TypeSizeToSizeIndex(TypeSizeInBits);
     if (AsCall && SizeIndex < kNumberOfAccessSizes && !MS.CompileKernel) {
       FunctionCallee Fn = MS.MaybeWarningFn[SizeIndex];
       Value *ConvertedShadow2 =
           IRB.CreateZExt(ConvertedShadow, IRB.getIntNTy(8 * (1 << SizeIndex)));
-      IRB.CreateCall(Fn, {ConvertedShadow2, MS.TrackOrigins && Origin
-                                                ? Origin
-                                                : (Value *)IRB.getInt32(0)});
+      CallBase *CB = IRB.CreateCall(
+          Fn, {ConvertedShadow2,
+               MS.TrackOrigins && Origin ? Origin : (Value *)IRB.getInt32(0)});
+      CB->addAttribute(AttributeList::FirstArgIndex, Attribute::ZExt);
+      CB->addAttribute(AttributeList::FirstArgIndex + 1, Attribute::ZExt);
     } else {
       Value *Cmp = convertToBool(ConvertedShadow, IRB, "_mscmp");
       Instruction *CheckTerm = SplitBlockAndInsertIfThen(
           Cmp, OrigIns,
           /* Unreachable */ !MS.Recover, MS.ColdCallWeights);
 
       IRB.SetInsertPoint(CheckTerm);
       insertWarningFn(IRB, Origin);

llvm/test/Instrumentation/MemorySanitizer/instrumentation-with-call-threshold.ll

 }
 
 declare void @foo(...)
 
 ; CHECK-LABEL: @LoadAndCmp
 ; CHECK: = load
 ; CHECK: = load
 ; CHECK: = zext i1 {{.*}} to i8
-; CHECK: call void @__msan_maybe_warning_1(
+; CHECK: call void @__msan_maybe_warning_1(i8 zeroext {{.*}}, i32 zeroext {{.*}})
 ; CHECK-NOT: unreachable
 ; CHECK: ret void
 
 
 define void @Store(i64* nocapture %p, i64 %x) nounwind uwtable sanitize_memory {
 entry:
   store i64 %x, i64* %p, align 4
   ret void
 }
 
 ; CHECK-LABEL: @Store
 ; CHECK: load {{.*}} @__msan_param_tls
 ; CHECK-ORIGINS: load {{.*}} @__msan_param_origin_tls
 ; CHECK: store
 ; CHECK-ORIGINS-NOT: __msan_chain_origin
 ; CHECK-ORIGINS: bitcast i64* {{.*}} to i8*
 ; CHECK-ORIGINS-NOT: __msan_chain_origin
-; CHECK-ORIGINS: call void @__msan_maybe_store_origin_8(
+; CHECK-ORIGINS: call void @__msan_maybe_store_origin_8(i64 zeroext {{.*}}, i8* {{.*}}, i32 zeroext {{.*}})
 ; CHECK-ORIGINS-NOT: __msan_chain_origin
 ; CHECK: store i64
 ; CHECK: ret void

llvm/test/Instrumentation/MemorySanitizer/with-call-type-size.ll

 ; RUN: opt < %s -msan-instrumentation-with-call-threshold=0 -S -passes=msan    \
 ; RUN: 2>&1 | FileCheck %s
 ; RUN: opt < %s -msan -msan-instrumentation-with-call-threshold=0 -S | FileCheck %s
 
 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
 target triple = "x86_64-unknown-linux-gnu"
 
 define <4 x i32> @test1(<4 x i32> %vec, i1 %idx, i32 %x) sanitize_memory {
   %vec1 = insertelement <4 x i32> %vec, i32 %x, i1 %idx
   ret <4 x i32> %vec1
 }
 ; CHECK-LABEL: @test1(
 ; CHECK:         %[[A:.*]] = zext i1 {{.*}} to i8
-; CHECK:         call void @__msan_maybe_warning_1(i8 %[[A]], i32 0)
+; CHECK:         call void @__msan_maybe_warning_1(i8 zeroext %[[A]], i32 zeroext 0)
 ; CHECK:         ret <4 x i32>
 
 define <4 x i32> @test2(<4 x i32> %vec, i2 %idx, i32 %x) sanitize_memory {
   %vec1 = insertelement <4 x i32> %vec, i32 %x, i2 %idx
   ret <4 x i32> %vec1
 }
 ; CHECK-LABEL: @test2(
 ; CHECK:         %[[A:.*]] = zext i2 {{.*}} to i8
-; CHECK:         call void @__msan_maybe_warning_1(i8 %[[A]], i32 0)
+; CHECK:         call void @__msan_maybe_warning_1(i8 zeroext %[[A]], i32 zeroext 0)
 ; CHECK:         ret <4 x i32>
 
 define <4 x i32> @test8(<4 x i32> %vec, i8 %idx, i32 %x) sanitize_memory {
   %vec1 = insertelement <4 x i32> %vec, i32 %x, i8 %idx
   ret <4 x i32> %vec1
 }
 ; CHECK-LABEL: @test8(
 ; zext i8 -> i8 unnecessary.
-; CHECK:         call void @__msan_maybe_warning_1(i8 %{{.*}}, i32 0)
+; CHECK:         call void @__msan_maybe_warning_1(i8 zeroext %{{.*}}, i32 zeroext 0)
 ; CHECK:         ret <4 x i32>
 
 define <4 x i32> @test9(<4 x i32> %vec, i9 %idx, i32 %x) sanitize_memory {
   %vec1 = insertelement <4 x i32> %vec, i32 %x, i9 %idx
   ret <4 x i32> %vec1
 }
 ; CHECK-LABEL: @test9(
 ; CHECK:         %[[A:.*]] = zext i9 {{.*}} to i16
-; CHECK:         call void @__msan_maybe_warning_2(i16 %[[A]], i32 0)
+; CHECK:         call void @__msan_maybe_warning_2(i16 zeroext %[[A]], i32 zeroext 0)
 ; CHECK:         ret <4 x i32>
 
 define <4 x i32> @test16(<4 x i32> %vec, i16 %idx, i32 %x) sanitize_memory {
   %vec1 = insertelement <4 x i32> %vec, i32 %x, i16 %idx
   ret <4 x i32> %vec1
 }
 ; CHECK-LABEL: @test16(
-; CHECK:         call void @__msan_maybe_warning_2(i16 %{{.*}}, i32 0)
+; CHECK:         call void @__msan_maybe_warning_2(i16 zeroext %{{.*}}, i32 zeroext 0)
 ; CHECK:         ret <4 x i32>
 
 define <4 x i32> @test17(<4 x i32> %vec, i17 %idx, i32 %x) sanitize_memory {
   %vec1 = insertelement <4 x i32> %vec, i32 %x, i17 %idx
   ret <4 x i32> %vec1
 }
 ; CHECK-LABEL: @test17(
 ; CHECK:         %[[A:.*]] = zext i17 {{.*}} to i32
-; CHECK:         call void @__msan_maybe_warning_4(i32 %[[A]], i32 0)
+; CHECK:         call void @__msan_maybe_warning_4(i32 zeroext %[[A]], i32 zeroext 0)
 ; CHECK:         ret <4 x i32>
 
 define <4 x i32> @test42(<4 x i32> %vec, i42 %idx, i32 %x) sanitize_memory {
   %vec1 = insertelement <4 x i32> %vec, i32 %x, i42 %idx
   ret <4 x i32> %vec1
 }
 ; CHECK-LABEL: @test42(
 ; CHECK:         %[[A:.*]] = zext i42 {{.*}} to i64
-; CHECK:         call void @__msan_maybe_warning_8(i64 %[[A]], i32 0)
+; CHECK:         call void @__msan_maybe_warning_8(i64 zeroext %[[A]], i32 zeroext 0)
 ; CHECK:         ret <4 x i32>
 
 define <4 x i32> @test64(<4 x i32> %vec, i64 %idx, i32 %x) sanitize_memory {
   %vec1 = insertelement <4 x i32> %vec, i32 %x, i64 %idx
   ret <4 x i32> %vec1
 }
 ; CHECK-LABEL: @test64(
-; CHECK:         call void @__msan_maybe_warning_8(i64 %{{.*}}, i32 0)
+; CHECK:         call void @__msan_maybe_warning_8(i64 zeroext %{{.*}}, i32 zeroext 0)
 ; CHECK:         ret <4 x i32>
 
 ; Type size too large => inline check.
 define <4 x i32> @test65(<4 x i32> %vec, i65 %idx, i32 %x) sanitize_memory {
   %vec1 = insertelement <4 x i32> %vec, i32 %x, i65 %idx
   ret <4 x i32> %vec1
 }
 ; CHECK-LABEL: @test65(
 ; CHECK-NOT:     call void @__msan_maybe_warning_
 ; CHECK:         icmp ne i65 %{{.*}}, 0
 ; CHECK-NOT:     call void @__msan_maybe_warning_
 ; CHECK:         ret <4 x i32>