[AMDGPU] Set unused dst_sel to '?' in the encoding

[rampitec]

Summary

This is to allow disasm with any bits in the unused fields.

[dp]

LGTM

llvm/lib/Target/AMDGPU/VOPInstructions.td

class VOP_SDWAe<VOPProfile P> : Enc64 {
   bits<2> src0_modifiers; // float: {abs,neg}, int {sext}
   bits<3> src1_sel;
   bits<2> src1_modifiers;
   bits<3> dst_sel;
   bits<2> dst_unused;
   bits<1> clamp;
 
   let Inst{39-32} = !if(P.HasSrc0, src0{7-0}, 0);
-  let Inst{42-40} = !if(P.EmitDstSel, dst_sel{2-0}, 0);
-  let Inst{44-43} = !if(P.EmitDstSel, dst_unused{1-0}, 0);
+  let Inst{42-40} = !if(P.EmitDstSel, dst_sel{2-0}, ?);
+  let Inst{44-43} = !if(P.EmitDstSel, dst_unused{1-0}, ?);
   let Inst{45}    = !if(P.HasSDWAClamp, clamp{0}, 0);
   let Inst{50-48} = !if(P.HasSrc0, src0_sel{2-0}, 0);
   let Inst{51}    = !if(P.HasSrc0IntMods, src0_modifiers{0}, 0);
   let Inst{53-52} = !if(P.HasSrc0FloatMods, src0_modifiers{1-0}, 0);
   let Inst{58-56} = !if(P.HasSrc1, src1_sel{2-0}, 0);
   let Inst{59}    = !if(P.HasSrc1IntMods, src1_modifiers{0}, 0);
   let Inst{61-60} = !if(P.HasSrc1FloatMods, src1_modifiers{1-0}, 0);
 }

 
 // gfx9 SDWA-A
 class VOP_SDWA9Ae<VOPProfile P> : VOP_SDWA9e<P> {
   bits<3> dst_sel;
   bits<2> dst_unused;
   bits<1> clamp;
   bits<2> omod;
 
-  let Inst{42-40} = !if(P.EmitDstSel, dst_sel{2-0}, 0);
-  let Inst{44-43} = !if(P.EmitDstSel, dst_unused{1-0}, 0);
+  let Inst{42-40} = !if(P.EmitDstSel, dst_sel{2-0}, ?);
+  let Inst{44-43} = !if(P.EmitDstSel, dst_unused{1-0}, ?);
   let Inst{45}    = !if(P.HasSDWAClamp, clamp{0}, 0);
   let Inst{47-46} = !if(P.HasSDWAOMod, omod{1-0}, 0);
 }
 
 // gfx9 SDWA-B
 class VOP_SDWA9Be<VOPProfile P> : VOP_SDWA9e<P> {
   bits<8> sdst; // {vcc_sdst{0}, sdst{6-0}}
 

llvm/test/MC/Disassembler/AMDGPU/sdwa_gfx9.txt

 0xf9 0x04 0xba 0x7d 0x01 0x00 0x02 0x04
 
 # GFX9: v_cmp_class_f32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:WORD_0 ; encoding: [0xf9,0x04,0x20,0x7c,0x01,0x00,0x02,0x04]
 0xf9 0x04 0x20 0x7c 0x01 0x00 0x02 0x04
 
 # GFX9: v_cmpx_class_f32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:WORD_0 ; encoding: [0xf9,0x04,0x22,0x7c,0x01,0x00,0x02,0x04]
 0xf9 0x04 0x22 0x7c 0x01 0x00 0x02 0x04
 
+# GFX9: v_cmp_lt_f32_sdwa vcc, v2, v4 src0_sel:BYTE_1 src1_sel:DWORD ; encoding: [0xf9,0x08,0x82,0x7c,0x02,0x00,0x01,0x06]
+0xf9,0x08,0x82,0x7c,0x02,0x00,0x01,0x06
+
+# GFX9: v_cmp_lt_f32_sdwa vcc, v2, v4 src0_sel:BYTE_1 src1_sel:DWORD ; encoding: [0xf9,0x08,0x82,0x7c,0x02,0x00,0x01,0x06]
+0xf9,0x08,0x82,0x7c,0x02,0x06,0x01,0x06
+
 #-----------------------------------------------------------------------------#
 # Modifiers
 #-----------------------------------------------------------------------------#
 
 # GFX9: v_fract_f32_sdwa v0, |v0| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 ; encoding: [0xf9,0x36,0x00,0x7e,0x00,0x06,0x25,0x00]
 0xf9 0x36 0x00 0x7e 0x00 0x06 0x25 0x00
 
 # GFX9: v_sin_f32_sdwa v0, -|v0| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 ; encoding: [0xf9,0x52,0x00,0x7e,0x00,0x06,0x35,0x00]

llvm/test/MC/Disassembler/AMDGPU/sdwa_vi.txt

 # VI: v_subb_u32_sdwa v1, vcc, v2, v3, vcc  dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x06,0x02,0x3a,0x02,0x06,0x05,0x02]
 0xf9 0x06 0x02 0x3a 0x02 0x06 0x05 0x02
 
 # VI: v_subbrev_u32_sdwa v1, vcc, v2, v3, vcc  dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x06,0x02,0x3c,0x02,0x06,0x05,0x02]
 0xf9 0x06 0x02 0x3c 0x02 0x06 0x05 0x02
 
 # VI: v_cndmask_b32_sdwa v5, v1, v2, vcc dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x0a,0x00,0x01,0x00,0x06,0x06]
 0xf9,0x04,0x0a,0x00,0x01,0x00,0x06,0x06
+
+# VI: v_cmp_lt_f32 vcc, v2, v4 src0_sel:BYTE_1 src1_sel:DWORD ; encoding: [0xf9,0x08,0x82,0x7c,0x02,0x00,0x01,0x06]
+0xf9,0x08,0x82,0x7c,0x02,0x00,0x01,0x06
+
+# VI: v_cmp_lt_f32 vcc, v2, v4 src0_sel:BYTE_1 src1_sel:DWORD ; encoding: [0xf9,0x08,0x82,0x7c,0x02,0x00,0x01,0x06]
+0xf9,0x08,0x82,0x7c,0x02,0x06,0x01,0x06