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Differential D102503

Fix some typos.
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Authored by Benoit on May 14 2021, 8:43 AM.

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ftynse
nicolasvasilache
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rGe0a88db545b6: Fix some typos.
Summary

Fix some typos

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Benoit created this revision.May 14 2021, 8:43 AM
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nicolasvasilache accepted this revision.May 14 2021, 8:46 AM
This revision is now accepted and ready to land.May 14 2021, 8:46 AM
This revision was landed with ongoing or failed builds.May 14 2021, 9:05 AM
Closed by commit rGe0a88db545b6: Fix some typos. (authored by Benoit, committed by xgupta). · Explain Why
This revision was automatically updated to reflect the committed changes.
xgupta added a commit: rGe0a88db545b6: Fix some typos..
Harbormaster completed remote builds in B104509: Diff 345451.May 14 2021, 9:33 AM

Revision Contents

PathSize
mlir/
include/
mlir/
Dialect/
ArmNeon/
2 lines
test/
Target/
LLVMIR/
8 lines

Diff 345455

mlir/include/mlir/Dialect/ArmNeon/ArmNeon.td

Show First 20 Lines • Show All 102 Lines • ▼ Show 20 Lines let description = [{
the following operation on signed integer vectors: res = dot(b, c) + a, the following operation on signed integer vectors: res = dot(b, c) + a,
where vector operands are partitioned into groups of four elements. where vector operands are partitioned into groups of four elements.
Source: Source:
https://developer.arm.com/architectures/instruction-sets/simd-isas/neon/intrinsics https://developer.arm.com/architectures/instruction-sets/simd-isas/neon/intrinsics
}]; }];
// Supports either: // Supports either:
// (vector<2xi32>, vector<8xi8>, vector<8xi8>) -> vector<2xi32> // (vector<2xi32>, vector<8xi8>, vector<8xi8>) -> vector<2xi32>
// (vector<4xi32>, vector<16xi8>, vector<16xi8>) -> vector<16xi32> // (vector<4xi32>, vector<16xi8>, vector<16xi8>) -> vector<4xi32>
let arguments = (ins VectorOfLengthAndType<[4, 2], [I32]>:$a, let arguments = (ins VectorOfLengthAndType<[4, 2], [I32]>:$a,
VectorOfLengthAndType<[16, 8], [I8]>:$b, VectorOfLengthAndType<[16, 8], [I8]>:$b,
VectorOfLengthAndType<[16, 8], [I8]>:$c); VectorOfLengthAndType<[16, 8], [I8]>:$c);
let results = (outs VectorOfLengthAndType<[4, 2], [I32]>:$res); let results = (outs VectorOfLengthAndType<[4, 2], [I32]>:$res);
let assemblyFormat = let assemblyFormat =
"$a `,` $b `,` $c attr-dict `:` type($b) `,` type($c) `to` type($res)"; "$a `,` $b `,` $c attr-dict `:` type($b) `,` type($c) `to` type($res)";
} }
#endif // ARMNEON_OPS #endif // ARMNEON_OPS

mlir/test/Target/LLVMIR/arm-neon.mlir

Show All 18 Linesllvm.func @arm_neon_smull(%arg0: vector<8xi8>, %arg1: vector<8xi8>) -> !llvm.struct<(vector<8xi16>, vector<4xi32>, vector<2xi64>)> {
%6 = llvm.insertvalue %0, %5[0] : !llvm.struct<(vector<8xi16>, vector<4xi32>, vector<2xi64>)> %6 = llvm.insertvalue %0, %5[0] : !llvm.struct<(vector<8xi16>, vector<4xi32>, vector<2xi64>)>
%7 = llvm.insertvalue %2, %6[1] : !llvm.struct<(vector<8xi16>, vector<4xi32>, vector<2xi64>)> %7 = llvm.insertvalue %2, %6[1] : !llvm.struct<(vector<8xi16>, vector<4xi32>, vector<2xi64>)>
%8 = llvm.insertvalue %4, %7[2] : !llvm.struct<(vector<8xi16>, vector<4xi32>, vector<2xi64>)> %8 = llvm.insertvalue %4, %7[2] : !llvm.struct<(vector<8xi16>, vector<4xi32>, vector<2xi64>)>
// CHECK: ret { <8 x i16>, <4 x i32>, <2 x i64> } // CHECK: ret { <8 x i16>, <4 x i32>, <2 x i64> }
llvm.return %8 : !llvm.struct<(vector<8xi16>, vector<4xi32>, vector<2xi64>)> llvm.return %8 : !llvm.struct<(vector<8xi16>, vector<4xi32>, vector<2xi64>)>
} }
// CHECK-LABEL: arm_neon_sdot_i8i8 // CHECK-LABEL: arm_neon_sdot_8_i8i8
llvm.func @arm_neon_sdot_i8i8(%a: vector<2xi32>, %b: vector<8xi8>, %c: vector<8xi8>) -> vector<2xi32> { llvm.func @arm_neon_sdot_8_i8i8(%a: vector<2xi32>, %b: vector<8xi8>, %c: vector<8xi8>) -> vector<2xi32> {
// CHECK: %[[V0:.*]] = call <2 x i32> @llvm.aarch64.neon.sdot.v2i32.v8i8(<2 x i32> %{{.*}}, <8 x i8> %{{.*}}, <8 x i8> %{{.*}}) // CHECK: %[[V0:.*]] = call <2 x i32> @llvm.aarch64.neon.sdot.v2i32.v8i8(<2 x i32> %{{.*}}, <8 x i8> %{{.*}}, <8 x i8> %{{.*}})
// CHECK-NEXT: ret <2 x i32> // CHECK-NEXT: ret <2 x i32>
%0 = arm_neon.intr.sdot %a, %b, %c : vector<8xi8>, vector<8xi8> to vector<2xi32> %0 = arm_neon.intr.sdot %a, %b, %c : vector<8xi8>, vector<8xi8> to vector<2xi32>
llvm.return %0 : vector<2xi32> llvm.return %0 : vector<2xi32>
} }
// CHECK-LABEL: arm_neon_sdot_i16i16 // CHECK-LABEL: arm_neon_sdot_16_i8i8
llvm.func @arm_neon_sdot_i16i16(%a: vector<4xi32>, %b: vector<16xi8>, %c: vector<16xi8>) -> vector<4xi32> { llvm.func @arm_neon_sdot_16_i8i8(%a: vector<4xi32>, %b: vector<16xi8>, %c: vector<16xi8>) -> vector<4xi32> {
// CHECK: %[[V0:.*]] = call <4 x i32> @llvm.aarch64.neon.sdot.v4i32.v16i8(<4 x i32> %{{.*}}, <16 x i8> %{{.*}}, <16 x i8> %{{.*}}) // CHECK: %[[V0:.*]] = call <4 x i32> @llvm.aarch64.neon.sdot.v4i32.v16i8(<4 x i32> %{{.*}}, <16 x i8> %{{.*}}, <16 x i8> %{{.*}})
// CHECK-NEXT: ret <4 x i32> // CHECK-NEXT: ret <4 x i32>
%0 = arm_neon.intr.sdot %a, %b, %c : vector<16xi8>, vector<16xi8> to vector<4xi32> %0 = arm_neon.intr.sdot %a, %b, %c : vector<16xi8>, vector<16xi8> to vector<4xi32>
llvm.return %0 : vector<4xi32> llvm.return %0 : vector<4xi32>
} }