[llvm-mc][AArch64] HINT instruction disassembled as BTI

[labrinea]

Summary

The Arm Architecture Reference Manual says that the SystemHintOp_BTI opcode is prefered when CRm:op2 matches 0100:xx0, but llvm-mc currently accepts 0100:xxx, which isn't right.

[ostannard]

LGTM

[labrinea]

Thanks, Oliver!

llvm/lib/Target/AArch64/AArch64InstrFormats.td

 }
 def btihint_op : Operand<i32> {
   let ParserMatchClass = BTIHintOperand;
   let PrintMethod = "printBTIHintOp";
   let MCOperandPredicate = [{
     // "bti" is an alias to "hint" only for certain values of CRm:Op2 fields.
     if (!MCOp.isImm())
       return false;
-    return AArch64BTIHint::lookupBTIByEncoding((MCOp.getImm() ^ 32) >> 1) != nullptr;
+    return AArch64BTIHint::lookupBTIByEncoding(MCOp.getImm() ^ 32) != nullptr;
   }];
 }
 
 class MRSI : RtSystemI<1, (outs GPR64:$Rt), (ins mrs_sysreg_op:$systemreg),
                        "mrs", "\t$Rt, $systemreg"> {
   bits<16> systemreg;
   let Inst{20-5} = systemreg;
   let DecoderNamespace = "Fallback";

llvm/lib/Target/AArch64/AArch64SystemOperands.td

 }
 
 def : PSB<"csync", 0x11>;
 
 //===----------------------------------------------------------------------===//
 // BTI instruction options.
 //===----------------------------------------------------------------------===//
 
-class BTI<string name, bits<2> encoding> : SearchableTable {
+class BTI<string name, bits<3> encoding> : SearchableTable {
   let SearchableFields = ["Name", "Encoding"];
   let EnumValueField = "Encoding";
 
   string Name = name;
-  bits<2> Encoding;
+  bits<3> Encoding;
   let Encoding = encoding;
 }
 
-def : BTI<"c",  0b01>;
-def : BTI<"j",  0b10>;
-def : BTI<"jc", 0b11>;
+def : BTI<"c",  0b010>;
+def : BTI<"j",  0b100>;
+def : BTI<"jc", 0b110>;
 
 //===----------------------------------------------------------------------===//
 // TLBI (translation lookaside buffer invalidate) instruction options.
 //===----------------------------------------------------------------------===//
 
 class TLBIEntry<string name, bits<3> op1, bits<4> crn, bits<4> crm,
              bits<3> op2, bit needsreg> {
   string Name = name;

llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp

static std::unique_ptr<AArch64Operand> CreatePSBHint(unsigned Val,
     return Op;
   }
 
   static std::unique_ptr<AArch64Operand> CreateBTIHint(unsigned Val,
                                                        StringRef Str,
                                                        SMLoc S,
                                                        MCContext &Ctx) {
     auto Op = std::make_unique<AArch64Operand>(k_BTIHint, Ctx);
-    Op->BTIHint.Val = Val << 1 | 32;
+    Op->BTIHint.Val = Val | 32;
     Op->BTIHint.Data = Str.data();
     Op->BTIHint.Length = Str.size();
     Op->StartLoc = S;
     Op->EndLoc = S;
     return Op;
   }
 
   static std::unique_ptr<AArch64Operand>

llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp

if (PSB)
     O << PSB->Name;
   else
     O << '#' << formatImm(psbhintop);
 }
 
 void AArch64InstPrinter::printBTIHintOp(const MCInst *MI, unsigned OpNum,
                                         const MCSubtargetInfo &STI,
                                         raw_ostream &O) {
-  unsigned btihintop = (MI->getOperand(OpNum).getImm() ^ 32) >> 1;
+  unsigned btihintop = MI->getOperand(OpNum).getImm() ^ 32;
   auto BTI = AArch64BTIHint::lookupBTIByEncoding(btihintop);
   if (BTI)
     O << BTI->Name;
   else
     O << '#' << formatImm(btihintop);
 }
 
 void AArch64InstPrinter::printFPImmOperand(const MCInst *MI, unsigned OpNum,

llvm/test/MC/Disassembler/AArch64/armv8.5a-bti.txt

 # RUN: llvm-mc -triple=aarch64 -mattr=+bti   -disassemble < %s      | FileCheck %s
 # RUN: llvm-mc -triple=aarch64 -mattr=+v8.5a -disassemble < %s      | FileCheck %s
 # RUN: llvm-mc -triple=aarch64 -mattr=-bti   -disassemble < %s 2>&1 | FileCheck %s --check-prefix=NOBTI
 
 [0x1f 0x24 0x03 0xd5]
 [0x5f 0x24 0x03 0xd5]
 [0x9f 0x24 0x03 0xd5]
 [0xdf 0x24 0x03 0xd5]
 
+[0x3f 0x24 0x03 0xd5]
+[0x7f 0x24 0x03 0xd5]
+[0xbf 0x24 0x03 0xd5]
+[0xff 0x24 0x03 0xd5]
+
 # CHECK: bti
 # CHECK: bti c
 # CHECK: bti j
 # CHECK: bti jc
 
+# CHECK: hint #33
+# CHECK: hint #35
+# CHECK: hint #37
+# CHECK: hint #39
+
 # NOBTI: hint #32
 # NOBTI: hint #34
 # NOBTI: hint #36
 # NOBTI: hint #38
+
+# NOBTI: hint #33
+# NOBTI: hint #35
+# NOBTI: hint #37
+# NOBTI: hint #39