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Differential D102111

[AMDGPU] Update SCC defs to VCC when uses are changed to VCC
ClosedPublic

Authored by bcahoon on May 8 2021, 10:50 AM.

Details

Reviewers
arsenm
Commits
rG3f7b7e7393f8: [AMDGPU] Update SCC defs to VCC when uses are changed to VCC
Summary

The FixSGPRCopies pass converts instructions to VALU when
removing illegal VGPR to SGPR copies. Instructions that use SCC
are changed to use VCC instead. When that happens, the pass must
also change instructions that define SCC to VCC.

The pass was not changing the SCC definition when an ADDC is
converted due to a input that is a VGPR to SGPR copy. But, the
initial ADD instruction, which define SCC, is not converted.
This causes a compilation failure due to a use of an undefined
physical register.

This patch adds code that inserts the SCC definition in the
MoveToVALU worklist when a SCC use is converted to a VCC use.

Diff Detail

Event Timeline

bcahoon created this revision.May 8 2021, 10:50 AM
Herald added subscribers: kerbowa, hiraditya, t-tye and 6 others. · View Herald TranscriptMay 8 2021, 10:50 AM
bcahoon requested review of this revision.May 8 2021, 10:50 AM
Herald added a project: Restricted Project. · View Herald TranscriptMay 8 2021, 10:50 AM
Herald added subscribers: llvm-commits, wdng. · View Herald Transcript
Harbormaster completed remote builds in B103329: Diff 343854.May 8 2021, 11:23 AM
arsenm added a comment.May 11 2021, 5:17 PM

Can you add an IR example where this happens? I thought this was a solved problem already

llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
6832–6834

modifiesRegister(VCC)

bcahoon updated this revision to Diff 344643.May 11 2021, 8:33 PM

Use modifyRegister. Added a .ll test case.

Harbormaster completed remote builds in B103925: Diff 344643.May 11 2021, 9:05 PM
dstuttard added a comment.May 13 2021, 2:06 AM

I've got a case where we see this issue as well.

Confirmed that the patch fixes it.

arsenm accepted this revision.May 13 2021, 6:22 PM

This isn't great but I also don't think it's worth putting real effort into improving SIFixSGPRCopies at this point

llvm/test/CodeGen/AMDGPU/urem-change-scc-to-scc.ll
12 ↗(On Diff #344643)

This isn't particularly enlightening. Something in the giant urem expansion triggered this. Can you come up with some IR approximating the situation in the middle?

This revision is now accepted and ready to land.May 13 2021, 6:22 PM
Closed by commit rG3f7b7e7393f8: [AMDGPU] Update SCC defs to VCC when uses are changed to VCC (authored by bcahoon). · Explain WhyMay 14 2021, 3:11 PM
This revision was automatically updated to reflect the committed changes.
bcahoon added a commit: rG3f7b7e7393f8: [AMDGPU] Update SCC defs to VCC when uses are changed to VCC.

Revision Contents

PathSize
llvm/
lib/
Target/
AMDGPU/
2 lines
28 lines
test/
CodeGen/
AMDGPU/
96 lines
74 lines
6 lines
10 lines
14 lines
10 lines

Diff 345573

llvm/lib/Target/AMDGPU/SIInstrInfo.h

Show First 20 Lines • Show All 117 Lines • ▼ Show 20 Lines void movePackToVALU(SetVectorType &Worklist,
MachineInstr &Inst) const; MachineInstr &Inst) const;
void addUsersToMoveToVALUWorklist(Register Reg, MachineRegisterInfo &MRI, void addUsersToMoveToVALUWorklist(Register Reg, MachineRegisterInfo &MRI,
SetVectorType &Worklist) const; SetVectorType &Worklist) const;
void addSCCDefUsersToVALUWorklist(MachineOperand &Op, void addSCCDefUsersToVALUWorklist(MachineOperand &Op,
MachineInstr &SCCDefInst, MachineInstr &SCCDefInst,
SetVectorType &Worklist) const; SetVectorType &Worklist) const;
void addSCCDefsToVALUWorklist(MachineOperand &Op,
SetVectorType &Worklist) const;
const TargetRegisterClass * const TargetRegisterClass *
getDestEquivalentVGPRClass(const MachineInstr &Inst) const; getDestEquivalentVGPRClass(const MachineInstr &Inst) const;
bool checkInstOffsetsDoNotOverlap(const MachineInstr &MIa, bool checkInstOffsetsDoNotOverlap(const MachineInstr &MIa,
const MachineInstr &MIb) const; const MachineInstr &MIb) const;
Register findUsedSGPR(const MachineInstr &MI, int OpIndices[3]) const; Register findUsedSGPR(const MachineInstr &MI, int OpIndices[3]) const;
▲ Show 20 Lines • Show All 1,128 Lines • Show Last 20 Lines

llvm/lib/Target/AMDGPU/SIInstrInfo.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 5,969 Lines • ▼ Show 20 Lines while (!Worklist.empty()) {
// We're just about to add the implicit use / defs of VCC, and we don't want // We're just about to add the implicit use / defs of VCC, and we don't want
// both. // both.
for (unsigned i = Inst.getNumOperands() - 1; i > 0; --i) { for (unsigned i = Inst.getNumOperands() - 1; i > 0; --i) {
MachineOperand &Op = Inst.getOperand(i); MachineOperand &Op = Inst.getOperand(i);
if (Op.isReg() && Op.getReg() == AMDGPU::SCC) { if (Op.isReg() && Op.getReg() == AMDGPU::SCC) {
// Only propagate through live-def of SCC. // Only propagate through live-def of SCC.
if (Op.isDef() && !Op.isDead()) if (Op.isDef() && !Op.isDead())
addSCCDefUsersToVALUWorklist(Op, Inst, Worklist); addSCCDefUsersToVALUWorklist(Op, Inst, Worklist);
if (Op.isUse())
addSCCDefsToVALUWorklist(Op, Worklist);
Inst.RemoveOperand(i); Inst.RemoveOperand(i);
} }
} }
if (Opcode == AMDGPU::S_SEXT_I32_I8 || Opcode == AMDGPU::S_SEXT_I32_I16) { if (Opcode == AMDGPU::S_SEXT_I32_I8 || Opcode == AMDGPU::S_SEXT_I32_I16) {
// We are converting these to a BFE, so we need to add the missing // We are converting these to a BFE, so we need to add the missing
// operands for the size and offset. // operands for the size and offset.
unsigned Size = (Opcode == AMDGPU::S_SEXT_I32_I8) ? 8 : 16; unsigned Size = (Opcode == AMDGPU::S_SEXT_I32_I8) ? 8 : 16;
▲ Show 20 Lines • Show All 819 Lines • ▼ Show 20 Linesvoid SIInstrInfo::addSCCDefUsersToVALUWorklist(MachineOperand &Op,
if (SCCUsedImplicitly) { if (SCCUsedImplicitly) {
BuildMI(*SCCDefInst.getParent(), std::next(SCCDefInst.getIterator()), BuildMI(*SCCDefInst.getParent(), std::next(SCCDefInst.getIterator()),
SCCDefInst.getDebugLoc(), get(AMDGPU::COPY), AMDGPU::SCC) SCCDefInst.getDebugLoc(), get(AMDGPU::COPY), AMDGPU::SCC)
.addReg(RI.getVCC()); .addReg(RI.getVCC());
} }
} }
// Instructions that use SCC may be converted to VALU instructions. When that
// happens, the SCC register is changed to VCC_LO. The instruction that defines
// SCC must be changed to an instruction that defines VCC. This function makes
// sure that the instruction that defines SCC is added to the moveToVALU
// worklist.
void SIInstrInfo::addSCCDefsToVALUWorklist(MachineOperand &Op,
SetVectorType &Worklist) const {
assert(Op.isReg() && Op.getReg() == AMDGPU::SCC && Op.isUse());
MachineInstr *SCCUseInst = Op.getParent();
// Look for a preceeding instruction that either defines VCC or SCC. If VCC
// then there is nothing to do because the defining instruction has been
// converted to a VALU already. If SCC then that instruction needs to be
// converted to a VALU.
for (MachineInstr &MI :
make_range(std::next(MachineBasicBlock::reverse_iterator(SCCUseInst)),
SCCUseInst->getParent()->rend())) {
if (MI.modifiesRegister(AMDGPU::VCC, &RI))
break;
if (MI.definesRegister(AMDGPU::SCC, &RI)) {
arsenmUnsubmitted
Not Done
ReplyInline Actions

modifiesRegister(VCC)

arsenm: modifiesRegister(VCC)
Worklist.insert(&MI);
break;
}
}
}
const TargetRegisterClass *SIInstrInfo::getDestEquivalentVGPRClass( const TargetRegisterClass *SIInstrInfo::getDestEquivalentVGPRClass(
const MachineInstr &Inst) const { const MachineInstr &Inst) const {
const TargetRegisterClass *NewDstRC = getOpRegClass(Inst, 0); const TargetRegisterClass *NewDstRC = getOpRegClass(Inst, 0);
switch (Inst.getOpcode()) { switch (Inst.getOpcode()) {
// For target instructions, getOpRegClass just returns the virtual register // For target instructions, getOpRegClass just returns the virtual register
// class associated with the operand, so we need to find an equivalent VGPR // class associated with the operand, so we need to find an equivalent VGPR
// register class in order to move the instruction to the VALU. // register class in order to move the instruction to the VALU.
▲ Show 20 Lines • Show All 1,007 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 7,120 Lines • ▼ Show 20 Lines
; GFX6-NEXT: v_mul_hi_u32 v9, v1, v2 ; GFX6-NEXT: v_mul_hi_u32 v9, v1, v2
; GFX6-NEXT: v_mul_lo_u32 v2, v1, v2 ; GFX6-NEXT: v_mul_lo_u32 v2, v1, v2
; GFX6-NEXT: s_movk_i32 s4, 0x11e ; GFX6-NEXT: s_movk_i32 s4, 0x11e
; GFX6-NEXT: v_add_i32_e32 v5, vcc, v6, v5 ; GFX6-NEXT: v_add_i32_e32 v5, vcc, v6, v5
; GFX6-NEXT: v_mul_lo_u32 v6, v1, v3 ; GFX6-NEXT: v_mul_lo_u32 v6, v1, v3
; GFX6-NEXT: v_mul_hi_u32 v3, v1, v3 ; GFX6-NEXT: v_mul_hi_u32 v3, v1, v3
; GFX6-NEXT: v_addc_u32_e32 v4, vcc, v8, v4, vcc ; GFX6-NEXT: v_addc_u32_e32 v4, vcc, v8, v4, vcc
; GFX6-NEXT: s_mov_b32 s10, -1 ; GFX6-NEXT: s_mov_b32 s10, -1
; GFX6-NEXT: v_add_i32_e32 v5, vcc, v6, v5 ; GFX6-NEXT: v_add_i32_e32 v5, vcc, v5, v6
; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v4, v3, vcc ; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v4, v3, vcc
; GFX6-NEXT: v_addc_u32_e32 v4, vcc, v9, v7, vcc ; GFX6-NEXT: v_addc_u32_e32 v4, vcc, v9, v7, vcc
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2
; GFX6-NEXT: v_add_i32_e64 v0, s[0:1], v0, v2 ; GFX6-NEXT: v_add_i32_e64 v0, s[0:1], v0, v2
; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v8, v4, vcc ; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v8, v4, vcc
; GFX6-NEXT: v_mul_lo_u32 v4, v0, s2 ; GFX6-NEXT: v_mul_lo_u32 v4, v0, s2
; GFX6-NEXT: v_mul_hi_u32 v5, v0, s3 ; GFX6-NEXT: v_mul_hi_u32 v5, v0, s3
; GFX6-NEXT: v_addc_u32_e64 v2, vcc, v1, v3, s[0:1] ; GFX6-NEXT: v_addc_u32_e64 v2, vcc, v1, v3, s[0:1]
Show All 26 Lines
; GFX6-NEXT: v_mul_hi_u32 v3, s6, v0 ; GFX6-NEXT: v_mul_hi_u32 v3, s6, v0
; GFX6-NEXT: v_mul_hi_u32 v4, s6, v1 ; GFX6-NEXT: v_mul_hi_u32 v4, s6, v1
; GFX6-NEXT: v_mul_hi_u32 v5, s7, v1 ; GFX6-NEXT: v_mul_hi_u32 v5, s7, v1
; GFX6-NEXT: v_mul_lo_u32 v1, s7, v1 ; GFX6-NEXT: v_mul_lo_u32 v1, s7, v1
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2
; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v8, v4, vcc ; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v8, v4, vcc
; GFX6-NEXT: v_mul_lo_u32 v4, s7, v0 ; GFX6-NEXT: v_mul_lo_u32 v4, s7, v0
; GFX6-NEXT: v_mul_hi_u32 v0, s7, v0 ; GFX6-NEXT: v_mul_hi_u32 v0, s7, v0
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v4, v2 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v4
; GFX6-NEXT: v_addc_u32_e32 v0, vcc, v3, v0, vcc ; GFX6-NEXT: v_addc_u32_e32 v0, vcc, v3, v0, vcc
; GFX6-NEXT: v_addc_u32_e32 v2, vcc, v5, v7, vcc ; GFX6-NEXT: v_addc_u32_e32 v2, vcc, v5, v7, vcc
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1 ; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1
; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v8, v2, vcc ; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v8, v2, vcc
; GFX6-NEXT: v_mul_lo_u32 v2, v0, s3 ; GFX6-NEXT: v_mul_lo_u32 v2, v0, s3
; GFX6-NEXT: v_mul_hi_u32 v3, v0, s2 ; GFX6-NEXT: v_mul_hi_u32 v3, v0, s2
; GFX6-NEXT: v_mul_lo_u32 v4, v1, s2 ; GFX6-NEXT: v_mul_lo_u32 v4, v1, s2
; GFX6-NEXT: v_mov_b32_e32 v5, s3 ; GFX6-NEXT: v_mov_b32_e32 v5, s3
▲ Show 20 Lines • Show All 60 Lines • ▼ Show 20 Lines
; GFX9-NEXT: v_mul_lo_u32 v5, v0, v2 ; GFX9-NEXT: v_mul_lo_u32 v5, v0, v2
; GFX9-NEXT: v_mul_hi_u32 v7, v0, v2 ; GFX9-NEXT: v_mul_hi_u32 v7, v0, v2
; GFX9-NEXT: v_mul_hi_u32 v8, v1, v2 ; GFX9-NEXT: v_mul_hi_u32 v8, v1, v2
; GFX9-NEXT: v_mul_lo_u32 v2, v1, v2 ; GFX9-NEXT: v_mul_lo_u32 v2, v1, v2
; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v5 ; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v5
; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v7, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v7, vcc
; GFX9-NEXT: v_mul_lo_u32 v7, v1, v4 ; GFX9-NEXT: v_mul_lo_u32 v7, v1, v4
; GFX9-NEXT: v_mul_hi_u32 v4, v1, v4 ; GFX9-NEXT: v_mul_hi_u32 v4, v1, v4
; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v7, v3 ; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v7
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v5, v4, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v5, v4, vcc
; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v8, v6, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v8, v6, vcc
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v3, v2 ; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v3, v2
; GFX9-NEXT: v_mov_b32_e32 v5, 0 ; GFX9-NEXT: v_mov_b32_e32 v5, 0
; GFX9-NEXT: v_add_co_u32_e64 v0, s[2:3], v0, v2 ; GFX9-NEXT: v_add_co_u32_e64 v0, s[2:3], v0, v2
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v5, v4, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v5, v4, vcc
; GFX9-NEXT: v_addc_co_u32_e64 v2, vcc, v1, v3, s[2:3] ; GFX9-NEXT: v_addc_co_u32_e64 v2, vcc, v1, v3, s[2:3]
; GFX9-NEXT: v_mul_lo_u32 v4, v0, s4 ; GFX9-NEXT: v_mul_lo_u32 v4, v0, s4
Show All 27 Lines
; GFX9-NEXT: v_mul_hi_u32 v4, s6, v1 ; GFX9-NEXT: v_mul_hi_u32 v4, s6, v1
; GFX9-NEXT: v_mul_hi_u32 v7, s7, v1 ; GFX9-NEXT: v_mul_hi_u32 v7, s7, v1
; GFX9-NEXT: v_mul_lo_u32 v1, s7, v1 ; GFX9-NEXT: v_mul_lo_u32 v1, s7, v1
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v3, v2 ; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v3, v2
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v4, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v4, vcc
; GFX9-NEXT: v_mul_lo_u32 v4, s7, v0 ; GFX9-NEXT: v_mul_lo_u32 v4, s7, v0
; GFX9-NEXT: v_mul_hi_u32 v0, s7, v0 ; GFX9-NEXT: v_mul_hi_u32 v0, s7, v0
; GFX9-NEXT: s_mov_b32 s2, 0x976a7377 ; GFX9-NEXT: s_mov_b32 s2, 0x976a7377
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v4, v2 ; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v2, v4
; GFX9-NEXT: v_addc_co_u32_e32 v0, vcc, v3, v0, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v0, vcc, v3, v0, vcc
; GFX9-NEXT: v_addc_co_u32_e32 v2, vcc, v7, v6, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v2, vcc, v7, v6, vcc
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v1 ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v1
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v5, v2, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v5, v2, vcc
; GFX9-NEXT: v_mul_lo_u32 v2, v0, s8 ; GFX9-NEXT: v_mul_lo_u32 v2, v0, s8
; GFX9-NEXT: v_mul_hi_u32 v3, v0, s2 ; GFX9-NEXT: v_mul_hi_u32 v3, v0, s2
; GFX9-NEXT: v_mul_lo_u32 v4, v1, s2 ; GFX9-NEXT: v_mul_lo_u32 v4, v1, s2
; GFX9-NEXT: v_mov_b32_e32 v5, s8 ; GFX9-NEXT: v_mov_b32_e32 v5, s8
▲ Show 20 Lines • Show All 197 Lines • ▼ Show 20 Lines
; GFX6-NEXT: v_mul_lo_u32 v5, v0, v3 ; GFX6-NEXT: v_mul_lo_u32 v5, v0, v3
; GFX6-NEXT: v_mul_hi_u32 v8, v0, v3 ; GFX6-NEXT: v_mul_hi_u32 v8, v0, v3
; GFX6-NEXT: v_mul_hi_u32 v9, v1, v3 ; GFX6-NEXT: v_mul_hi_u32 v9, v1, v3
; GFX6-NEXT: v_mul_lo_u32 v3, v1, v3 ; GFX6-NEXT: v_mul_lo_u32 v3, v1, v3
; GFX6-NEXT: v_add_i32_e32 v5, vcc, v6, v5 ; GFX6-NEXT: v_add_i32_e32 v5, vcc, v6, v5
; GFX6-NEXT: v_addc_u32_e32 v6, vcc, v7, v8, vcc ; GFX6-NEXT: v_addc_u32_e32 v6, vcc, v7, v8, vcc
; GFX6-NEXT: v_mul_lo_u32 v8, v1, v4 ; GFX6-NEXT: v_mul_lo_u32 v8, v1, v4
; GFX6-NEXT: v_mul_hi_u32 v4, v1, v4 ; GFX6-NEXT: v_mul_hi_u32 v4, v1, v4
; GFX6-NEXT: v_add_i32_e32 v5, vcc, v8, v5 ; GFX6-NEXT: v_add_i32_e32 v5, vcc, v5, v8
; GFX6-NEXT: v_addc_u32_e32 v4, vcc, v6, v4, vcc ; GFX6-NEXT: v_addc_u32_e32 v4, vcc, v6, v4, vcc
; GFX6-NEXT: v_addc_u32_e32 v5, vcc, v9, v2, vcc ; GFX6-NEXT: v_addc_u32_e32 v5, vcc, v9, v2, vcc
; GFX6-NEXT: v_add_i32_e32 v3, vcc, v4, v3 ; GFX6-NEXT: v_add_i32_e32 v3, vcc, v4, v3
; GFX6-NEXT: v_add_i32_e64 v0, s[2:3], v0, v3 ; GFX6-NEXT: v_add_i32_e64 v0, s[2:3], v0, v3
; GFX6-NEXT: v_addc_u32_e32 v4, vcc, v7, v5, vcc ; GFX6-NEXT: v_addc_u32_e32 v4, vcc, v7, v5, vcc
; GFX6-NEXT: v_mul_hi_u32 v5, v0, s6 ; GFX6-NEXT: v_mul_hi_u32 v5, v0, s6
; GFX6-NEXT: v_addc_u32_e64 v3, vcc, v1, v4, s[2:3] ; GFX6-NEXT: v_addc_u32_e64 v3, vcc, v1, v4, s[2:3]
; GFX6-NEXT: v_mul_lo_u32 v6, v3, s6 ; GFX6-NEXT: v_mul_lo_u32 v6, v3, s6
Show All 25 Lines
; GFX6-NEXT: v_mul_hi_u32 v5, s10, v1 ; GFX6-NEXT: v_mul_hi_u32 v5, s10, v1
; GFX6-NEXT: v_mul_hi_u32 v6, s11, v1 ; GFX6-NEXT: v_mul_hi_u32 v6, s11, v1
; GFX6-NEXT: v_mul_lo_u32 v1, s11, v1 ; GFX6-NEXT: v_mul_lo_u32 v1, s11, v1
; GFX6-NEXT: v_add_i32_e32 v3, vcc, v4, v3 ; GFX6-NEXT: v_add_i32_e32 v3, vcc, v4, v3
; GFX6-NEXT: v_addc_u32_e32 v4, vcc, v7, v5, vcc ; GFX6-NEXT: v_addc_u32_e32 v4, vcc, v7, v5, vcc
; GFX6-NEXT: v_mul_lo_u32 v5, s11, v0 ; GFX6-NEXT: v_mul_lo_u32 v5, s11, v0
; GFX6-NEXT: v_mul_hi_u32 v0, s11, v0 ; GFX6-NEXT: v_mul_hi_u32 v0, s11, v0
; GFX6-NEXT: s_lshr_b64 s[2:3], s[8:9], 12 ; GFX6-NEXT: s_lshr_b64 s[2:3], s[8:9], 12
; GFX6-NEXT: v_add_i32_e32 v3, vcc, v5, v3 ; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v5
; GFX6-NEXT: v_addc_u32_e32 v0, vcc, v4, v0, vcc ; GFX6-NEXT: v_addc_u32_e32 v0, vcc, v4, v0, vcc
; GFX6-NEXT: v_addc_u32_e32 v2, vcc, v6, v2, vcc ; GFX6-NEXT: v_addc_u32_e32 v2, vcc, v6, v2, vcc
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1 ; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1
; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v7, v2, vcc ; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v7, v2, vcc
; GFX6-NEXT: v_mul_lo_u32 v2, v1, s0 ; GFX6-NEXT: v_mul_lo_u32 v2, v1, s0
; GFX6-NEXT: v_mul_hi_u32 v3, v0, s0 ; GFX6-NEXT: v_mul_hi_u32 v3, v0, s0
; GFX6-NEXT: v_mul_lo_u32 v4, v0, s0 ; GFX6-NEXT: v_mul_lo_u32 v4, v0, s0
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2
▲ Show 20 Lines • Show All 50 Lines • ▼ Show 20 Lines
; GFX9-NEXT: v_mul_lo_u32 v4, v0, v2 ; GFX9-NEXT: v_mul_lo_u32 v4, v0, v2
; GFX9-NEXT: v_mul_hi_u32 v8, v0, v2 ; GFX9-NEXT: v_mul_hi_u32 v8, v0, v2
; GFX9-NEXT: v_mul_hi_u32 v9, v1, v2 ; GFX9-NEXT: v_mul_hi_u32 v9, v1, v2
; GFX9-NEXT: v_mul_lo_u32 v2, v1, v2 ; GFX9-NEXT: v_mul_lo_u32 v2, v1, v2
; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v6, v4 ; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v6, v4
; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, v7, v8, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, v7, v8, vcc
; GFX9-NEXT: v_mul_lo_u32 v8, v1, v3 ; GFX9-NEXT: v_mul_lo_u32 v8, v1, v3
; GFX9-NEXT: v_mul_hi_u32 v3, v1, v3 ; GFX9-NEXT: v_mul_hi_u32 v3, v1, v3
; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v8, v4 ; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v4, v8
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v6, v3, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v6, v3, vcc
; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v9, v5, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v9, v5, vcc
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v3, v2 ; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v3, v2
; GFX9-NEXT: v_add_co_u32_e64 v0, s[2:3], v0, v2 ; GFX9-NEXT: v_add_co_u32_e64 v0, s[2:3], v0, v2
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v7, v4, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v7, v4, vcc
; GFX9-NEXT: v_addc_co_u32_e64 v2, vcc, v1, v3, s[2:3] ; GFX9-NEXT: v_addc_co_u32_e64 v2, vcc, v1, v3, s[2:3]
; GFX9-NEXT: v_mul_hi_u32 v4, v0, s4 ; GFX9-NEXT: v_mul_hi_u32 v4, v0, s4
; GFX9-NEXT: v_mul_lo_u32 v6, v2, s4 ; GFX9-NEXT: v_mul_lo_u32 v6, v2, s4
Show All 26 Lines
; GFX9-NEXT: v_mul_hi_u32 v4, s6, v1 ; GFX9-NEXT: v_mul_hi_u32 v4, s6, v1
; GFX9-NEXT: v_mul_hi_u32 v6, s7, v1 ; GFX9-NEXT: v_mul_hi_u32 v6, s7, v1
; GFX9-NEXT: v_mul_lo_u32 v1, s7, v1 ; GFX9-NEXT: v_mul_lo_u32 v1, s7, v1
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v3, v2 ; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v3, v2
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v7, v4, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v7, v4, vcc
; GFX9-NEXT: v_mul_lo_u32 v4, s7, v0 ; GFX9-NEXT: v_mul_lo_u32 v4, s7, v0
; GFX9-NEXT: v_mul_hi_u32 v0, s7, v0 ; GFX9-NEXT: v_mul_hi_u32 v0, s7, v0
; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 ; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v4, v2 ; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v2, v4
; GFX9-NEXT: v_addc_co_u32_e32 v0, vcc, v3, v0, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v0, vcc, v3, v0, vcc
; GFX9-NEXT: v_addc_co_u32_e32 v2, vcc, v6, v5, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v2, vcc, v6, v5, vcc
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v1 ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v1
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v7, v2, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v7, v2, vcc
; GFX9-NEXT: v_mul_lo_u32 v4, v0, s8 ; GFX9-NEXT: v_mul_lo_u32 v4, v0, s8
; GFX9-NEXT: v_mul_lo_u32 v2, v1, s8 ; GFX9-NEXT: v_mul_lo_u32 v2, v1, s8
; GFX9-NEXT: v_mul_hi_u32 v3, v0, s8 ; GFX9-NEXT: v_mul_hi_u32 v3, v0, s8
; GFX9-NEXT: v_sub_co_u32_e32 v4, vcc, s6, v4 ; GFX9-NEXT: v_sub_co_u32_e32 v4, vcc, s6, v4
▲ Show 20 Lines • Show All 125 Lines • ▼ Show 20 Lines
; GFX6-NEXT: v_mul_lo_u32 v2, v1, v2 ; GFX6-NEXT: v_mul_lo_u32 v2, v1, v2
; GFX6-NEXT: s_waitcnt lgkmcnt(0) ; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: s_mov_b32 s9, s5 ; GFX6-NEXT: s_mov_b32 s9, s5
; GFX6-NEXT: v_add_i32_e32 v5, vcc, v6, v5 ; GFX6-NEXT: v_add_i32_e32 v5, vcc, v6, v5
; GFX6-NEXT: v_mul_lo_u32 v6, v1, v3 ; GFX6-NEXT: v_mul_lo_u32 v6, v1, v3
; GFX6-NEXT: v_mul_hi_u32 v3, v1, v3 ; GFX6-NEXT: v_mul_hi_u32 v3, v1, v3
; GFX6-NEXT: v_addc_u32_e32 v4, vcc, v8, v4, vcc ; GFX6-NEXT: v_addc_u32_e32 v4, vcc, v8, v4, vcc
; GFX6-NEXT: s_movk_i32 s5, 0x11e ; GFX6-NEXT: s_movk_i32 s5, 0x11e
; GFX6-NEXT: v_add_i32_e32 v5, vcc, v6, v5 ; GFX6-NEXT: v_add_i32_e32 v5, vcc, v5, v6
; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v4, v3, vcc ; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v4, v3, vcc
; GFX6-NEXT: v_addc_u32_e32 v4, vcc, v9, v7, vcc ; GFX6-NEXT: v_addc_u32_e32 v4, vcc, v9, v7, vcc
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2
; GFX6-NEXT: v_add_i32_e64 v0, s[0:1], v0, v2 ; GFX6-NEXT: v_add_i32_e64 v0, s[0:1], v0, v2
; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v8, v4, vcc ; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v8, v4, vcc
; GFX6-NEXT: v_mul_lo_u32 v4, v0, s2 ; GFX6-NEXT: v_mul_lo_u32 v4, v0, s2
; GFX6-NEXT: v_mul_hi_u32 v5, v0, s3 ; GFX6-NEXT: v_mul_hi_u32 v5, v0, s3
; GFX6-NEXT: v_addc_u32_e64 v2, vcc, v1, v3, s[0:1] ; GFX6-NEXT: v_addc_u32_e64 v2, vcc, v1, v3, s[0:1]
Show All 27 Lines
; GFX6-NEXT: v_mul_hi_u32 v3, s6, v0 ; GFX6-NEXT: v_mul_hi_u32 v3, s6, v0
; GFX6-NEXT: v_mul_hi_u32 v4, s6, v1 ; GFX6-NEXT: v_mul_hi_u32 v4, s6, v1
; GFX6-NEXT: v_mul_hi_u32 v5, s7, v1 ; GFX6-NEXT: v_mul_hi_u32 v5, s7, v1
; GFX6-NEXT: v_mul_lo_u32 v1, s7, v1 ; GFX6-NEXT: v_mul_lo_u32 v1, s7, v1
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2
; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v8, v4, vcc ; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v8, v4, vcc
; GFX6-NEXT: v_mul_lo_u32 v4, s7, v0 ; GFX6-NEXT: v_mul_lo_u32 v4, s7, v0
; GFX6-NEXT: v_mul_hi_u32 v0, s7, v0 ; GFX6-NEXT: v_mul_hi_u32 v0, s7, v0
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v4, v2 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v4
; GFX6-NEXT: v_addc_u32_e32 v0, vcc, v3, v0, vcc ; GFX6-NEXT: v_addc_u32_e32 v0, vcc, v3, v0, vcc
; GFX6-NEXT: v_addc_u32_e32 v2, vcc, v5, v7, vcc ; GFX6-NEXT: v_addc_u32_e32 v2, vcc, v5, v7, vcc
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1 ; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1
; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v8, v2, vcc ; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v8, v2, vcc
; GFX6-NEXT: v_mul_lo_u32 v2, v0, s12 ; GFX6-NEXT: v_mul_lo_u32 v2, v0, s12
; GFX6-NEXT: v_mul_hi_u32 v3, v0, s13 ; GFX6-NEXT: v_mul_hi_u32 v3, v0, s13
; GFX6-NEXT: v_mul_lo_u32 v1, v1, s13 ; GFX6-NEXT: v_mul_lo_u32 v1, v1, s13
; GFX6-NEXT: v_mul_lo_u32 v0, v0, s13 ; GFX6-NEXT: v_mul_lo_u32 v0, v0, s13
▲ Show 20 Lines • Show All 59 Lines • ▼ Show 20 Lines
; GFX9-NEXT: v_mul_lo_u32 v5, v0, v2 ; GFX9-NEXT: v_mul_lo_u32 v5, v0, v2
; GFX9-NEXT: v_mul_hi_u32 v7, v0, v2 ; GFX9-NEXT: v_mul_hi_u32 v7, v0, v2
; GFX9-NEXT: v_mul_hi_u32 v8, v1, v2 ; GFX9-NEXT: v_mul_hi_u32 v8, v1, v2
; GFX9-NEXT: v_mul_lo_u32 v2, v1, v2 ; GFX9-NEXT: v_mul_lo_u32 v2, v1, v2
; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v5 ; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v5
; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v7, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v7, vcc
; GFX9-NEXT: v_mul_lo_u32 v7, v1, v4 ; GFX9-NEXT: v_mul_lo_u32 v7, v1, v4
; GFX9-NEXT: v_mul_hi_u32 v4, v1, v4 ; GFX9-NEXT: v_mul_hi_u32 v4, v1, v4
; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v7, v3 ; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v7
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v5, v4, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v5, v4, vcc
; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v8, v6, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v8, v6, vcc
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v3, v2 ; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v3, v2
; GFX9-NEXT: v_mov_b32_e32 v5, 0 ; GFX9-NEXT: v_mov_b32_e32 v5, 0
; GFX9-NEXT: v_add_co_u32_e64 v0, s[2:3], v0, v2 ; GFX9-NEXT: v_add_co_u32_e64 v0, s[2:3], v0, v2
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v5, v4, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v5, v4, vcc
; GFX9-NEXT: v_addc_co_u32_e64 v2, vcc, v1, v3, s[2:3] ; GFX9-NEXT: v_addc_co_u32_e64 v2, vcc, v1, v3, s[2:3]
; GFX9-NEXT: v_mul_lo_u32 v4, v0, s4 ; GFX9-NEXT: v_mul_lo_u32 v4, v0, s4
Show All 26 Lines
; GFX9-NEXT: v_mul_hi_u32 v3, s6, v0 ; GFX9-NEXT: v_mul_hi_u32 v3, s6, v0
; GFX9-NEXT: v_mul_hi_u32 v4, s6, v1 ; GFX9-NEXT: v_mul_hi_u32 v4, s6, v1
; GFX9-NEXT: v_mul_hi_u32 v7, s7, v1 ; GFX9-NEXT: v_mul_hi_u32 v7, s7, v1
; GFX9-NEXT: v_mul_lo_u32 v1, s7, v1 ; GFX9-NEXT: v_mul_lo_u32 v1, s7, v1
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v3, v2 ; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v3, v2
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v4, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v4, vcc
; GFX9-NEXT: v_mul_lo_u32 v4, s7, v0 ; GFX9-NEXT: v_mul_lo_u32 v4, s7, v0
; GFX9-NEXT: v_mul_hi_u32 v0, s7, v0 ; GFX9-NEXT: v_mul_hi_u32 v0, s7, v0
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v4, v2 ; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v2, v4
; GFX9-NEXT: v_addc_co_u32_e32 v0, vcc, v3, v0, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v0, vcc, v3, v0, vcc
; GFX9-NEXT: v_addc_co_u32_e32 v2, vcc, v7, v6, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v2, vcc, v7, v6, vcc
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v1 ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v1
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v5, v2, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v5, v2, vcc
; GFX9-NEXT: v_mul_lo_u32 v2, v0, s8 ; GFX9-NEXT: v_mul_lo_u32 v2, v0, s8
; GFX9-NEXT: v_mul_hi_u32 v3, v0, s9 ; GFX9-NEXT: v_mul_hi_u32 v3, v0, s9
; GFX9-NEXT: v_mul_lo_u32 v1, v1, s9 ; GFX9-NEXT: v_mul_lo_u32 v1, v1, s9
; GFX9-NEXT: v_mul_lo_u32 v0, v0, s9 ; GFX9-NEXT: v_mul_lo_u32 v0, v0, s9
▲ Show 20 Lines • Show All 269 Lines • ▼ Show 20 Lines
; GFX6-NEXT: v_mul_hi_u32 v3, v0, v2 ; GFX6-NEXT: v_mul_hi_u32 v3, v0, v2
; GFX6-NEXT: v_mul_hi_u32 v9, v1, v2 ; GFX6-NEXT: v_mul_hi_u32 v9, v1, v2
; GFX6-NEXT: v_mul_lo_u32 v2, v1, v2 ; GFX6-NEXT: v_mul_lo_u32 v2, v1, v2
; GFX6-NEXT: v_add_i32_e32 v5, vcc, v6, v5 ; GFX6-NEXT: v_add_i32_e32 v5, vcc, v6, v5
; GFX6-NEXT: v_mul_lo_u32 v6, v1, v4 ; GFX6-NEXT: v_mul_lo_u32 v6, v1, v4
; GFX6-NEXT: v_mul_hi_u32 v4, v1, v4 ; GFX6-NEXT: v_mul_hi_u32 v4, v1, v4
; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v8, v3, vcc ; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v8, v3, vcc
; GFX6-NEXT: s_mov_b32 s5, s9 ; GFX6-NEXT: s_mov_b32 s5, s9
; GFX6-NEXT: v_add_i32_e32 v5, vcc, v6, v5 ; GFX6-NEXT: v_add_i32_e32 v5, vcc, v5, v6
; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v3, v4, vcc ; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v3, v4, vcc
; GFX6-NEXT: v_addc_u32_e32 v4, vcc, v9, v7, vcc ; GFX6-NEXT: v_addc_u32_e32 v4, vcc, v9, v7, vcc
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2
; GFX6-NEXT: v_add_i32_e64 v0, s[0:1], v0, v2 ; GFX6-NEXT: v_add_i32_e64 v0, s[0:1], v0, v2
; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v8, v4, vcc ; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v8, v4, vcc
; GFX6-NEXT: v_addc_u32_e64 v2, vcc, v1, v3, s[0:1] ; GFX6-NEXT: v_addc_u32_e64 v2, vcc, v1, v3, s[0:1]
; GFX6-NEXT: v_mul_lo_u32 v4, v2, s2 ; GFX6-NEXT: v_mul_lo_u32 v4, v2, s2
; GFX6-NEXT: v_mul_hi_u32 v5, s2, v0 ; GFX6-NEXT: v_mul_hi_u32 v5, s2, v0
Show All 28 Lines
; GFX6-NEXT: v_mul_hi_u32 v4, s0, v1 ; GFX6-NEXT: v_mul_hi_u32 v4, s0, v1
; GFX6-NEXT: v_mul_hi_u32 v5, s1, v1 ; GFX6-NEXT: v_mul_hi_u32 v5, s1, v1
; GFX6-NEXT: v_mul_lo_u32 v1, s1, v1 ; GFX6-NEXT: v_mul_lo_u32 v1, s1, v1
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2
; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v8, v4, vcc ; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v8, v4, vcc
; GFX6-NEXT: v_mul_lo_u32 v4, s1, v0 ; GFX6-NEXT: v_mul_lo_u32 v4, s1, v0
; GFX6-NEXT: v_mul_hi_u32 v0, s1, v0 ; GFX6-NEXT: v_mul_hi_u32 v0, s1, v0
; GFX6-NEXT: s_mov_b32 s3, 0x12d8fb ; GFX6-NEXT: s_mov_b32 s3, 0x12d8fb
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v4, v2 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v4
; GFX6-NEXT: v_addc_u32_e32 v0, vcc, v3, v0, vcc ; GFX6-NEXT: v_addc_u32_e32 v0, vcc, v3, v0, vcc
; GFX6-NEXT: v_addc_u32_e32 v2, vcc, v5, v7, vcc ; GFX6-NEXT: v_addc_u32_e32 v2, vcc, v5, v7, vcc
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1 ; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1
; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v8, v2, vcc ; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v8, v2, vcc
; GFX6-NEXT: v_mul_lo_u32 v2, v1, s3 ; GFX6-NEXT: v_mul_lo_u32 v2, v1, s3
; GFX6-NEXT: v_mul_hi_u32 v3, s3, v0 ; GFX6-NEXT: v_mul_hi_u32 v3, s3, v0
; GFX6-NEXT: v_mul_lo_u32 v4, v0, s3 ; GFX6-NEXT: v_mul_lo_u32 v4, v0, s3
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2
▲ Show 20 Lines • Show All 53 Lines • ▼ Show 20 Lines
; GFX9-NEXT: v_mul_lo_u32 v6, v0, v2 ; GFX9-NEXT: v_mul_lo_u32 v6, v0, v2
; GFX9-NEXT: v_mul_hi_u32 v8, v0, v2 ; GFX9-NEXT: v_mul_hi_u32 v8, v0, v2
; GFX9-NEXT: v_mul_hi_u32 v9, v1, v2 ; GFX9-NEXT: v_mul_hi_u32 v9, v1, v2
; GFX9-NEXT: v_mul_lo_u32 v2, v1, v2 ; GFX9-NEXT: v_mul_lo_u32 v2, v1, v2
; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v6 ; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v6
; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, v7, v8, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, v7, v8, vcc
; GFX9-NEXT: v_mul_lo_u32 v8, v1, v4 ; GFX9-NEXT: v_mul_lo_u32 v8, v1, v4
; GFX9-NEXT: v_mul_hi_u32 v4, v1, v4 ; GFX9-NEXT: v_mul_hi_u32 v4, v1, v4
; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v8, v3 ; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v8
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v6, v4, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v6, v4, vcc
; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v9, v5, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v9, v5, vcc
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v3, v2 ; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v3, v2
; GFX9-NEXT: v_add_co_u32_e64 v0, s[2:3], v0, v2 ; GFX9-NEXT: v_add_co_u32_e64 v0, s[2:3], v0, v2
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v7, v4, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v7, v4, vcc
; GFX9-NEXT: v_addc_co_u32_e64 v2, vcc, v1, v3, s[2:3] ; GFX9-NEXT: v_addc_co_u32_e64 v2, vcc, v1, v3, s[2:3]
; GFX9-NEXT: v_mul_lo_u32 v4, v2, s8 ; GFX9-NEXT: v_mul_lo_u32 v4, v2, s8
; GFX9-NEXT: v_mul_hi_u32 v6, s8, v0 ; GFX9-NEXT: v_mul_hi_u32 v6, s8, v0
Show All 29 Lines
; GFX9-NEXT: v_mul_hi_u32 v4, s0, v1 ; GFX9-NEXT: v_mul_hi_u32 v4, s0, v1
; GFX9-NEXT: v_mul_hi_u32 v6, s1, v1 ; GFX9-NEXT: v_mul_hi_u32 v6, s1, v1
; GFX9-NEXT: v_mul_lo_u32 v1, s1, v1 ; GFX9-NEXT: v_mul_lo_u32 v1, s1, v1
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v3, v2 ; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v3, v2
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v7, v4, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v7, v4, vcc
; GFX9-NEXT: v_mul_lo_u32 v4, s1, v0 ; GFX9-NEXT: v_mul_lo_u32 v4, s1, v0
; GFX9-NEXT: v_mul_hi_u32 v0, s1, v0 ; GFX9-NEXT: v_mul_hi_u32 v0, s1, v0
; GFX9-NEXT: s_mov_b32 s3, 0x12d8fb ; GFX9-NEXT: s_mov_b32 s3, 0x12d8fb
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v4, v2 ; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v2, v4
; GFX9-NEXT: v_addc_co_u32_e32 v0, vcc, v3, v0, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v0, vcc, v3, v0, vcc
; GFX9-NEXT: v_addc_co_u32_e32 v2, vcc, v6, v5, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v2, vcc, v6, v5, vcc
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v1 ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v1
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v7, v2, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v7, v2, vcc
; GFX9-NEXT: v_mul_lo_u32 v4, v0, s3 ; GFX9-NEXT: v_mul_lo_u32 v4, v0, s3
; GFX9-NEXT: v_mul_lo_u32 v2, v1, s3 ; GFX9-NEXT: v_mul_lo_u32 v2, v1, s3
; GFX9-NEXT: v_mul_hi_u32 v3, s3, v0 ; GFX9-NEXT: v_mul_hi_u32 v3, s3, v0
; GFX9-NEXT: v_sub_co_u32_e32 v4, vcc, s0, v4 ; GFX9-NEXT: v_sub_co_u32_e32 v4, vcc, s0, v4
▲ Show 20 Lines • Show All 122 Lines • ▼ Show 20 Lines
; GFX6-NEXT: v_mul_lo_u32 v5, v0, v2 ; GFX6-NEXT: v_mul_lo_u32 v5, v0, v2
; GFX6-NEXT: v_mul_hi_u32 v6, v0, v2 ; GFX6-NEXT: v_mul_hi_u32 v6, v0, v2
; GFX6-NEXT: v_mul_hi_u32 v7, v1, v2 ; GFX6-NEXT: v_mul_hi_u32 v7, v1, v2
; GFX6-NEXT: v_mul_lo_u32 v2, v1, v2 ; GFX6-NEXT: v_mul_lo_u32 v2, v1, v2
; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v5 ; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v5
; GFX6-NEXT: v_addc_u32_e32 v5, vcc, 0, v6, vcc ; GFX6-NEXT: v_addc_u32_e32 v5, vcc, 0, v6, vcc
; GFX6-NEXT: v_mul_lo_u32 v6, v1, v4 ; GFX6-NEXT: v_mul_lo_u32 v6, v1, v4
; GFX6-NEXT: v_mul_hi_u32 v4, v1, v4 ; GFX6-NEXT: v_mul_hi_u32 v4, v1, v4
; GFX6-NEXT: v_add_i32_e32 v3, vcc, v6, v3 ; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v6
; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v5, v4, vcc ; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v5, v4, vcc
; GFX6-NEXT: v_mov_b32_e32 v4, 0 ; GFX6-NEXT: v_mov_b32_e32 v4, 0
; GFX6-NEXT: v_addc_u32_e32 v5, vcc, v7, v4, vcc ; GFX6-NEXT: v_addc_u32_e32 v5, vcc, v7, v4, vcc
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2
; GFX6-NEXT: v_mov_b32_e32 v6, 0 ; GFX6-NEXT: v_mov_b32_e32 v6, 0
; GFX6-NEXT: v_add_i32_e64 v0, s[0:1], v0, v2 ; GFX6-NEXT: v_add_i32_e64 v0, s[0:1], v0, v2
; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v6, v5, vcc ; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v6, v5, vcc
; GFX6-NEXT: v_addc_u32_e64 v2, vcc, v1, v3, s[0:1] ; GFX6-NEXT: v_addc_u32_e64 v2, vcc, v1, v3, s[0:1]
Show All 30 Lines
; GFX6-NEXT: v_mul_hi_u32 v5, s10, v1 ; GFX6-NEXT: v_mul_hi_u32 v5, s10, v1
; GFX6-NEXT: v_mul_hi_u32 v7, s11, v1 ; GFX6-NEXT: v_mul_hi_u32 v7, s11, v1
; GFX6-NEXT: v_mul_lo_u32 v1, s11, v1 ; GFX6-NEXT: v_mul_lo_u32 v1, s11, v1
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2
; GFX6-NEXT: v_addc_u32_e32 v3, vcc, 0, v5, vcc ; GFX6-NEXT: v_addc_u32_e32 v3, vcc, 0, v5, vcc
; GFX6-NEXT: v_mul_lo_u32 v5, s11, v0 ; GFX6-NEXT: v_mul_lo_u32 v5, s11, v0
; GFX6-NEXT: v_mul_hi_u32 v0, s11, v0 ; GFX6-NEXT: v_mul_hi_u32 v0, s11, v0
; GFX6-NEXT: s_mov_b32 s4, s8 ; GFX6-NEXT: s_mov_b32 s4, s8
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v5, v2 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v5
; GFX6-NEXT: v_addc_u32_e32 v0, vcc, v3, v0, vcc ; GFX6-NEXT: v_addc_u32_e32 v0, vcc, v3, v0, vcc
; GFX6-NEXT: v_addc_u32_e32 v2, vcc, v7, v4, vcc ; GFX6-NEXT: v_addc_u32_e32 v2, vcc, v7, v4, vcc
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1 ; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1
; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v6, v2, vcc ; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v6, v2, vcc
; GFX6-NEXT: v_mul_lo_u32 v2, s2, v1 ; GFX6-NEXT: v_mul_lo_u32 v2, s2, v1
; GFX6-NEXT: v_mul_hi_u32 v3, s2, v0 ; GFX6-NEXT: v_mul_hi_u32 v3, s2, v0
; GFX6-NEXT: v_mul_lo_u32 v4, s3, v0 ; GFX6-NEXT: v_mul_lo_u32 v4, s3, v0
; GFX6-NEXT: v_mov_b32_e32 v5, s3 ; GFX6-NEXT: v_mov_b32_e32 v5, s3
▲ Show 20 Lines • Show All 73 Lines • ▼ Show 20 Lines
; GFX9-NEXT: v_mul_lo_u32 v6, v0, v3 ; GFX9-NEXT: v_mul_lo_u32 v6, v0, v3
; GFX9-NEXT: v_mul_hi_u32 v8, v0, v3 ; GFX9-NEXT: v_mul_hi_u32 v8, v0, v3
; GFX9-NEXT: v_mul_hi_u32 v7, v1, v5 ; GFX9-NEXT: v_mul_hi_u32 v7, v1, v5
; GFX9-NEXT: v_mul_lo_u32 v5, v1, v5 ; GFX9-NEXT: v_mul_lo_u32 v5, v1, v5
; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v4, v6 ; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v4, v6
; GFX9-NEXT: v_mul_hi_u32 v9, v1, v3 ; GFX9-NEXT: v_mul_hi_u32 v9, v1, v3
; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, 0, v8, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, 0, v8, vcc
; GFX9-NEXT: v_mul_lo_u32 v3, v1, v3 ; GFX9-NEXT: v_mul_lo_u32 v3, v1, v3
; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v5, v4 ; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v4, v5
; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v6, v7, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v6, v7, vcc
; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, v9, v2, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, v9, v2, vcc
; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v4, v3 ; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v4, v3
; GFX9-NEXT: v_mov_b32_e32 v6, 0 ; GFX9-NEXT: v_mov_b32_e32 v6, 0
; GFX9-NEXT: v_add_co_u32_e64 v0, s[2:3], v0, v3 ; GFX9-NEXT: v_add_co_u32_e64 v0, s[2:3], v0, v3
; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v6, v5, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v6, v5, vcc
; GFX9-NEXT: v_addc_co_u32_e64 v3, vcc, v1, v4, s[2:3] ; GFX9-NEXT: v_addc_co_u32_e64 v3, vcc, v1, v4, s[2:3]
; GFX9-NEXT: v_mul_lo_u32 v5, s12, v3 ; GFX9-NEXT: v_mul_lo_u32 v5, s12, v3
Show All 31 Lines
; GFX9-NEXT: v_mul_hi_u32 v4, s6, v0 ; GFX9-NEXT: v_mul_hi_u32 v4, s6, v0
; GFX9-NEXT: v_mul_hi_u32 v5, s6, v1 ; GFX9-NEXT: v_mul_hi_u32 v5, s6, v1
; GFX9-NEXT: v_mul_hi_u32 v7, s7, v1 ; GFX9-NEXT: v_mul_hi_u32 v7, s7, v1
; GFX9-NEXT: v_mul_lo_u32 v1, s7, v1 ; GFX9-NEXT: v_mul_lo_u32 v1, s7, v1
; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v4, v3 ; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v4, v3
; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, 0, v5, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, 0, v5, vcc
; GFX9-NEXT: v_mul_lo_u32 v5, s7, v0 ; GFX9-NEXT: v_mul_lo_u32 v5, s7, v0
; GFX9-NEXT: v_mul_hi_u32 v0, s7, v0 ; GFX9-NEXT: v_mul_hi_u32 v0, s7, v0
; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v5, v3 ; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v5
; GFX9-NEXT: v_addc_co_u32_e32 v0, vcc, v4, v0, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v0, vcc, v4, v0, vcc
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v7, v2, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v7, v2, vcc
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v1 ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v1
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v6, v3, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v6, v3, vcc
; GFX9-NEXT: v_mul_lo_u32 v3, s10, v1 ; GFX9-NEXT: v_mul_lo_u32 v3, s10, v1
; GFX9-NEXT: v_mul_hi_u32 v4, s10, v0 ; GFX9-NEXT: v_mul_hi_u32 v4, s10, v0
; GFX9-NEXT: v_mul_lo_u32 v5, s11, v0 ; GFX9-NEXT: v_mul_lo_u32 v5, s11, v0
; GFX9-NEXT: v_mov_b32_e32 v6, s11 ; GFX9-NEXT: v_mov_b32_e32 v6, s11
▲ Show 20 Lines • Show All 149 Lines • ▼ Show 20 Lines
; GFX6-NEXT: v_mul_hi_u32 v7, v1, v2 ; GFX6-NEXT: v_mul_hi_u32 v7, v1, v2
; GFX6-NEXT: v_mul_lo_u32 v2, v1, v2 ; GFX6-NEXT: v_mul_lo_u32 v2, v1, v2
; GFX6-NEXT: s_ashr_i64 s[2:3], s[2:3], 12 ; GFX6-NEXT: s_ashr_i64 s[2:3], s[2:3], 12
; GFX6-NEXT: v_add_i32_e32 v4, vcc, v5, v4 ; GFX6-NEXT: v_add_i32_e32 v4, vcc, v5, v4
; GFX6-NEXT: v_addc_u32_e32 v5, vcc, 0, v6, vcc ; GFX6-NEXT: v_addc_u32_e32 v5, vcc, 0, v6, vcc
; GFX6-NEXT: v_mul_lo_u32 v6, v1, v3 ; GFX6-NEXT: v_mul_lo_u32 v6, v1, v3
; GFX6-NEXT: v_mul_hi_u32 v3, v1, v3 ; GFX6-NEXT: v_mul_hi_u32 v3, v1, v3
; GFX6-NEXT: s_mov_b32 s9, s8 ; GFX6-NEXT: s_mov_b32 s9, s8
; GFX6-NEXT: v_add_i32_e32 v4, vcc, v6, v4 ; GFX6-NEXT: v_add_i32_e32 v4, vcc, v4, v6
; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v5, v3, vcc ; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v5, v3, vcc
; GFX6-NEXT: v_mov_b32_e32 v4, 0 ; GFX6-NEXT: v_mov_b32_e32 v4, 0
; GFX6-NEXT: v_addc_u32_e32 v5, vcc, v7, v4, vcc ; GFX6-NEXT: v_addc_u32_e32 v5, vcc, v7, v4, vcc
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2
; GFX6-NEXT: v_mov_b32_e32 v6, 0 ; GFX6-NEXT: v_mov_b32_e32 v6, 0
; GFX6-NEXT: v_add_i32_e64 v0, s[0:1], v0, v2 ; GFX6-NEXT: v_add_i32_e64 v0, s[0:1], v0, v2
; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v6, v5, vcc ; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v6, v5, vcc
; GFX6-NEXT: v_addc_u32_e64 v2, vcc, v1, v3, s[0:1] ; GFX6-NEXT: v_addc_u32_e64 v2, vcc, v1, v3, s[0:1]
Show All 29 Lines
; GFX6-NEXT: v_mul_hi_u32 v7, s1, v1 ; GFX6-NEXT: v_mul_hi_u32 v7, s1, v1
; GFX6-NEXT: v_mul_lo_u32 v1, s1, v1 ; GFX6-NEXT: v_mul_lo_u32 v1, s1, v1
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2
; GFX6-NEXT: v_addc_u32_e32 v3, vcc, 0, v5, vcc ; GFX6-NEXT: v_addc_u32_e32 v3, vcc, 0, v5, vcc
; GFX6-NEXT: v_mul_lo_u32 v5, s1, v0 ; GFX6-NEXT: v_mul_lo_u32 v5, s1, v0
; GFX6-NEXT: v_mul_hi_u32 v0, s1, v0 ; GFX6-NEXT: v_mul_hi_u32 v0, s1, v0
; GFX6-NEXT: s_movk_i32 s9, 0xfff ; GFX6-NEXT: s_movk_i32 s9, 0xfff
; GFX6-NEXT: s_mov_b32 s6, -1 ; GFX6-NEXT: s_mov_b32 s6, -1
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v5, v2 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v5
; GFX6-NEXT: v_addc_u32_e32 v0, vcc, v3, v0, vcc ; GFX6-NEXT: v_addc_u32_e32 v0, vcc, v3, v0, vcc
; GFX6-NEXT: v_addc_u32_e32 v2, vcc, v7, v4, vcc ; GFX6-NEXT: v_addc_u32_e32 v2, vcc, v7, v4, vcc
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1 ; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1
; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v6, v2, vcc ; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v6, v2, vcc
; GFX6-NEXT: v_mul_lo_u32 v2, v1, s9 ; GFX6-NEXT: v_mul_lo_u32 v2, v1, s9
; GFX6-NEXT: v_mul_hi_u32 v3, s9, v0 ; GFX6-NEXT: v_mul_hi_u32 v3, s9, v0
; GFX6-NEXT: v_mul_lo_u32 v4, v0, s9 ; GFX6-NEXT: v_mul_lo_u32 v4, v0, s9
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2
▲ Show 20 Lines • Show All 61 Lines • ▼ Show 20 Lines
; GFX9-NEXT: v_mul_hi_u32 v7, v0, v2 ; GFX9-NEXT: v_mul_hi_u32 v7, v0, v2
; GFX9-NEXT: v_mul_hi_u32 v8, v1, v2 ; GFX9-NEXT: v_mul_hi_u32 v8, v1, v2
; GFX9-NEXT: v_mul_lo_u32 v2, v1, v2 ; GFX9-NEXT: v_mul_lo_u32 v2, v1, v2
; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v6, v3 ; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v6, v3
; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, 0, v7, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, 0, v7, vcc
; GFX9-NEXT: v_mul_lo_u32 v7, v1, v5 ; GFX9-NEXT: v_mul_lo_u32 v7, v1, v5
; GFX9-NEXT: v_mul_hi_u32 v5, v1, v5 ; GFX9-NEXT: v_mul_hi_u32 v5, v1, v5
; GFX9-NEXT: s_ashr_i64 s[4:5], s[4:5], 12 ; GFX9-NEXT: s_ashr_i64 s[4:5], s[4:5], 12
; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v7, v3 ; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v7
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v6, v5, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v6, v5, vcc
; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, v8, v4, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, v8, v4, vcc
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v3, v2 ; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v3, v2
; GFX9-NEXT: v_mov_b32_e32 v6, 0 ; GFX9-NEXT: v_mov_b32_e32 v6, 0
; GFX9-NEXT: v_add_co_u32_e64 v0, s[2:3], v0, v2 ; GFX9-NEXT: v_add_co_u32_e64 v0, s[2:3], v0, v2
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v6, v5, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v6, v5, vcc
; GFX9-NEXT: v_addc_co_u32_e64 v2, vcc, v1, v3, s[2:3] ; GFX9-NEXT: v_addc_co_u32_e64 v2, vcc, v1, v3, s[2:3]
; GFX9-NEXT: v_mul_lo_u32 v5, v2, s8 ; GFX9-NEXT: v_mul_lo_u32 v5, v2, s8
Show All 30 Lines
; GFX9-NEXT: v_mul_hi_u32 v5, s6, v1 ; GFX9-NEXT: v_mul_hi_u32 v5, s6, v1
; GFX9-NEXT: v_mul_hi_u32 v7, s7, v1 ; GFX9-NEXT: v_mul_hi_u32 v7, s7, v1
; GFX9-NEXT: v_mul_lo_u32 v1, s7, v1 ; GFX9-NEXT: v_mul_lo_u32 v1, s7, v1
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v3, v2 ; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v3, v2
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v5, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v5, vcc
; GFX9-NEXT: v_mul_lo_u32 v5, s7, v0 ; GFX9-NEXT: v_mul_lo_u32 v5, s7, v0
; GFX9-NEXT: v_mul_hi_u32 v0, s7, v0 ; GFX9-NEXT: v_mul_hi_u32 v0, s7, v0
; GFX9-NEXT: s_movk_i32 s3, 0xfff ; GFX9-NEXT: s_movk_i32 s3, 0xfff
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v5, v2 ; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v2, v5
; GFX9-NEXT: v_addc_co_u32_e32 v0, vcc, v3, v0, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v0, vcc, v3, v0, vcc
; GFX9-NEXT: v_addc_co_u32_e32 v2, vcc, v7, v4, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v2, vcc, v7, v4, vcc
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v1 ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v1
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v6, v2, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v6, v2, vcc
; GFX9-NEXT: v_mul_lo_u32 v5, v0, s3 ; GFX9-NEXT: v_mul_lo_u32 v5, v0, s3
; GFX9-NEXT: v_mul_lo_u32 v2, v1, s3 ; GFX9-NEXT: v_mul_lo_u32 v2, v1, s3
; GFX9-NEXT: v_mul_hi_u32 v3, s3, v0 ; GFX9-NEXT: v_mul_hi_u32 v3, s3, v0
; GFX9-NEXT: v_sub_co_u32_e32 v5, vcc, s6, v5 ; GFX9-NEXT: v_sub_co_u32_e32 v5, vcc, s6, v5
▲ Show 20 Lines • Show All 91 Lines • ▼ Show 20 Lines
; GFX6-NEXT: v_mul_hi_u32 v4, v0, v5 ; GFX6-NEXT: v_mul_hi_u32 v4, v0, v5
; GFX6-NEXT: v_mul_hi_u32 v6, v0, v2 ; GFX6-NEXT: v_mul_hi_u32 v6, v0, v2
; GFX6-NEXT: v_mul_hi_u32 v7, v1, v2 ; GFX6-NEXT: v_mul_hi_u32 v7, v1, v2
; GFX6-NEXT: v_mul_lo_u32 v2, v1, v2 ; GFX6-NEXT: v_mul_lo_u32 v2, v1, v2
; GFX6-NEXT: v_add_i32_e32 v3, vcc, v4, v3 ; GFX6-NEXT: v_add_i32_e32 v3, vcc, v4, v3
; GFX6-NEXT: v_addc_u32_e32 v4, vcc, 0, v6, vcc ; GFX6-NEXT: v_addc_u32_e32 v4, vcc, 0, v6, vcc
; GFX6-NEXT: v_mul_lo_u32 v6, v1, v5 ; GFX6-NEXT: v_mul_lo_u32 v6, v1, v5
; GFX6-NEXT: v_mul_hi_u32 v5, v1, v5 ; GFX6-NEXT: v_mul_hi_u32 v5, v1, v5
; GFX6-NEXT: v_add_i32_e32 v3, vcc, v6, v3 ; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v6
; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v4, v5, vcc ; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v4, v5, vcc
; GFX6-NEXT: v_mov_b32_e32 v4, 0 ; GFX6-NEXT: v_mov_b32_e32 v4, 0
; GFX6-NEXT: v_addc_u32_e32 v5, vcc, v7, v4, vcc ; GFX6-NEXT: v_addc_u32_e32 v5, vcc, v7, v4, vcc
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2
; GFX6-NEXT: v_mov_b32_e32 v6, 0 ; GFX6-NEXT: v_mov_b32_e32 v6, 0
; GFX6-NEXT: v_add_i32_e64 v0, s[2:3], v0, v2 ; GFX6-NEXT: v_add_i32_e64 v0, s[2:3], v0, v2
; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v6, v5, vcc ; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v6, v5, vcc
; GFX6-NEXT: v_addc_u32_e64 v2, vcc, v1, v3, s[2:3] ; GFX6-NEXT: v_addc_u32_e64 v2, vcc, v1, v3, s[2:3]
Show All 34 Lines
; GFX6-NEXT: v_mul_hi_u32 v7, s9, v1 ; GFX6-NEXT: v_mul_hi_u32 v7, s9, v1
; GFX6-NEXT: v_mul_lo_u32 v1, s9, v1 ; GFX6-NEXT: v_mul_lo_u32 v1, s9, v1
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2
; GFX6-NEXT: v_addc_u32_e32 v3, vcc, 0, v5, vcc ; GFX6-NEXT: v_addc_u32_e32 v3, vcc, 0, v5, vcc
; GFX6-NEXT: v_mul_lo_u32 v5, s9, v0 ; GFX6-NEXT: v_mul_lo_u32 v5, s9, v0
; GFX6-NEXT: v_mul_hi_u32 v0, s9, v0 ; GFX6-NEXT: v_mul_hi_u32 v0, s9, v0
; GFX6-NEXT: s_xor_b64 s[2:3], s[2:3], s[16:17] ; GFX6-NEXT: s_xor_b64 s[2:3], s[2:3], s[16:17]
; GFX6-NEXT: s_mov_b32 s6, -1 ; GFX6-NEXT: s_mov_b32 s6, -1
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v5, v2 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v5
; GFX6-NEXT: v_addc_u32_e32 v0, vcc, v3, v0, vcc ; GFX6-NEXT: v_addc_u32_e32 v0, vcc, v3, v0, vcc
; GFX6-NEXT: v_addc_u32_e32 v2, vcc, v7, v4, vcc ; GFX6-NEXT: v_addc_u32_e32 v2, vcc, v7, v4, vcc
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1 ; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1
; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v6, v2, vcc ; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v6, v2, vcc
; GFX6-NEXT: v_mul_lo_u32 v2, s14, v1 ; GFX6-NEXT: v_mul_lo_u32 v2, s14, v1
; GFX6-NEXT: v_mul_hi_u32 v3, s14, v0 ; GFX6-NEXT: v_mul_hi_u32 v3, s14, v0
; GFX6-NEXT: v_mul_lo_u32 v5, s15, v0 ; GFX6-NEXT: v_mul_lo_u32 v5, s15, v0
; GFX6-NEXT: v_mov_b32_e32 v7, s15 ; GFX6-NEXT: v_mov_b32_e32 v7, s15
▲ Show 20 Lines • Show All 58 Lines • ▼ Show 20 Lines
; GFX6-NEXT: v_mul_hi_u32 v9, v3, v7 ; GFX6-NEXT: v_mul_hi_u32 v9, v3, v7
; GFX6-NEXT: v_mul_hi_u32 v11, v5, v2 ; GFX6-NEXT: v_mul_hi_u32 v11, v5, v2
; GFX6-NEXT: v_mul_lo_u32 v2, v5, v2 ; GFX6-NEXT: v_mul_lo_u32 v2, v5, v2
; GFX6-NEXT: v_xor_b32_e32 v1, s3, v1 ; GFX6-NEXT: v_xor_b32_e32 v1, s3, v1
; GFX6-NEXT: v_add_i32_e32 v8, vcc, v9, v8 ; GFX6-NEXT: v_add_i32_e32 v8, vcc, v9, v8
; GFX6-NEXT: v_addc_u32_e32 v9, vcc, 0, v10, vcc ; GFX6-NEXT: v_addc_u32_e32 v9, vcc, 0, v10, vcc
; GFX6-NEXT: v_mul_lo_u32 v10, v5, v7 ; GFX6-NEXT: v_mul_lo_u32 v10, v5, v7
; GFX6-NEXT: v_mul_hi_u32 v7, v5, v7 ; GFX6-NEXT: v_mul_hi_u32 v7, v5, v7
; GFX6-NEXT: v_add_i32_e32 v8, vcc, v10, v8 ; GFX6-NEXT: v_add_i32_e32 v8, vcc, v8, v10
; GFX6-NEXT: v_addc_u32_e32 v7, vcc, v9, v7, vcc ; GFX6-NEXT: v_addc_u32_e32 v7, vcc, v9, v7, vcc
; GFX6-NEXT: v_addc_u32_e32 v8, vcc, v11, v4, vcc ; GFX6-NEXT: v_addc_u32_e32 v8, vcc, v11, v4, vcc
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v7, v2 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v7, v2
; GFX6-NEXT: v_add_i32_e64 v2, s[0:1], v3, v2 ; GFX6-NEXT: v_add_i32_e64 v2, s[0:1], v3, v2
; GFX6-NEXT: v_addc_u32_e32 v7, vcc, v6, v8, vcc ; GFX6-NEXT: v_addc_u32_e32 v7, vcc, v6, v8, vcc
; GFX6-NEXT: v_addc_u32_e64 v3, vcc, v5, v7, s[0:1] ; GFX6-NEXT: v_addc_u32_e64 v3, vcc, v5, v7, s[0:1]
; GFX6-NEXT: v_mul_lo_u32 v8, s14, v3 ; GFX6-NEXT: v_mul_lo_u32 v8, s14, v3
; GFX6-NEXT: v_mul_hi_u32 v9, s14, v2 ; GFX6-NEXT: v_mul_hi_u32 v9, s14, v2
Show All 29 Lines
; GFX6-NEXT: v_mul_hi_u32 v9, s10, v3 ; GFX6-NEXT: v_mul_hi_u32 v9, s10, v3
; GFX6-NEXT: v_mul_hi_u32 v10, s11, v3 ; GFX6-NEXT: v_mul_hi_u32 v10, s11, v3
; GFX6-NEXT: v_mul_lo_u32 v3, s11, v3 ; GFX6-NEXT: v_mul_lo_u32 v3, s11, v3
; GFX6-NEXT: v_add_i32_e32 v5, vcc, v7, v5 ; GFX6-NEXT: v_add_i32_e32 v5, vcc, v7, v5
; GFX6-NEXT: v_addc_u32_e32 v7, vcc, 0, v9, vcc ; GFX6-NEXT: v_addc_u32_e32 v7, vcc, 0, v9, vcc
; GFX6-NEXT: v_mul_lo_u32 v9, s11, v2 ; GFX6-NEXT: v_mul_lo_u32 v9, s11, v2
; GFX6-NEXT: v_mul_hi_u32 v2, s11, v2 ; GFX6-NEXT: v_mul_hi_u32 v2, s11, v2
; GFX6-NEXT: v_mov_b32_e32 v8, s3 ; GFX6-NEXT: v_mov_b32_e32 v8, s3
; GFX6-NEXT: v_add_i32_e32 v5, vcc, v9, v5 ; GFX6-NEXT: v_add_i32_e32 v5, vcc, v5, v9
; GFX6-NEXT: v_addc_u32_e32 v2, vcc, v7, v2, vcc ; GFX6-NEXT: v_addc_u32_e32 v2, vcc, v7, v2, vcc
; GFX6-NEXT: v_addc_u32_e32 v4, vcc, v10, v4, vcc ; GFX6-NEXT: v_addc_u32_e32 v4, vcc, v10, v4, vcc
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v3 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v3
; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v6, v4, vcc ; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v6, v4, vcc
; GFX6-NEXT: v_mul_lo_u32 v4, s12, v3 ; GFX6-NEXT: v_mul_lo_u32 v4, s12, v3
; GFX6-NEXT: v_mul_hi_u32 v5, s12, v2 ; GFX6-NEXT: v_mul_hi_u32 v5, s12, v2
; GFX6-NEXT: v_mul_lo_u32 v6, s13, v2 ; GFX6-NEXT: v_mul_lo_u32 v6, s13, v2
; GFX6-NEXT: v_subrev_i32_e32 v0, vcc, s2, v0 ; GFX6-NEXT: v_subrev_i32_e32 v0, vcc, s2, v0
▲ Show 20 Lines • Show All 80 Lines • ▼ Show 20 Lines
; GFX9-NEXT: v_mul_lo_u32 v5, v0, v2 ; GFX9-NEXT: v_mul_lo_u32 v5, v0, v2
; GFX9-NEXT: v_mul_hi_u32 v7, v0, v2 ; GFX9-NEXT: v_mul_hi_u32 v7, v0, v2
; GFX9-NEXT: v_mul_hi_u32 v8, v1, v2 ; GFX9-NEXT: v_mul_hi_u32 v8, v1, v2
; GFX9-NEXT: v_mul_lo_u32 v2, v1, v2 ; GFX9-NEXT: v_mul_lo_u32 v2, v1, v2
; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v5 ; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v5
; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v7, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v7, vcc
; GFX9-NEXT: v_mul_lo_u32 v7, v1, v4 ; GFX9-NEXT: v_mul_lo_u32 v7, v1, v4
; GFX9-NEXT: v_mul_hi_u32 v4, v1, v4 ; GFX9-NEXT: v_mul_hi_u32 v4, v1, v4
; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v7, v3 ; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v7
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v5, v4, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v5, v4, vcc
; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v8, v6, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v8, v6, vcc
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v3, v2 ; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v3, v2
; GFX9-NEXT: v_mov_b32_e32 v5, 0 ; GFX9-NEXT: v_mov_b32_e32 v5, 0
; GFX9-NEXT: v_add_co_u32_e64 v0, s[2:3], v0, v2 ; GFX9-NEXT: v_add_co_u32_e64 v0, s[2:3], v0, v2
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v5, v4, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v5, v4, vcc
; GFX9-NEXT: v_addc_co_u32_e64 v2, vcc, v1, v3, s[2:3] ; GFX9-NEXT: v_addc_co_u32_e64 v2, vcc, v1, v3, s[2:3]
; GFX9-NEXT: v_mul_lo_u32 v4, s14, v2 ; GFX9-NEXT: v_mul_lo_u32 v4, s14, v2
Show All 33 Lines
; GFX9-NEXT: v_mul_hi_u32 v7, s17, v1 ; GFX9-NEXT: v_mul_hi_u32 v7, s17, v1
; GFX9-NEXT: v_mul_lo_u32 v1, s17, v1 ; GFX9-NEXT: v_mul_lo_u32 v1, s17, v1
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v3, v2 ; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v3, v2
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v4, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v4, vcc
; GFX9-NEXT: v_mul_lo_u32 v4, s17, v0 ; GFX9-NEXT: v_mul_lo_u32 v4, s17, v0
; GFX9-NEXT: v_mul_hi_u32 v0, s17, v0 ; GFX9-NEXT: v_mul_hi_u32 v0, s17, v0
; GFX9-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24 ; GFX9-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24
; GFX9-NEXT: s_xor_b64 s[12:13], s[14:15], s[12:13] ; GFX9-NEXT: s_xor_b64 s[12:13], s[14:15], s[12:13]
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v4, v2 ; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v2, v4
; GFX9-NEXT: v_addc_co_u32_e32 v0, vcc, v3, v0, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v0, vcc, v3, v0, vcc
; GFX9-NEXT: v_addc_co_u32_e32 v2, vcc, v7, v6, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v2, vcc, v7, v6, vcc
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v1 ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v1
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v5, v2, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v5, v2, vcc
; GFX9-NEXT: v_mul_lo_u32 v2, s10, v1 ; GFX9-NEXT: v_mul_lo_u32 v2, s10, v1
; GFX9-NEXT: v_mul_hi_u32 v3, s10, v0 ; GFX9-NEXT: v_mul_hi_u32 v3, s10, v0
; GFX9-NEXT: v_mul_lo_u32 v4, s11, v0 ; GFX9-NEXT: v_mul_lo_u32 v4, s11, v0
; GFX9-NEXT: v_mov_b32_e32 v7, s11 ; GFX9-NEXT: v_mov_b32_e32 v7, s11
▲ Show 20 Lines • Show All 58 Lines • ▼ Show 20 Lines
; GFX9-NEXT: v_mul_hi_u32 v11, v4, v7 ; GFX9-NEXT: v_mul_hi_u32 v11, v4, v7
; GFX9-NEXT: v_mul_lo_u32 v7, v4, v7 ; GFX9-NEXT: v_mul_lo_u32 v7, v4, v7
; GFX9-NEXT: v_add_co_u32_e32 v8, vcc, v9, v8 ; GFX9-NEXT: v_add_co_u32_e32 v8, vcc, v9, v8
; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, 0, v10, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, 0, v10, vcc
; GFX9-NEXT: v_mul_lo_u32 v10, v4, v2 ; GFX9-NEXT: v_mul_lo_u32 v10, v4, v2
; GFX9-NEXT: v_mul_hi_u32 v2, v4, v2 ; GFX9-NEXT: v_mul_hi_u32 v2, v4, v2
; GFX9-NEXT: s_ashr_i32 s10, s7, 31 ; GFX9-NEXT: s_ashr_i32 s10, s7, 31
; GFX9-NEXT: s_mov_b32 s11, s10 ; GFX9-NEXT: s_mov_b32 s11, s10
; GFX9-NEXT: v_add_co_u32_e32 v8, vcc, v10, v8 ; GFX9-NEXT: v_add_co_u32_e32 v8, vcc, v8, v10
; GFX9-NEXT: v_addc_co_u32_e32 v2, vcc, v9, v2, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v2, vcc, v9, v2, vcc
; GFX9-NEXT: v_addc_co_u32_e32 v8, vcc, v11, v6, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v8, vcc, v11, v6, vcc
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v2, v7 ; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v2, v7
; GFX9-NEXT: v_add_co_u32_e64 v2, s[0:1], v3, v2 ; GFX9-NEXT: v_add_co_u32_e64 v2, s[0:1], v3, v2
; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, v5, v8, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, v5, v8, vcc
; GFX9-NEXT: v_addc_co_u32_e64 v3, vcc, v4, v7, s[0:1] ; GFX9-NEXT: v_addc_co_u32_e64 v3, vcc, v4, v7, s[0:1]
; GFX9-NEXT: v_mul_lo_u32 v8, s2, v3 ; GFX9-NEXT: v_mul_lo_u32 v8, s2, v3
; GFX9-NEXT: v_mul_hi_u32 v9, s2, v2 ; GFX9-NEXT: v_mul_hi_u32 v9, s2, v2
Show All 28 Lines
; GFX9-NEXT: v_mul_hi_u32 v10, s7, v3 ; GFX9-NEXT: v_mul_hi_u32 v10, s7, v3
; GFX9-NEXT: v_mul_lo_u32 v3, s7, v3 ; GFX9-NEXT: v_mul_lo_u32 v3, s7, v3
; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v7, v4 ; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v7, v4
; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, 0, v9, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, 0, v9, vcc
; GFX9-NEXT: v_mul_lo_u32 v9, s7, v2 ; GFX9-NEXT: v_mul_lo_u32 v9, s7, v2
; GFX9-NEXT: v_mul_hi_u32 v2, s7, v2 ; GFX9-NEXT: v_mul_hi_u32 v2, s7, v2
; GFX9-NEXT: v_xor_b32_e32 v0, s12, v0 ; GFX9-NEXT: v_xor_b32_e32 v0, s12, v0
; GFX9-NEXT: v_xor_b32_e32 v1, s13, v1 ; GFX9-NEXT: v_xor_b32_e32 v1, s13, v1
; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v9, v4 ; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v4, v9
; GFX9-NEXT: v_addc_co_u32_e32 v2, vcc, v7, v2, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v2, vcc, v7, v2, vcc
; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v10, v6, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v10, v6, vcc
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v2, v3 ; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v2, v3
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v5, v4, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v5, v4, vcc
; GFX9-NEXT: v_mul_lo_u32 v4, s8, v3 ; GFX9-NEXT: v_mul_lo_u32 v4, s8, v3
; GFX9-NEXT: v_mul_hi_u32 v5, s8, v2 ; GFX9-NEXT: v_mul_hi_u32 v5, s8, v2
; GFX9-NEXT: v_mul_lo_u32 v7, s9, v2 ; GFX9-NEXT: v_mul_lo_u32 v7, s9, v2
; GFX9-NEXT: v_mov_b32_e32 v8, s13 ; GFX9-NEXT: v_mov_b32_e32 v8, s13
▲ Show 20 Lines • Show All 82 Lines • ▼ Show 20 Lines
; GFX6-NEXT: v_mul_hi_u32 v3, v0, v2 ; GFX6-NEXT: v_mul_hi_u32 v3, v0, v2
; GFX6-NEXT: v_mul_hi_u32 v9, v1, v2 ; GFX6-NEXT: v_mul_hi_u32 v9, v1, v2
; GFX6-NEXT: v_mul_lo_u32 v2, v1, v2 ; GFX6-NEXT: v_mul_lo_u32 v2, v1, v2
; GFX6-NEXT: v_add_i32_e32 v5, vcc, v6, v5 ; GFX6-NEXT: v_add_i32_e32 v5, vcc, v6, v5
; GFX6-NEXT: v_mul_lo_u32 v6, v1, v4 ; GFX6-NEXT: v_mul_lo_u32 v6, v1, v4
; GFX6-NEXT: v_mul_hi_u32 v4, v1, v4 ; GFX6-NEXT: v_mul_hi_u32 v4, v1, v4
; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v8, v3, vcc ; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v8, v3, vcc
; GFX6-NEXT: s_mov_b32 s5, s9 ; GFX6-NEXT: s_mov_b32 s5, s9
; GFX6-NEXT: v_add_i32_e32 v5, vcc, v6, v5 ; GFX6-NEXT: v_add_i32_e32 v5, vcc, v5, v6
; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v3, v4, vcc ; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v3, v4, vcc
; GFX6-NEXT: v_addc_u32_e32 v4, vcc, v9, v7, vcc ; GFX6-NEXT: v_addc_u32_e32 v4, vcc, v9, v7, vcc
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2
; GFX6-NEXT: v_add_i32_e64 v0, s[0:1], v0, v2 ; GFX6-NEXT: v_add_i32_e64 v0, s[0:1], v0, v2
; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v8, v4, vcc ; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v8, v4, vcc
; GFX6-NEXT: v_addc_u32_e64 v2, vcc, v1, v3, s[0:1] ; GFX6-NEXT: v_addc_u32_e64 v2, vcc, v1, v3, s[0:1]
; GFX6-NEXT: v_mul_lo_u32 v4, v2, s2 ; GFX6-NEXT: v_mul_lo_u32 v4, v2, s2
; GFX6-NEXT: v_mul_hi_u32 v5, s2, v0 ; GFX6-NEXT: v_mul_hi_u32 v5, s2, v0
Show All 28 Lines
; GFX6-NEXT: v_mul_hi_u32 v4, s0, v1 ; GFX6-NEXT: v_mul_hi_u32 v4, s0, v1
; GFX6-NEXT: v_mul_hi_u32 v5, s1, v1 ; GFX6-NEXT: v_mul_hi_u32 v5, s1, v1
; GFX6-NEXT: v_mul_lo_u32 v1, s1, v1 ; GFX6-NEXT: v_mul_lo_u32 v1, s1, v1
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2
; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v8, v4, vcc ; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v8, v4, vcc
; GFX6-NEXT: v_mul_lo_u32 v4, s1, v0 ; GFX6-NEXT: v_mul_lo_u32 v4, s1, v0
; GFX6-NEXT: v_mul_hi_u32 v0, s1, v0 ; GFX6-NEXT: v_mul_hi_u32 v0, s1, v0
; GFX6-NEXT: s_mov_b32 s3, 0x12d8fb ; GFX6-NEXT: s_mov_b32 s3, 0x12d8fb
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v4, v2 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v4
; GFX6-NEXT: v_addc_u32_e32 v0, vcc, v3, v0, vcc ; GFX6-NEXT: v_addc_u32_e32 v0, vcc, v3, v0, vcc
; GFX6-NEXT: v_addc_u32_e32 v2, vcc, v5, v7, vcc ; GFX6-NEXT: v_addc_u32_e32 v2, vcc, v5, v7, vcc
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1 ; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1
; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v8, v2, vcc ; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v8, v2, vcc
; GFX6-NEXT: v_mul_hi_u32 v2, s3, v0 ; GFX6-NEXT: v_mul_hi_u32 v2, s3, v0
; GFX6-NEXT: v_mul_lo_u32 v1, v1, s3 ; GFX6-NEXT: v_mul_lo_u32 v1, v1, s3
; GFX6-NEXT: v_mul_lo_u32 v0, v0, s3 ; GFX6-NEXT: v_mul_lo_u32 v0, v0, s3
; GFX6-NEXT: v_add_i32_e32 v1, vcc, v2, v1 ; GFX6-NEXT: v_add_i32_e32 v1, vcc, v2, v1
▲ Show 20 Lines • Show All 51 Lines • ▼ Show 20 Lines
; GFX9-NEXT: v_mul_lo_u32 v6, v0, v2 ; GFX9-NEXT: v_mul_lo_u32 v6, v0, v2
; GFX9-NEXT: v_mul_hi_u32 v8, v0, v2 ; GFX9-NEXT: v_mul_hi_u32 v8, v0, v2
; GFX9-NEXT: v_mul_hi_u32 v9, v1, v2 ; GFX9-NEXT: v_mul_hi_u32 v9, v1, v2
; GFX9-NEXT: v_mul_lo_u32 v2, v1, v2 ; GFX9-NEXT: v_mul_lo_u32 v2, v1, v2
; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v6 ; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v6
; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, v7, v8, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, v7, v8, vcc
; GFX9-NEXT: v_mul_lo_u32 v8, v1, v4 ; GFX9-NEXT: v_mul_lo_u32 v8, v1, v4
; GFX9-NEXT: v_mul_hi_u32 v4, v1, v4 ; GFX9-NEXT: v_mul_hi_u32 v4, v1, v4
; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v8, v3 ; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v8
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v6, v4, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v6, v4, vcc
; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v9, v5, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v9, v5, vcc
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v3, v2 ; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v3, v2
; GFX9-NEXT: v_add_co_u32_e64 v0, s[2:3], v0, v2 ; GFX9-NEXT: v_add_co_u32_e64 v0, s[2:3], v0, v2
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v7, v4, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v7, v4, vcc
; GFX9-NEXT: v_addc_co_u32_e64 v2, vcc, v1, v3, s[2:3] ; GFX9-NEXT: v_addc_co_u32_e64 v2, vcc, v1, v3, s[2:3]
; GFX9-NEXT: v_mul_lo_u32 v4, v2, s8 ; GFX9-NEXT: v_mul_lo_u32 v4, v2, s8
; GFX9-NEXT: v_mul_hi_u32 v6, s8, v0 ; GFX9-NEXT: v_mul_hi_u32 v6, s8, v0
Show All 29 Lines
; GFX9-NEXT: v_mul_hi_u32 v4, s0, v1 ; GFX9-NEXT: v_mul_hi_u32 v4, s0, v1
; GFX9-NEXT: v_mul_hi_u32 v6, s1, v1 ; GFX9-NEXT: v_mul_hi_u32 v6, s1, v1
; GFX9-NEXT: v_mul_lo_u32 v1, s1, v1 ; GFX9-NEXT: v_mul_lo_u32 v1, s1, v1
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v3, v2 ; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v3, v2
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v7, v4, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v7, v4, vcc
; GFX9-NEXT: v_mul_lo_u32 v4, s1, v0 ; GFX9-NEXT: v_mul_lo_u32 v4, s1, v0
; GFX9-NEXT: v_mul_hi_u32 v0, s1, v0 ; GFX9-NEXT: v_mul_hi_u32 v0, s1, v0
; GFX9-NEXT: s_mov_b32 s3, 0x12d8fb ; GFX9-NEXT: s_mov_b32 s3, 0x12d8fb
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v4, v2 ; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v2, v4
; GFX9-NEXT: v_addc_co_u32_e32 v0, vcc, v3, v0, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v0, vcc, v3, v0, vcc
; GFX9-NEXT: v_addc_co_u32_e32 v2, vcc, v6, v5, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v2, vcc, v6, v5, vcc
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v1 ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v1
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v7, v2, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v7, v2, vcc
; GFX9-NEXT: v_mul_hi_u32 v2, s3, v0 ; GFX9-NEXT: v_mul_hi_u32 v2, s3, v0
; GFX9-NEXT: v_mul_lo_u32 v1, v1, s3 ; GFX9-NEXT: v_mul_lo_u32 v1, v1, s3
; GFX9-NEXT: v_mul_lo_u32 v0, v0, s3 ; GFX9-NEXT: v_mul_lo_u32 v0, v0, s3
; GFX9-NEXT: v_add_u32_e32 v1, v2, v1 ; GFX9-NEXT: v_add_u32_e32 v1, v2, v1
▲ Show 20 Lines • Show All 126 Lines • ▼ Show 20 Lines
; GFX6-NEXT: v_mul_lo_u32 v5, v0, v2 ; GFX6-NEXT: v_mul_lo_u32 v5, v0, v2
; GFX6-NEXT: v_mul_hi_u32 v6, v0, v2 ; GFX6-NEXT: v_mul_hi_u32 v6, v0, v2
; GFX6-NEXT: v_mul_hi_u32 v7, v1, v2 ; GFX6-NEXT: v_mul_hi_u32 v7, v1, v2
; GFX6-NEXT: v_mul_lo_u32 v2, v1, v2 ; GFX6-NEXT: v_mul_lo_u32 v2, v1, v2
; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v5 ; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v5
; GFX6-NEXT: v_addc_u32_e32 v5, vcc, 0, v6, vcc ; GFX6-NEXT: v_addc_u32_e32 v5, vcc, 0, v6, vcc
; GFX6-NEXT: v_mul_lo_u32 v6, v1, v4 ; GFX6-NEXT: v_mul_lo_u32 v6, v1, v4
; GFX6-NEXT: v_mul_hi_u32 v4, v1, v4 ; GFX6-NEXT: v_mul_hi_u32 v4, v1, v4
; GFX6-NEXT: v_add_i32_e32 v3, vcc, v6, v3 ; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v6
; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v5, v4, vcc ; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v5, v4, vcc
; GFX6-NEXT: v_mov_b32_e32 v4, 0 ; GFX6-NEXT: v_mov_b32_e32 v4, 0
; GFX6-NEXT: v_addc_u32_e32 v5, vcc, v7, v4, vcc ; GFX6-NEXT: v_addc_u32_e32 v5, vcc, v7, v4, vcc
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2
; GFX6-NEXT: v_mov_b32_e32 v6, 0 ; GFX6-NEXT: v_mov_b32_e32 v6, 0
; GFX6-NEXT: v_add_i32_e64 v0, s[0:1], v0, v2 ; GFX6-NEXT: v_add_i32_e64 v0, s[0:1], v0, v2
; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v6, v5, vcc ; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v6, v5, vcc
; GFX6-NEXT: v_addc_u32_e64 v2, vcc, v1, v3, s[0:1] ; GFX6-NEXT: v_addc_u32_e64 v2, vcc, v1, v3, s[0:1]
Show All 28 Lines
; GFX6-NEXT: v_mul_hi_u32 v3, s10, v0 ; GFX6-NEXT: v_mul_hi_u32 v3, s10, v0
; GFX6-NEXT: v_mul_hi_u32 v5, s10, v1 ; GFX6-NEXT: v_mul_hi_u32 v5, s10, v1
; GFX6-NEXT: v_mul_hi_u32 v7, s11, v1 ; GFX6-NEXT: v_mul_hi_u32 v7, s11, v1
; GFX6-NEXT: v_mul_lo_u32 v1, s11, v1 ; GFX6-NEXT: v_mul_lo_u32 v1, s11, v1
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2
; GFX6-NEXT: v_addc_u32_e32 v3, vcc, 0, v5, vcc ; GFX6-NEXT: v_addc_u32_e32 v3, vcc, 0, v5, vcc
; GFX6-NEXT: v_mul_lo_u32 v5, s11, v0 ; GFX6-NEXT: v_mul_lo_u32 v5, s11, v0
; GFX6-NEXT: v_mul_hi_u32 v0, s11, v0 ; GFX6-NEXT: v_mul_hi_u32 v0, s11, v0
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v5, v2 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v5
; GFX6-NEXT: v_addc_u32_e32 v0, vcc, v3, v0, vcc ; GFX6-NEXT: v_addc_u32_e32 v0, vcc, v3, v0, vcc
; GFX6-NEXT: v_addc_u32_e32 v2, vcc, v7, v4, vcc ; GFX6-NEXT: v_addc_u32_e32 v2, vcc, v7, v4, vcc
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1 ; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1
; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v6, v2, vcc ; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v6, v2, vcc
; GFX6-NEXT: v_mul_lo_u32 v1, s12, v1 ; GFX6-NEXT: v_mul_lo_u32 v1, s12, v1
; GFX6-NEXT: v_mul_hi_u32 v2, s12, v0 ; GFX6-NEXT: v_mul_hi_u32 v2, s12, v0
; GFX6-NEXT: v_mul_lo_u32 v3, s13, v0 ; GFX6-NEXT: v_mul_lo_u32 v3, s13, v0
; GFX6-NEXT: v_mul_lo_u32 v0, s12, v0 ; GFX6-NEXT: v_mul_lo_u32 v0, s12, v0
▲ Show 20 Lines • Show All 71 Lines • ▼ Show 20 Lines
; GFX9-NEXT: v_mul_lo_u32 v6, v0, v3 ; GFX9-NEXT: v_mul_lo_u32 v6, v0, v3
; GFX9-NEXT: v_mul_hi_u32 v8, v0, v3 ; GFX9-NEXT: v_mul_hi_u32 v8, v0, v3
; GFX9-NEXT: v_mul_hi_u32 v7, v1, v5 ; GFX9-NEXT: v_mul_hi_u32 v7, v1, v5
; GFX9-NEXT: v_mul_lo_u32 v5, v1, v5 ; GFX9-NEXT: v_mul_lo_u32 v5, v1, v5
; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v4, v6 ; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v4, v6
; GFX9-NEXT: v_mul_hi_u32 v9, v1, v3 ; GFX9-NEXT: v_mul_hi_u32 v9, v1, v3
; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, 0, v8, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, 0, v8, vcc
; GFX9-NEXT: v_mul_lo_u32 v3, v1, v3 ; GFX9-NEXT: v_mul_lo_u32 v3, v1, v3
; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v5, v4 ; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v4, v5
; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v6, v7, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v6, v7, vcc
; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, v9, v2, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, v9, v2, vcc
; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v4, v3 ; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v4, v3
; GFX9-NEXT: v_mov_b32_e32 v6, 0 ; GFX9-NEXT: v_mov_b32_e32 v6, 0
; GFX9-NEXT: v_add_co_u32_e64 v0, s[2:3], v0, v3 ; GFX9-NEXT: v_add_co_u32_e64 v0, s[2:3], v0, v3
; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v6, v5, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v6, v5, vcc
; GFX9-NEXT: v_addc_co_u32_e64 v3, vcc, v1, v4, s[2:3] ; GFX9-NEXT: v_addc_co_u32_e64 v3, vcc, v1, v4, s[2:3]
; GFX9-NEXT: v_mul_lo_u32 v5, s10, v3 ; GFX9-NEXT: v_mul_lo_u32 v5, s10, v3
Show All 31 Lines
; GFX9-NEXT: v_mul_hi_u32 v4, s6, v0 ; GFX9-NEXT: v_mul_hi_u32 v4, s6, v0
; GFX9-NEXT: v_mul_hi_u32 v5, s6, v1 ; GFX9-NEXT: v_mul_hi_u32 v5, s6, v1
; GFX9-NEXT: v_mul_hi_u32 v7, s7, v1 ; GFX9-NEXT: v_mul_hi_u32 v7, s7, v1
; GFX9-NEXT: v_mul_lo_u32 v1, s7, v1 ; GFX9-NEXT: v_mul_lo_u32 v1, s7, v1
; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v4, v3 ; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v4, v3
; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, 0, v5, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, 0, v5, vcc
; GFX9-NEXT: v_mul_lo_u32 v5, s7, v0 ; GFX9-NEXT: v_mul_lo_u32 v5, s7, v0
; GFX9-NEXT: v_mul_hi_u32 v0, s7, v0 ; GFX9-NEXT: v_mul_hi_u32 v0, s7, v0
; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v5, v3 ; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v5
; GFX9-NEXT: v_addc_co_u32_e32 v0, vcc, v4, v0, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v0, vcc, v4, v0, vcc
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v7, v2, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v7, v2, vcc
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v1 ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v1
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v6, v3, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v6, v3, vcc
; GFX9-NEXT: v_mul_lo_u32 v1, s8, v1 ; GFX9-NEXT: v_mul_lo_u32 v1, s8, v1
; GFX9-NEXT: v_mul_hi_u32 v3, s8, v0 ; GFX9-NEXT: v_mul_hi_u32 v3, s8, v0
; GFX9-NEXT: v_mul_lo_u32 v4, s9, v0 ; GFX9-NEXT: v_mul_lo_u32 v4, s9, v0
; GFX9-NEXT: v_mul_lo_u32 v0, s8, v0 ; GFX9-NEXT: v_mul_lo_u32 v0, s8, v0
▲ Show 20 Lines • Show All 174 Lines • ▼ Show 20 Lines
; GFX6-NEXT: v_mul_hi_u32 v7, v1, v2 ; GFX6-NEXT: v_mul_hi_u32 v7, v1, v2
; GFX6-NEXT: v_mul_lo_u32 v2, v1, v2 ; GFX6-NEXT: v_mul_lo_u32 v2, v1, v2
; GFX6-NEXT: v_add_i32_e32 v3, vcc, v4, v3 ; GFX6-NEXT: v_add_i32_e32 v3, vcc, v4, v3
; GFX6-NEXT: v_addc_u32_e32 v4, vcc, 0, v6, vcc ; GFX6-NEXT: v_addc_u32_e32 v4, vcc, 0, v6, vcc
; GFX6-NEXT: v_mul_lo_u32 v6, v1, v5 ; GFX6-NEXT: v_mul_lo_u32 v6, v1, v5
; GFX6-NEXT: v_mul_hi_u32 v5, v1, v5 ; GFX6-NEXT: v_mul_hi_u32 v5, v1, v5
; GFX6-NEXT: s_addc_u32 s1, s9, s12 ; GFX6-NEXT: s_addc_u32 s1, s9, s12
; GFX6-NEXT: s_xor_b64 s[8:9], s[0:1], s[12:13] ; GFX6-NEXT: s_xor_b64 s[8:9], s[0:1], s[12:13]
; GFX6-NEXT: v_add_i32_e32 v3, vcc, v6, v3 ; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v6
; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v4, v5, vcc ; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v4, v5, vcc
; GFX6-NEXT: v_mov_b32_e32 v4, 0 ; GFX6-NEXT: v_mov_b32_e32 v4, 0
; GFX6-NEXT: v_addc_u32_e32 v5, vcc, v7, v4, vcc ; GFX6-NEXT: v_addc_u32_e32 v5, vcc, v7, v4, vcc
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2
; GFX6-NEXT: v_mov_b32_e32 v6, 0 ; GFX6-NEXT: v_mov_b32_e32 v6, 0
; GFX6-NEXT: v_add_i32_e64 v0, s[2:3], v0, v2 ; GFX6-NEXT: v_add_i32_e64 v0, s[2:3], v0, v2
; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v6, v5, vcc ; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v6, v5, vcc
; GFX6-NEXT: v_addc_u32_e64 v2, vcc, v1, v3, s[2:3] ; GFX6-NEXT: v_addc_u32_e64 v2, vcc, v1, v3, s[2:3]
Show All 27 Lines
; GFX6-NEXT: v_mul_hi_u32 v5, s8, v1 ; GFX6-NEXT: v_mul_hi_u32 v5, s8, v1
; GFX6-NEXT: v_mul_hi_u32 v7, s9, v1 ; GFX6-NEXT: v_mul_hi_u32 v7, s9, v1
; GFX6-NEXT: v_mul_lo_u32 v1, s9, v1 ; GFX6-NEXT: v_mul_lo_u32 v1, s9, v1
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2
; GFX6-NEXT: v_addc_u32_e32 v3, vcc, 0, v5, vcc ; GFX6-NEXT: v_addc_u32_e32 v3, vcc, 0, v5, vcc
; GFX6-NEXT: v_mul_lo_u32 v5, s9, v0 ; GFX6-NEXT: v_mul_lo_u32 v5, s9, v0
; GFX6-NEXT: v_mul_hi_u32 v0, s9, v0 ; GFX6-NEXT: v_mul_hi_u32 v0, s9, v0
; GFX6-NEXT: s_mov_b32 s6, -1 ; GFX6-NEXT: s_mov_b32 s6, -1
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v5, v2 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v5
; GFX6-NEXT: v_addc_u32_e32 v0, vcc, v3, v0, vcc ; GFX6-NEXT: v_addc_u32_e32 v0, vcc, v3, v0, vcc
; GFX6-NEXT: v_addc_u32_e32 v2, vcc, v7, v4, vcc ; GFX6-NEXT: v_addc_u32_e32 v2, vcc, v7, v4, vcc
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1 ; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1
; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v6, v2, vcc ; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v6, v2, vcc
; GFX6-NEXT: v_mul_lo_u32 v1, s16, v1 ; GFX6-NEXT: v_mul_lo_u32 v1, s16, v1
; GFX6-NEXT: v_mul_hi_u32 v2, s16, v0 ; GFX6-NEXT: v_mul_hi_u32 v2, s16, v0
; GFX6-NEXT: v_mul_lo_u32 v3, s17, v0 ; GFX6-NEXT: v_mul_lo_u32 v3, s17, v0
; GFX6-NEXT: v_mul_lo_u32 v0, s16, v0 ; GFX6-NEXT: v_mul_lo_u32 v0, s16, v0
▲ Show 20 Lines • Show All 59 Lines • ▼ Show 20 Lines
; GFX6-NEXT: v_mul_lo_u32 v2, v5, v2 ; GFX6-NEXT: v_mul_lo_u32 v2, v5, v2
; GFX6-NEXT: s_mov_b32 s15, s14 ; GFX6-NEXT: s_mov_b32 s15, s14
; GFX6-NEXT: v_add_i32_e32 v8, vcc, v9, v8 ; GFX6-NEXT: v_add_i32_e32 v8, vcc, v9, v8
; GFX6-NEXT: v_addc_u32_e32 v9, vcc, 0, v10, vcc ; GFX6-NEXT: v_addc_u32_e32 v9, vcc, 0, v10, vcc
; GFX6-NEXT: v_mul_lo_u32 v10, v5, v7 ; GFX6-NEXT: v_mul_lo_u32 v10, v5, v7
; GFX6-NEXT: v_mul_hi_u32 v7, v5, v7 ; GFX6-NEXT: v_mul_hi_u32 v7, v5, v7
; GFX6-NEXT: v_xor_b32_e32 v0, s12, v0 ; GFX6-NEXT: v_xor_b32_e32 v0, s12, v0
; GFX6-NEXT: v_xor_b32_e32 v1, s12, v1 ; GFX6-NEXT: v_xor_b32_e32 v1, s12, v1
; GFX6-NEXT: v_add_i32_e32 v8, vcc, v10, v8 ; GFX6-NEXT: v_add_i32_e32 v8, vcc, v8, v10
; GFX6-NEXT: v_addc_u32_e32 v7, vcc, v9, v7, vcc ; GFX6-NEXT: v_addc_u32_e32 v7, vcc, v9, v7, vcc
; GFX6-NEXT: v_addc_u32_e32 v8, vcc, v11, v4, vcc ; GFX6-NEXT: v_addc_u32_e32 v8, vcc, v11, v4, vcc
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v7, v2 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v7, v2
; GFX6-NEXT: v_add_i32_e64 v2, s[0:1], v3, v2 ; GFX6-NEXT: v_add_i32_e64 v2, s[0:1], v3, v2
; GFX6-NEXT: v_addc_u32_e32 v7, vcc, v6, v8, vcc ; GFX6-NEXT: v_addc_u32_e32 v7, vcc, v6, v8, vcc
; GFX6-NEXT: v_addc_u32_e64 v3, vcc, v5, v7, s[0:1] ; GFX6-NEXT: v_addc_u32_e64 v3, vcc, v5, v7, s[0:1]
; GFX6-NEXT: v_mul_lo_u32 v8, s2, v3 ; GFX6-NEXT: v_mul_lo_u32 v8, s2, v3
; GFX6-NEXT: v_mul_hi_u32 v9, s2, v2 ; GFX6-NEXT: v_mul_hi_u32 v9, s2, v2
Show All 27 Lines
; GFX6-NEXT: v_mul_hi_u32 v9, s10, v3 ; GFX6-NEXT: v_mul_hi_u32 v9, s10, v3
; GFX6-NEXT: v_mul_hi_u32 v10, s11, v3 ; GFX6-NEXT: v_mul_hi_u32 v10, s11, v3
; GFX6-NEXT: v_mul_lo_u32 v3, s11, v3 ; GFX6-NEXT: v_mul_lo_u32 v3, s11, v3
; GFX6-NEXT: v_add_i32_e32 v5, vcc, v7, v5 ; GFX6-NEXT: v_add_i32_e32 v5, vcc, v7, v5
; GFX6-NEXT: v_addc_u32_e32 v7, vcc, 0, v9, vcc ; GFX6-NEXT: v_addc_u32_e32 v7, vcc, 0, v9, vcc
; GFX6-NEXT: v_mul_lo_u32 v9, s11, v2 ; GFX6-NEXT: v_mul_lo_u32 v9, s11, v2
; GFX6-NEXT: v_mul_hi_u32 v2, s11, v2 ; GFX6-NEXT: v_mul_hi_u32 v2, s11, v2
; GFX6-NEXT: v_mov_b32_e32 v8, s12 ; GFX6-NEXT: v_mov_b32_e32 v8, s12
; GFX6-NEXT: v_add_i32_e32 v5, vcc, v9, v5 ; GFX6-NEXT: v_add_i32_e32 v5, vcc, v5, v9
; GFX6-NEXT: v_addc_u32_e32 v2, vcc, v7, v2, vcc ; GFX6-NEXT: v_addc_u32_e32 v2, vcc, v7, v2, vcc
; GFX6-NEXT: v_addc_u32_e32 v4, vcc, v10, v4, vcc ; GFX6-NEXT: v_addc_u32_e32 v4, vcc, v10, v4, vcc
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v3 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v3
; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v6, v4, vcc ; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v6, v4, vcc
; GFX6-NEXT: v_mul_lo_u32 v3, s8, v3 ; GFX6-NEXT: v_mul_lo_u32 v3, s8, v3
; GFX6-NEXT: v_mul_hi_u32 v4, s8, v2 ; GFX6-NEXT: v_mul_hi_u32 v4, s8, v2
; GFX6-NEXT: v_mul_lo_u32 v5, s9, v2 ; GFX6-NEXT: v_mul_lo_u32 v5, s9, v2
; GFX6-NEXT: v_subrev_i32_e32 v0, vcc, s12, v0 ; GFX6-NEXT: v_subrev_i32_e32 v0, vcc, s12, v0
▲ Show 20 Lines • Show All 82 Lines • ▼ Show 20 Lines
; GFX9-NEXT: v_mul_lo_u32 v5, v0, v2 ; GFX9-NEXT: v_mul_lo_u32 v5, v0, v2
; GFX9-NEXT: v_mul_hi_u32 v7, v0, v2 ; GFX9-NEXT: v_mul_hi_u32 v7, v0, v2
; GFX9-NEXT: v_mul_hi_u32 v8, v1, v2 ; GFX9-NEXT: v_mul_hi_u32 v8, v1, v2
; GFX9-NEXT: v_mul_lo_u32 v2, v1, v2 ; GFX9-NEXT: v_mul_lo_u32 v2, v1, v2
; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v5 ; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v5
; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v7, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v7, vcc
; GFX9-NEXT: v_mul_lo_u32 v7, v1, v4 ; GFX9-NEXT: v_mul_lo_u32 v7, v1, v4
; GFX9-NEXT: v_mul_hi_u32 v4, v1, v4 ; GFX9-NEXT: v_mul_hi_u32 v4, v1, v4
; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v7, v3 ; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v7
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v5, v4, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v5, v4, vcc
; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v8, v6, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v8, v6, vcc
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v3, v2 ; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v3, v2
; GFX9-NEXT: v_mov_b32_e32 v5, 0 ; GFX9-NEXT: v_mov_b32_e32 v5, 0
; GFX9-NEXT: v_add_co_u32_e64 v0, s[2:3], v0, v2 ; GFX9-NEXT: v_add_co_u32_e64 v0, s[2:3], v0, v2
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v5, v4, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v5, v4, vcc
; GFX9-NEXT: v_addc_co_u32_e64 v2, vcc, v1, v3, s[2:3] ; GFX9-NEXT: v_addc_co_u32_e64 v2, vcc, v1, v3, s[2:3]
; GFX9-NEXT: v_mul_lo_u32 v4, s4, v2 ; GFX9-NEXT: v_mul_lo_u32 v4, s4, v2
Show All 28 Lines
; GFX9-NEXT: v_mul_hi_u32 v4, s8, v1 ; GFX9-NEXT: v_mul_hi_u32 v4, s8, v1
; GFX9-NEXT: v_mul_hi_u32 v7, s9, v1 ; GFX9-NEXT: v_mul_hi_u32 v7, s9, v1
; GFX9-NEXT: v_mul_lo_u32 v1, s9, v1 ; GFX9-NEXT: v_mul_lo_u32 v1, s9, v1
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v3, v2 ; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v3, v2
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v4, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v4, vcc
; GFX9-NEXT: v_mul_lo_u32 v4, s9, v0 ; GFX9-NEXT: v_mul_lo_u32 v4, s9, v0
; GFX9-NEXT: v_mul_hi_u32 v0, s9, v0 ; GFX9-NEXT: v_mul_hi_u32 v0, s9, v0
; GFX9-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24 ; GFX9-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v4, v2 ; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v2, v4
; GFX9-NEXT: v_addc_co_u32_e32 v0, vcc, v3, v0, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v0, vcc, v3, v0, vcc
; GFX9-NEXT: v_addc_co_u32_e32 v2, vcc, v7, v6, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v2, vcc, v7, v6, vcc
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v1 ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v1
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v5, v2, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v5, v2, vcc
; GFX9-NEXT: v_mul_lo_u32 v1, s14, v1 ; GFX9-NEXT: v_mul_lo_u32 v1, s14, v1
; GFX9-NEXT: v_mul_hi_u32 v2, s14, v0 ; GFX9-NEXT: v_mul_hi_u32 v2, s14, v0
; GFX9-NEXT: v_mul_lo_u32 v3, s15, v0 ; GFX9-NEXT: v_mul_lo_u32 v3, s15, v0
; GFX9-NEXT: v_mul_lo_u32 v0, s14, v0 ; GFX9-NEXT: v_mul_lo_u32 v0, s14, v0
▲ Show 20 Lines • Show All 57 Lines • ▼ Show 20 Lines
; GFX9-NEXT: v_mul_hi_u32 v11, v4, v7 ; GFX9-NEXT: v_mul_hi_u32 v11, v4, v7
; GFX9-NEXT: v_mul_lo_u32 v7, v4, v7 ; GFX9-NEXT: v_mul_lo_u32 v7, v4, v7
; GFX9-NEXT: v_add_co_u32_e32 v8, vcc, v9, v8 ; GFX9-NEXT: v_add_co_u32_e32 v8, vcc, v9, v8
; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, 0, v10, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, 0, v10, vcc
; GFX9-NEXT: v_mul_lo_u32 v10, v4, v2 ; GFX9-NEXT: v_mul_lo_u32 v10, v4, v2
; GFX9-NEXT: v_mul_hi_u32 v2, v4, v2 ; GFX9-NEXT: v_mul_hi_u32 v2, v4, v2
; GFX9-NEXT: s_ashr_i32 s12, s11, 31 ; GFX9-NEXT: s_ashr_i32 s12, s11, 31
; GFX9-NEXT: s_mov_b32 s13, s12 ; GFX9-NEXT: s_mov_b32 s13, s12
; GFX9-NEXT: v_add_co_u32_e32 v8, vcc, v10, v8 ; GFX9-NEXT: v_add_co_u32_e32 v8, vcc, v8, v10
; GFX9-NEXT: v_addc_co_u32_e32 v2, vcc, v9, v2, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v2, vcc, v9, v2, vcc
; GFX9-NEXT: v_addc_co_u32_e32 v8, vcc, v11, v6, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v8, vcc, v11, v6, vcc
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v2, v7 ; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v2, v7
; GFX9-NEXT: v_add_co_u32_e64 v2, s[0:1], v3, v2 ; GFX9-NEXT: v_add_co_u32_e64 v2, s[0:1], v3, v2
; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, v5, v8, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, v5, v8, vcc
; GFX9-NEXT: v_addc_co_u32_e64 v3, vcc, v4, v7, s[0:1] ; GFX9-NEXT: v_addc_co_u32_e64 v3, vcc, v4, v7, s[0:1]
; GFX9-NEXT: v_mul_lo_u32 v8, s2, v3 ; GFX9-NEXT: v_mul_lo_u32 v8, s2, v3
; GFX9-NEXT: v_mul_hi_u32 v9, s2, v2 ; GFX9-NEXT: v_mul_hi_u32 v9, s2, v2
Show All 28 Lines
; GFX9-NEXT: v_mul_hi_u32 v10, s11, v3 ; GFX9-NEXT: v_mul_hi_u32 v10, s11, v3
; GFX9-NEXT: v_mul_lo_u32 v3, s11, v3 ; GFX9-NEXT: v_mul_lo_u32 v3, s11, v3
; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v7, v4 ; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v7, v4
; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, 0, v9, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, 0, v9, vcc
; GFX9-NEXT: v_mul_lo_u32 v9, s11, v2 ; GFX9-NEXT: v_mul_lo_u32 v9, s11, v2
; GFX9-NEXT: v_mul_hi_u32 v2, s11, v2 ; GFX9-NEXT: v_mul_hi_u32 v2, s11, v2
; GFX9-NEXT: v_xor_b32_e32 v0, s6, v0 ; GFX9-NEXT: v_xor_b32_e32 v0, s6, v0
; GFX9-NEXT: v_xor_b32_e32 v1, s6, v1 ; GFX9-NEXT: v_xor_b32_e32 v1, s6, v1
; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v9, v4 ; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v4, v9
; GFX9-NEXT: v_addc_co_u32_e32 v2, vcc, v7, v2, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v2, vcc, v7, v2, vcc
; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v10, v6, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v10, v6, vcc
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v2, v3 ; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v2, v3
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v5, v4, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v5, v4, vcc
; GFX9-NEXT: v_mul_lo_u32 v3, s8, v3 ; GFX9-NEXT: v_mul_lo_u32 v3, s8, v3
; GFX9-NEXT: v_mul_hi_u32 v4, s8, v2 ; GFX9-NEXT: v_mul_hi_u32 v4, s8, v2
; GFX9-NEXT: v_mul_lo_u32 v5, s9, v2 ; GFX9-NEXT: v_mul_lo_u32 v5, s9, v2
; GFX9-NEXT: v_mul_lo_u32 v2, s8, v2 ; GFX9-NEXT: v_mul_lo_u32 v2, s8, v2
▲ Show 20 Lines • Show All 47 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/change-scc-to-vcc.mir

  • This file was added.
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -mcpu=gfx1030 -run-pass=si-fix-sgpr-copies -verify-machineinstrs -o - %s | FileCheck --check-prefix=GCN %s
# Test that the Fix SGPR Copy pass changes scc definitions to vcc if the
# instruction that uses the scc is changed to use vcc.
---
name: change_scc_def
body: |
bb.0:
; GCN-LABEL: name: change_scc_def
; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 681
; GCN: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
; GCN: [[DEF1:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
; GCN: [[DEF2:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
; GCN: [[DEF3:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
; GCN: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 1
; GCN: [[S_MOV_B32_2:%[0-9]+]]:sreg_32 = S_MOV_B32 0
; GCN: [[V_MUL_HI_U32_U24_e64_:%[0-9]+]]:vgpr_32 = V_MUL_HI_U32_U24_e64 [[S_MOV_B32_1]], [[S_MOV_B32_]], implicit $exec
; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY killed [[DEF1]]
; GCN: [[V_ADD_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 killed [[DEF]], [[COPY]], implicit-def $vcc_lo, implicit $exec
; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY killed [[DEF3]]
; GCN: [[V_ADDC_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADDC_U32_e32 killed [[DEF2]], [[COPY1]], implicit-def $vcc_lo, implicit $vcc_lo, implicit $exec
; GCN: [[DEF4:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_2]]
; GCN: [[V_ADDC_U32_e32_1:%[0-9]+]]:vgpr_32 = V_ADDC_U32_e32 [[V_MUL_HI_U32_U24_e64_]], [[COPY2]], implicit-def $vcc_lo, implicit $vcc_lo, implicit $exec
%0:sreg_32 = S_MOV_B32 681
%1:sreg_32 = IMPLICIT_DEF
%2:sreg_32 = IMPLICIT_DEF
%3:sreg_32 = IMPLICIT_DEF
%4:sreg_32 = IMPLICIT_DEF
%5:sreg_32 = S_MOV_B32 1
%6:sreg_32 = S_MOV_B32 0
%7:vgpr_32 = V_MUL_HI_U32_U24_e64 %5, %0, implicit $exec
%8:sreg_32 = S_ADD_U32 killed %1, killed %2, implicit-def $scc
%9:sreg_32 = S_ADDC_U32 killed %3, killed %4, implicit-def $scc, implicit $scc
%10:sreg_32 = COPY %7
%11:sreg_32 = S_ADDC_U32 killed %10, %6, implicit-def dead $scc, implicit $scc
...
# This case successfully converted scc definitions to vcc because the input
# to the first add is a vgpr. This test checks that it still works correctly.
---
name: test-working-scc-def
body: |
bb.0:
; GCN-LABEL: name: test-working-scc-def
; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GCN: [[DEF1:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GCN: [[DEF2:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
; GCN: [[DEF3:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
; GCN: [[DEF4:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
; GCN: [[DEF5:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
; GCN: [[DEF6:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
; GCN: [[V_ADD_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 killed [[DEF2]], [[DEF]], implicit-def $vcc_lo, implicit $exec
; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY killed [[DEF4]]
; GCN: [[V_ADDC_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADDC_U32_e32 killed [[DEF3]], [[COPY]], implicit-def $vcc_lo, implicit $vcc_lo, implicit $exec
; GCN: [[DEF7:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[DEF5]]
; GCN: [[V_ADDC_U32_e32_1:%[0-9]+]]:vgpr_32 = V_ADDC_U32_e32 killed [[V_ADDC_U32_e32_1]], [[COPY1]], implicit-def $vcc_lo, implicit $vcc_lo, implicit $exec
%0:vgpr_32 = IMPLICIT_DEF
%1:vgpr_32 = IMPLICIT_DEF
%2:sreg_32 = IMPLICIT_DEF
%3:sreg_32 = IMPLICIT_DEF
%4:sreg_32 = IMPLICIT_DEF
%5:sreg_32 = IMPLICIT_DEF
%6:sreg_32 = COPY %0
%7:sreg_32 = S_ADD_U32 killed %6, killed %2, implicit-def $scc
%8:sreg_32 = S_ADDC_U32 killed %3, killed %4, implicit-def $scc, implicit $scc
%9:sreg_32 = COPY %1
%10:sreg_32 = S_ADDC_U32 killed %10, %5, implicit-def dead $scc, implicit $scc
...

llvm/test/CodeGen/AMDGPU/sdiv64.ll

Show All 40 Lines
; GCN-NEXT: v_mul_lo_u32 v6, v0, v3 ; GCN-NEXT: v_mul_lo_u32 v6, v0, v3
; GCN-NEXT: v_mul_hi_u32 v8, v0, v3 ; GCN-NEXT: v_mul_hi_u32 v8, v0, v3
; GCN-NEXT: v_mul_hi_u32 v9, v2, v3 ; GCN-NEXT: v_mul_hi_u32 v9, v2, v3
; GCN-NEXT: v_mul_lo_u32 v3, v2, v3 ; GCN-NEXT: v_mul_lo_u32 v3, v2, v3
; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v6 ; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v6
; GCN-NEXT: v_addc_u32_e32 v6, vcc, v7, v8, vcc ; GCN-NEXT: v_addc_u32_e32 v6, vcc, v7, v8, vcc
; GCN-NEXT: v_mul_lo_u32 v8, v2, v5 ; GCN-NEXT: v_mul_lo_u32 v8, v2, v5
; GCN-NEXT: v_mul_hi_u32 v5, v2, v5 ; GCN-NEXT: v_mul_hi_u32 v5, v2, v5
; GCN-NEXT: v_add_i32_e32 v4, vcc, v8, v4 ; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v8
; GCN-NEXT: v_addc_u32_e32 v4, vcc, v6, v5, vcc ; GCN-NEXT: v_addc_u32_e32 v4, vcc, v6, v5, vcc
; GCN-NEXT: v_addc_u32_e32 v5, vcc, v9, v1, vcc ; GCN-NEXT: v_addc_u32_e32 v5, vcc, v9, v1, vcc
; GCN-NEXT: v_add_i32_e32 v3, vcc, v4, v3 ; GCN-NEXT: v_add_i32_e32 v3, vcc, v4, v3
; GCN-NEXT: v_add_i32_e64 v0, s[0:1], v0, v3 ; GCN-NEXT: v_add_i32_e64 v0, s[0:1], v0, v3
; GCN-NEXT: v_addc_u32_e32 v4, vcc, v7, v5, vcc ; GCN-NEXT: v_addc_u32_e32 v4, vcc, v7, v5, vcc
; GCN-NEXT: v_addc_u32_e64 v3, vcc, v2, v4, s[0:1] ; GCN-NEXT: v_addc_u32_e64 v3, vcc, v2, v4, s[0:1]
; GCN-NEXT: v_mul_lo_u32 v5, s4, v3 ; GCN-NEXT: v_mul_lo_u32 v5, s4, v3
; GCN-NEXT: v_mul_hi_u32 v6, s4, v0 ; GCN-NEXT: v_mul_hi_u32 v6, s4, v0
Show All 28 Lines
; GCN-NEXT: v_mul_hi_u32 v5, s10, v2 ; GCN-NEXT: v_mul_hi_u32 v5, s10, v2
; GCN-NEXT: v_mul_hi_u32 v6, s11, v2 ; GCN-NEXT: v_mul_hi_u32 v6, s11, v2
; GCN-NEXT: v_mul_lo_u32 v2, s11, v2 ; GCN-NEXT: v_mul_lo_u32 v2, s11, v2
; GCN-NEXT: v_add_i32_e32 v3, vcc, v4, v3 ; GCN-NEXT: v_add_i32_e32 v3, vcc, v4, v3
; GCN-NEXT: v_addc_u32_e32 v4, vcc, v7, v5, vcc ; GCN-NEXT: v_addc_u32_e32 v4, vcc, v7, v5, vcc
; GCN-NEXT: v_mul_lo_u32 v5, s11, v0 ; GCN-NEXT: v_mul_lo_u32 v5, s11, v0
; GCN-NEXT: v_mul_hi_u32 v0, s11, v0 ; GCN-NEXT: v_mul_hi_u32 v0, s11, v0
; GCN-NEXT: s_mov_b32 s4, s8 ; GCN-NEXT: s_mov_b32 s4, s8
; GCN-NEXT: v_add_i32_e32 v3, vcc, v5, v3 ; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v5
; GCN-NEXT: v_addc_u32_e32 v0, vcc, v4, v0, vcc ; GCN-NEXT: v_addc_u32_e32 v0, vcc, v4, v0, vcc
; GCN-NEXT: v_addc_u32_e32 v1, vcc, v6, v1, vcc ; GCN-NEXT: v_addc_u32_e32 v1, vcc, v6, v1, vcc
; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2 ; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2
; GCN-NEXT: v_addc_u32_e32 v1, vcc, v7, v1, vcc ; GCN-NEXT: v_addc_u32_e32 v1, vcc, v7, v1, vcc
; GCN-NEXT: v_mul_lo_u32 v2, s2, v1 ; GCN-NEXT: v_mul_lo_u32 v2, s2, v1
; GCN-NEXT: v_mul_hi_u32 v3, s2, v0 ; GCN-NEXT: v_mul_hi_u32 v3, s2, v0
; GCN-NEXT: v_mul_lo_u32 v4, s3, v0 ; GCN-NEXT: v_mul_lo_u32 v4, s3, v0
; GCN-NEXT: v_mov_b32_e32 v5, s3 ; GCN-NEXT: v_mov_b32_e32 v5, s3
▲ Show 20 Lines • Show All 1,063 Lines • ▼ Show 20 Lines
; GCN-NEXT: v_mul_lo_u32 v7, v0, v4 ; GCN-NEXT: v_mul_lo_u32 v7, v0, v4
; GCN-NEXT: v_mul_hi_u32 v9, v0, v4 ; GCN-NEXT: v_mul_hi_u32 v9, v0, v4
; GCN-NEXT: v_mul_lo_u32 v8, v3, v6 ; GCN-NEXT: v_mul_lo_u32 v8, v3, v6
; GCN-NEXT: v_mul_hi_u32 v6, v3, v6 ; GCN-NEXT: v_mul_hi_u32 v6, v3, v6
; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v7 ; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v7
; GCN-NEXT: v_addc_u32_e32 v7, vcc, v2, v9, vcc ; GCN-NEXT: v_addc_u32_e32 v7, vcc, v2, v9, vcc
; GCN-NEXT: v_mul_hi_u32 v9, v3, v4 ; GCN-NEXT: v_mul_hi_u32 v9, v3, v4
; GCN-NEXT: v_mul_lo_u32 v4, v3, v4 ; GCN-NEXT: v_mul_lo_u32 v4, v3, v4
; GCN-NEXT: v_add_i32_e32 v5, vcc, v8, v5 ; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v8
; GCN-NEXT: v_addc_u32_e32 v5, vcc, v7, v6, vcc ; GCN-NEXT: v_addc_u32_e32 v5, vcc, v7, v6, vcc
; GCN-NEXT: v_addc_u32_e32 v6, vcc, v9, v1, vcc ; GCN-NEXT: v_addc_u32_e32 v6, vcc, v9, v1, vcc
; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4 ; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4
; GCN-NEXT: v_add_i32_e64 v0, s[0:1], v0, v4 ; GCN-NEXT: v_add_i32_e64 v0, s[0:1], v0, v4
; GCN-NEXT: v_addc_u32_e32 v5, vcc, v2, v6, vcc ; GCN-NEXT: v_addc_u32_e32 v5, vcc, v2, v6, vcc
; GCN-NEXT: v_addc_u32_e64 v4, vcc, v3, v5, s[0:1] ; GCN-NEXT: v_addc_u32_e64 v4, vcc, v3, v5, s[0:1]
; GCN-NEXT: v_mul_lo_u32 v6, s3, v4 ; GCN-NEXT: v_mul_lo_u32 v6, s3, v4
; GCN-NEXT: v_mul_hi_u32 v7, s3, v0 ; GCN-NEXT: v_mul_hi_u32 v7, s3, v0
▲ Show 20 Lines • Show All 940 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/srem64.ll

Show All 35 Lines
; GCN-NEXT: v_mul_lo_u32 v7, v0, v4 ; GCN-NEXT: v_mul_lo_u32 v7, v0, v4
; GCN-NEXT: v_mul_hi_u32 v9, v0, v4 ; GCN-NEXT: v_mul_hi_u32 v9, v0, v4
; GCN-NEXT: v_mul_lo_u32 v8, v3, v6 ; GCN-NEXT: v_mul_lo_u32 v8, v3, v6
; GCN-NEXT: v_mul_hi_u32 v6, v3, v6 ; GCN-NEXT: v_mul_hi_u32 v6, v3, v6
; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v7 ; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v7
; GCN-NEXT: v_addc_u32_e32 v7, vcc, v2, v9, vcc ; GCN-NEXT: v_addc_u32_e32 v7, vcc, v2, v9, vcc
; GCN-NEXT: v_mul_hi_u32 v9, v3, v4 ; GCN-NEXT: v_mul_hi_u32 v9, v3, v4
; GCN-NEXT: v_mul_lo_u32 v4, v3, v4 ; GCN-NEXT: v_mul_lo_u32 v4, v3, v4
; GCN-NEXT: v_add_i32_e32 v5, vcc, v8, v5 ; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v8
; GCN-NEXT: v_addc_u32_e32 v5, vcc, v7, v6, vcc ; GCN-NEXT: v_addc_u32_e32 v5, vcc, v7, v6, vcc
; GCN-NEXT: v_addc_u32_e32 v6, vcc, v9, v1, vcc ; GCN-NEXT: v_addc_u32_e32 v6, vcc, v9, v1, vcc
; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4 ; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4
; GCN-NEXT: v_add_i32_e64 v0, s[0:1], v0, v4 ; GCN-NEXT: v_add_i32_e64 v0, s[0:1], v0, v4
; GCN-NEXT: v_addc_u32_e32 v5, vcc, v2, v6, vcc ; GCN-NEXT: v_addc_u32_e32 v5, vcc, v2, v6, vcc
; GCN-NEXT: v_addc_u32_e64 v4, vcc, v3, v5, s[0:1] ; GCN-NEXT: v_addc_u32_e64 v4, vcc, v3, v5, s[0:1]
; GCN-NEXT: v_mul_lo_u32 v6, s2, v4 ; GCN-NEXT: v_mul_lo_u32 v6, s2, v4
; GCN-NEXT: v_mul_hi_u32 v7, s2, v0 ; GCN-NEXT: v_mul_hi_u32 v7, s2, v0
Show All 23 Lines
; GCN-NEXT: v_mul_hi_u32 v5, s10, v0 ; GCN-NEXT: v_mul_hi_u32 v5, s10, v0
; GCN-NEXT: v_mul_hi_u32 v6, s10, v3 ; GCN-NEXT: v_mul_hi_u32 v6, s10, v3
; GCN-NEXT: v_mul_hi_u32 v7, s11, v3 ; GCN-NEXT: v_mul_hi_u32 v7, s11, v3
; GCN-NEXT: v_mul_lo_u32 v3, s11, v3 ; GCN-NEXT: v_mul_lo_u32 v3, s11, v3
; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4 ; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4
; GCN-NEXT: v_addc_u32_e32 v5, vcc, v2, v6, vcc ; GCN-NEXT: v_addc_u32_e32 v5, vcc, v2, v6, vcc
; GCN-NEXT: v_mul_lo_u32 v6, s11, v0 ; GCN-NEXT: v_mul_lo_u32 v6, s11, v0
; GCN-NEXT: v_mul_hi_u32 v0, s11, v0 ; GCN-NEXT: v_mul_hi_u32 v0, s11, v0
; GCN-NEXT: v_add_i32_e32 v4, vcc, v6, v4 ; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v6
; GCN-NEXT: v_addc_u32_e32 v0, vcc, v5, v0, vcc ; GCN-NEXT: v_addc_u32_e32 v0, vcc, v5, v0, vcc
; GCN-NEXT: v_addc_u32_e32 v1, vcc, v7, v1, vcc ; GCN-NEXT: v_addc_u32_e32 v1, vcc, v7, v1, vcc
; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v3 ; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v3
; GCN-NEXT: v_addc_u32_e32 v1, vcc, v2, v1, vcc ; GCN-NEXT: v_addc_u32_e32 v1, vcc, v2, v1, vcc
; GCN-NEXT: v_mul_lo_u32 v1, s12, v1 ; GCN-NEXT: v_mul_lo_u32 v1, s12, v1
; GCN-NEXT: v_mul_hi_u32 v2, s12, v0 ; GCN-NEXT: v_mul_hi_u32 v2, s12, v0
; GCN-NEXT: v_mul_lo_u32 v3, s13, v0 ; GCN-NEXT: v_mul_lo_u32 v3, s13, v0
; GCN-NEXT: v_mul_lo_u32 v0, s12, v0 ; GCN-NEXT: v_mul_lo_u32 v0, s12, v0
▲ Show 20 Lines • Show All 829 Lines • ▼ Show 20 Lines
; GCN-NEXT: v_mul_lo_u32 v6, v0, v3 ; GCN-NEXT: v_mul_lo_u32 v6, v0, v3
; GCN-NEXT: v_mul_hi_u32 v8, v0, v3 ; GCN-NEXT: v_mul_hi_u32 v8, v0, v3
; GCN-NEXT: v_mul_hi_u32 v9, v2, v3 ; GCN-NEXT: v_mul_hi_u32 v9, v2, v3
; GCN-NEXT: v_mul_lo_u32 v3, v2, v3 ; GCN-NEXT: v_mul_lo_u32 v3, v2, v3
; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v6 ; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v6
; GCN-NEXT: v_addc_u32_e32 v6, vcc, v7, v8, vcc ; GCN-NEXT: v_addc_u32_e32 v6, vcc, v7, v8, vcc
; GCN-NEXT: v_mul_lo_u32 v8, v2, v5 ; GCN-NEXT: v_mul_lo_u32 v8, v2, v5
; GCN-NEXT: v_mul_hi_u32 v5, v2, v5 ; GCN-NEXT: v_mul_hi_u32 v5, v2, v5
; GCN-NEXT: v_add_i32_e32 v4, vcc, v8, v4 ; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v8
; GCN-NEXT: v_addc_u32_e32 v4, vcc, v6, v5, vcc ; GCN-NEXT: v_addc_u32_e32 v4, vcc, v6, v5, vcc
; GCN-NEXT: v_addc_u32_e32 v5, vcc, v9, v1, vcc ; GCN-NEXT: v_addc_u32_e32 v5, vcc, v9, v1, vcc
; GCN-NEXT: v_add_i32_e32 v3, vcc, v4, v3 ; GCN-NEXT: v_add_i32_e32 v3, vcc, v4, v3
; GCN-NEXT: v_add_i32_e64 v0, s[0:1], v0, v3 ; GCN-NEXT: v_add_i32_e64 v0, s[0:1], v0, v3
; GCN-NEXT: v_addc_u32_e32 v4, vcc, v7, v5, vcc ; GCN-NEXT: v_addc_u32_e32 v4, vcc, v7, v5, vcc
; GCN-NEXT: v_addc_u32_e64 v3, vcc, v2, v4, s[0:1] ; GCN-NEXT: v_addc_u32_e64 v3, vcc, v2, v4, s[0:1]
; GCN-NEXT: v_mul_lo_u32 v5, s4, v3 ; GCN-NEXT: v_mul_lo_u32 v5, s4, v3
; GCN-NEXT: v_mul_hi_u32 v6, s4, v0 ; GCN-NEXT: v_mul_hi_u32 v6, s4, v0
Show All 28 Lines
; GCN-NEXT: v_mul_hi_u32 v5, s14, v2 ; GCN-NEXT: v_mul_hi_u32 v5, s14, v2
; GCN-NEXT: v_mul_hi_u32 v6, s15, v2 ; GCN-NEXT: v_mul_hi_u32 v6, s15, v2
; GCN-NEXT: v_mul_lo_u32 v2, s15, v2 ; GCN-NEXT: v_mul_lo_u32 v2, s15, v2
; GCN-NEXT: v_add_i32_e32 v3, vcc, v4, v3 ; GCN-NEXT: v_add_i32_e32 v3, vcc, v4, v3
; GCN-NEXT: v_addc_u32_e32 v4, vcc, v7, v5, vcc ; GCN-NEXT: v_addc_u32_e32 v4, vcc, v7, v5, vcc
; GCN-NEXT: v_mul_lo_u32 v5, s15, v0 ; GCN-NEXT: v_mul_lo_u32 v5, s15, v0
; GCN-NEXT: v_mul_hi_u32 v0, s15, v0 ; GCN-NEXT: v_mul_hi_u32 v0, s15, v0
; GCN-NEXT: s_mov_b32 s4, s8 ; GCN-NEXT: s_mov_b32 s4, s8
; GCN-NEXT: v_add_i32_e32 v3, vcc, v5, v3 ; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v5
; GCN-NEXT: v_addc_u32_e32 v0, vcc, v4, v0, vcc ; GCN-NEXT: v_addc_u32_e32 v0, vcc, v4, v0, vcc
; GCN-NEXT: v_addc_u32_e32 v1, vcc, v6, v1, vcc ; GCN-NEXT: v_addc_u32_e32 v1, vcc, v6, v1, vcc
; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2 ; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2
; GCN-NEXT: v_addc_u32_e32 v1, vcc, v7, v1, vcc ; GCN-NEXT: v_addc_u32_e32 v1, vcc, v7, v1, vcc
; GCN-NEXT: v_mul_lo_u32 v1, s12, v1 ; GCN-NEXT: v_mul_lo_u32 v1, s12, v1
; GCN-NEXT: v_mul_hi_u32 v2, s12, v0 ; GCN-NEXT: v_mul_hi_u32 v2, s12, v0
; GCN-NEXT: v_mul_lo_u32 v3, s13, v0 ; GCN-NEXT: v_mul_lo_u32 v3, s13, v0
; GCN-NEXT: v_mul_lo_u32 v0, s12, v0 ; GCN-NEXT: v_mul_lo_u32 v0, s12, v0
▲ Show 20 Lines • Show All 370 Lines • ▼ Show 20 Lines
; GCN-NEXT: v_mul_lo_u32 v7, v0, v4 ; GCN-NEXT: v_mul_lo_u32 v7, v0, v4
; GCN-NEXT: v_mul_hi_u32 v9, v0, v4 ; GCN-NEXT: v_mul_hi_u32 v9, v0, v4
; GCN-NEXT: v_mul_lo_u32 v8, v3, v6 ; GCN-NEXT: v_mul_lo_u32 v8, v3, v6
; GCN-NEXT: v_mul_hi_u32 v6, v3, v6 ; GCN-NEXT: v_mul_hi_u32 v6, v3, v6
; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v7 ; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v7
; GCN-NEXT: v_addc_u32_e32 v7, vcc, v2, v9, vcc ; GCN-NEXT: v_addc_u32_e32 v7, vcc, v2, v9, vcc
; GCN-NEXT: v_mul_hi_u32 v9, v3, v4 ; GCN-NEXT: v_mul_hi_u32 v9, v3, v4
; GCN-NEXT: v_mul_lo_u32 v4, v3, v4 ; GCN-NEXT: v_mul_lo_u32 v4, v3, v4
; GCN-NEXT: v_add_i32_e32 v5, vcc, v8, v5 ; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v8
; GCN-NEXT: v_addc_u32_e32 v5, vcc, v7, v6, vcc ; GCN-NEXT: v_addc_u32_e32 v5, vcc, v7, v6, vcc
; GCN-NEXT: v_addc_u32_e32 v6, vcc, v9, v1, vcc ; GCN-NEXT: v_addc_u32_e32 v6, vcc, v9, v1, vcc
; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4 ; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4
; GCN-NEXT: v_add_i32_e64 v0, s[0:1], v0, v4 ; GCN-NEXT: v_add_i32_e64 v0, s[0:1], v0, v4
; GCN-NEXT: v_addc_u32_e32 v5, vcc, v2, v6, vcc ; GCN-NEXT: v_addc_u32_e32 v5, vcc, v2, v6, vcc
; GCN-NEXT: v_addc_u32_e64 v4, vcc, v3, v5, s[0:1] ; GCN-NEXT: v_addc_u32_e64 v4, vcc, v3, v5, s[0:1]
; GCN-NEXT: v_mul_lo_u32 v6, s2, v4 ; GCN-NEXT: v_mul_lo_u32 v6, s2, v4
; GCN-NEXT: v_mul_hi_u32 v7, s2, v0 ; GCN-NEXT: v_mul_hi_u32 v7, s2, v0
▲ Show 20 Lines • Show All 956 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/udiv64.ll

Show All 33 Lines
; GCN-NEXT: v_mul_lo_u32 v7, v0, v4 ; GCN-NEXT: v_mul_lo_u32 v7, v0, v4
; GCN-NEXT: v_mul_hi_u32 v9, v0, v4 ; GCN-NEXT: v_mul_hi_u32 v9, v0, v4
; GCN-NEXT: v_mul_lo_u32 v8, v3, v6 ; GCN-NEXT: v_mul_lo_u32 v8, v3, v6
; GCN-NEXT: v_mul_hi_u32 v6, v3, v6 ; GCN-NEXT: v_mul_hi_u32 v6, v3, v6
; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v7 ; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v7
; GCN-NEXT: v_addc_u32_e32 v7, vcc, v2, v9, vcc ; GCN-NEXT: v_addc_u32_e32 v7, vcc, v2, v9, vcc
; GCN-NEXT: v_mul_hi_u32 v9, v3, v4 ; GCN-NEXT: v_mul_hi_u32 v9, v3, v4
; GCN-NEXT: v_mul_lo_u32 v4, v3, v4 ; GCN-NEXT: v_mul_lo_u32 v4, v3, v4
; GCN-NEXT: v_add_i32_e32 v5, vcc, v8, v5 ; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v8
; GCN-NEXT: v_addc_u32_e32 v5, vcc, v7, v6, vcc ; GCN-NEXT: v_addc_u32_e32 v5, vcc, v7, v6, vcc
; GCN-NEXT: v_addc_u32_e32 v6, vcc, v9, v1, vcc ; GCN-NEXT: v_addc_u32_e32 v6, vcc, v9, v1, vcc
; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4 ; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4
; GCN-NEXT: v_add_i32_e64 v0, s[0:1], v0, v4 ; GCN-NEXT: v_add_i32_e64 v0, s[0:1], v0, v4
; GCN-NEXT: v_addc_u32_e32 v5, vcc, v2, v6, vcc ; GCN-NEXT: v_addc_u32_e32 v5, vcc, v2, v6, vcc
; GCN-NEXT: v_addc_u32_e64 v4, vcc, v3, v5, s[0:1] ; GCN-NEXT: v_addc_u32_e64 v4, vcc, v3, v5, s[0:1]
; GCN-NEXT: v_mul_lo_u32 v6, s4, v4 ; GCN-NEXT: v_mul_lo_u32 v6, s4, v4
; GCN-NEXT: v_mul_hi_u32 v7, s4, v0 ; GCN-NEXT: v_mul_hi_u32 v7, s4, v0
Show All 25 Lines
; GCN-NEXT: v_mul_hi_u32 v6, s10, v3 ; GCN-NEXT: v_mul_hi_u32 v6, s10, v3
; GCN-NEXT: v_mul_hi_u32 v7, s11, v3 ; GCN-NEXT: v_mul_hi_u32 v7, s11, v3
; GCN-NEXT: v_mul_lo_u32 v3, s11, v3 ; GCN-NEXT: v_mul_lo_u32 v3, s11, v3
; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4 ; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4
; GCN-NEXT: v_addc_u32_e32 v5, vcc, v2, v6, vcc ; GCN-NEXT: v_addc_u32_e32 v5, vcc, v2, v6, vcc
; GCN-NEXT: v_mul_lo_u32 v6, s11, v0 ; GCN-NEXT: v_mul_lo_u32 v6, s11, v0
; GCN-NEXT: v_mul_hi_u32 v0, s11, v0 ; GCN-NEXT: v_mul_hi_u32 v0, s11, v0
; GCN-NEXT: s_mov_b32 s4, s8 ; GCN-NEXT: s_mov_b32 s4, s8
; GCN-NEXT: v_add_i32_e32 v4, vcc, v6, v4 ; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v6
; GCN-NEXT: v_addc_u32_e32 v0, vcc, v5, v0, vcc ; GCN-NEXT: v_addc_u32_e32 v0, vcc, v5, v0, vcc
; GCN-NEXT: v_addc_u32_e32 v1, vcc, v7, v1, vcc ; GCN-NEXT: v_addc_u32_e32 v1, vcc, v7, v1, vcc
; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v3 ; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v3
; GCN-NEXT: v_addc_u32_e32 v1, vcc, v2, v1, vcc ; GCN-NEXT: v_addc_u32_e32 v1, vcc, v2, v1, vcc
; GCN-NEXT: v_mul_lo_u32 v2, s2, v1 ; GCN-NEXT: v_mul_lo_u32 v2, s2, v1
; GCN-NEXT: v_mul_hi_u32 v3, s2, v0 ; GCN-NEXT: v_mul_hi_u32 v3, s2, v0
; GCN-NEXT: v_mul_lo_u32 v4, s3, v0 ; GCN-NEXT: v_mul_lo_u32 v4, s3, v0
; GCN-NEXT: v_mov_b32_e32 v5, s3 ; GCN-NEXT: v_mov_b32_e32 v5, s3
▲ Show 20 Lines • Show All 648 Lines • ▼ Show 20 Lines
; GCN-NEXT: v_mul_hi_u32 v5, v1, v3 ; GCN-NEXT: v_mul_hi_u32 v5, v1, v3
; GCN-NEXT: v_mul_hi_u32 v7, v1, v4 ; GCN-NEXT: v_mul_hi_u32 v7, v1, v4
; GCN-NEXT: v_mul_hi_u32 v10, v2, v3 ; GCN-NEXT: v_mul_hi_u32 v10, v2, v3
; GCN-NEXT: v_mul_lo_u32 v3, v2, v3 ; GCN-NEXT: v_mul_lo_u32 v3, v2, v3
; GCN-NEXT: v_add_i32_e32 v6, vcc, v7, v6 ; GCN-NEXT: v_add_i32_e32 v6, vcc, v7, v6
; GCN-NEXT: v_mul_lo_u32 v7, v2, v4 ; GCN-NEXT: v_mul_lo_u32 v7, v2, v4
; GCN-NEXT: v_mul_hi_u32 v4, v2, v4 ; GCN-NEXT: v_mul_hi_u32 v4, v2, v4
; GCN-NEXT: v_addc_u32_e32 v5, vcc, v9, v5, vcc ; GCN-NEXT: v_addc_u32_e32 v5, vcc, v9, v5, vcc
; GCN-NEXT: v_add_i32_e32 v6, vcc, v7, v6 ; GCN-NEXT: v_add_i32_e32 v6, vcc, v6, v7
; GCN-NEXT: v_addc_u32_e32 v4, vcc, v5, v4, vcc ; GCN-NEXT: v_addc_u32_e32 v4, vcc, v5, v4, vcc
; GCN-NEXT: v_addc_u32_e32 v5, vcc, v10, v8, vcc ; GCN-NEXT: v_addc_u32_e32 v5, vcc, v10, v8, vcc
; GCN-NEXT: v_add_i32_e32 v3, vcc, v4, v3 ; GCN-NEXT: v_add_i32_e32 v3, vcc, v4, v3
; GCN-NEXT: v_add_i32_e64 v1, s[2:3], v1, v3 ; GCN-NEXT: v_add_i32_e64 v1, s[2:3], v1, v3
; GCN-NEXT: v_addc_u32_e32 v4, vcc, v9, v5, vcc ; GCN-NEXT: v_addc_u32_e32 v4, vcc, v9, v5, vcc
; GCN-NEXT: v_addc_u32_e64 v3, vcc, v2, v4, s[2:3] ; GCN-NEXT: v_addc_u32_e64 v3, vcc, v2, v4, s[2:3]
; GCN-NEXT: v_mul_lo_u32 v5, s8, v3 ; GCN-NEXT: v_mul_lo_u32 v5, s8, v3
; GCN-NEXT: v_mul_hi_u32 v6, s8, v1 ; GCN-NEXT: v_mul_hi_u32 v6, s8, v1
▲ Show 20 Lines • Show All 212 Lines • ▼ Show 20 Lines
; GCN-NEXT: v_mul_lo_u32 v7, v0, v4 ; GCN-NEXT: v_mul_lo_u32 v7, v0, v4
; GCN-NEXT: v_mul_hi_u32 v9, v0, v4 ; GCN-NEXT: v_mul_hi_u32 v9, v0, v4
; GCN-NEXT: v_mul_hi_u32 v8, v3, v6 ; GCN-NEXT: v_mul_hi_u32 v8, v3, v6
; GCN-NEXT: v_mul_lo_u32 v6, v3, v6 ; GCN-NEXT: v_mul_lo_u32 v6, v3, v6
; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v7 ; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v7
; GCN-NEXT: v_mul_hi_u32 v10, v3, v4 ; GCN-NEXT: v_mul_hi_u32 v10, v3, v4
; GCN-NEXT: v_addc_u32_e32 v7, vcc, v2, v9, vcc ; GCN-NEXT: v_addc_u32_e32 v7, vcc, v2, v9, vcc
; GCN-NEXT: v_mul_lo_u32 v4, v3, v4 ; GCN-NEXT: v_mul_lo_u32 v4, v3, v4
; GCN-NEXT: v_add_i32_e32 v5, vcc, v6, v5 ; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v6
; GCN-NEXT: v_addc_u32_e32 v5, vcc, v7, v8, vcc ; GCN-NEXT: v_addc_u32_e32 v5, vcc, v7, v8, vcc
; GCN-NEXT: v_addc_u32_e32 v6, vcc, v10, v1, vcc ; GCN-NEXT: v_addc_u32_e32 v6, vcc, v10, v1, vcc
; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4 ; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4
; GCN-NEXT: v_add_i32_e64 v0, s[0:1], v0, v4 ; GCN-NEXT: v_add_i32_e64 v0, s[0:1], v0, v4
; GCN-NEXT: v_addc_u32_e32 v5, vcc, v2, v6, vcc ; GCN-NEXT: v_addc_u32_e32 v5, vcc, v2, v6, vcc
; GCN-NEXT: v_addc_u32_e64 v4, vcc, v3, v5, s[0:1] ; GCN-NEXT: v_addc_u32_e64 v4, vcc, v3, v5, s[0:1]
; GCN-NEXT: v_mul_lo_u32 v6, s2, v4 ; GCN-NEXT: v_mul_lo_u32 v6, s2, v4
; GCN-NEXT: v_mul_hi_u32 v7, s2, v0 ; GCN-NEXT: v_mul_hi_u32 v7, s2, v0
▲ Show 20 Lines • Show All 458 Lines • ▼ Show 20 Lines
; GCN-NEXT: v_mul_hi_u32 v9, v1, v2 ; GCN-NEXT: v_mul_hi_u32 v9, v1, v2
; GCN-NEXT: v_mul_lo_u32 v2, v1, v2 ; GCN-NEXT: v_mul_lo_u32 v2, v1, v2
; GCN-NEXT: v_add_i32_e32 v5, vcc, v6, v5 ; GCN-NEXT: v_add_i32_e32 v5, vcc, v6, v5
; GCN-NEXT: v_mul_lo_u32 v6, v1, v4 ; GCN-NEXT: v_mul_lo_u32 v6, v1, v4
; GCN-NEXT: v_mul_hi_u32 v4, v1, v4 ; GCN-NEXT: v_mul_hi_u32 v4, v1, v4
; GCN-NEXT: v_addc_u32_e32 v3, vcc, v8, v3, vcc ; GCN-NEXT: v_addc_u32_e32 v3, vcc, v8, v3, vcc
; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_mov_b32 s4, s8 ; GCN-NEXT: s_mov_b32 s4, s8
; GCN-NEXT: v_add_i32_e32 v5, vcc, v6, v5 ; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v6
; GCN-NEXT: v_addc_u32_e32 v3, vcc, v3, v4, vcc ; GCN-NEXT: v_addc_u32_e32 v3, vcc, v3, v4, vcc
; GCN-NEXT: v_addc_u32_e32 v4, vcc, v9, v7, vcc ; GCN-NEXT: v_addc_u32_e32 v4, vcc, v9, v7, vcc
; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2 ; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2
; GCN-NEXT: v_add_i32_e64 v0, s[0:1], v0, v2 ; GCN-NEXT: v_add_i32_e64 v0, s[0:1], v0, v2
; GCN-NEXT: v_addc_u32_e32 v3, vcc, v8, v4, vcc ; GCN-NEXT: v_addc_u32_e32 v3, vcc, v8, v4, vcc
; GCN-NEXT: v_mul_hi_u32 v4, v0, s2 ; GCN-NEXT: v_mul_hi_u32 v4, v0, s2
; GCN-NEXT: v_addc_u32_e64 v2, vcc, v1, v3, s[0:1] ; GCN-NEXT: v_addc_u32_e64 v2, vcc, v1, v3, s[0:1]
; GCN-NEXT: v_mul_lo_u32 v5, v2, s2 ; GCN-NEXT: v_mul_lo_u32 v5, v2, s2
Show All 23 Lines
; GCN-NEXT: v_mul_hi_u32 v3, s10, v0 ; GCN-NEXT: v_mul_hi_u32 v3, s10, v0
; GCN-NEXT: v_mul_hi_u32 v4, s10, v1 ; GCN-NEXT: v_mul_hi_u32 v4, s10, v1
; GCN-NEXT: v_mul_hi_u32 v5, s11, v1 ; GCN-NEXT: v_mul_hi_u32 v5, s11, v1
; GCN-NEXT: v_mul_lo_u32 v1, s11, v1 ; GCN-NEXT: v_mul_lo_u32 v1, s11, v1
; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2 ; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2
; GCN-NEXT: v_addc_u32_e32 v3, vcc, v8, v4, vcc ; GCN-NEXT: v_addc_u32_e32 v3, vcc, v8, v4, vcc
; GCN-NEXT: v_mul_lo_u32 v4, s11, v0 ; GCN-NEXT: v_mul_lo_u32 v4, s11, v0
; GCN-NEXT: v_mul_hi_u32 v0, s11, v0 ; GCN-NEXT: v_mul_hi_u32 v0, s11, v0
; GCN-NEXT: v_add_i32_e32 v2, vcc, v4, v2 ; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v4
; GCN-NEXT: v_addc_u32_e32 v0, vcc, v3, v0, vcc ; GCN-NEXT: v_addc_u32_e32 v0, vcc, v3, v0, vcc
; GCN-NEXT: v_addc_u32_e32 v2, vcc, v5, v7, vcc ; GCN-NEXT: v_addc_u32_e32 v2, vcc, v5, v7, vcc
; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v1 ; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v1
; GCN-NEXT: v_addc_u32_e32 v1, vcc, v8, v2, vcc ; GCN-NEXT: v_addc_u32_e32 v1, vcc, v8, v2, vcc
; GCN-NEXT: v_mul_lo_u32 v2, v1, 24 ; GCN-NEXT: v_mul_lo_u32 v2, v1, 24
; GCN-NEXT: v_mul_hi_u32 v3, v0, 24 ; GCN-NEXT: v_mul_hi_u32 v3, v0, 24
; GCN-NEXT: v_mul_lo_u32 v4, v0, 24 ; GCN-NEXT: v_mul_lo_u32 v4, v0, 24
; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2 ; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2
▲ Show 20 Lines • Show All 132 Lines • ▼ Show 20 Lines
; GCN-NEXT: v_mul_hi_u32 v8, v2, v6 ; GCN-NEXT: v_mul_hi_u32 v8, v2, v6
; GCN-NEXT: v_mul_hi_u32 v5, v2, v4 ; GCN-NEXT: v_mul_hi_u32 v5, v2, v4
; GCN-NEXT: v_mul_hi_u32 v11, v3, v4 ; GCN-NEXT: v_mul_hi_u32 v11, v3, v4
; GCN-NEXT: v_mul_lo_u32 v4, v3, v4 ; GCN-NEXT: v_mul_lo_u32 v4, v3, v4
; GCN-NEXT: v_add_i32_e32 v7, vcc, v8, v7 ; GCN-NEXT: v_add_i32_e32 v7, vcc, v8, v7
; GCN-NEXT: v_mul_lo_u32 v8, v3, v6 ; GCN-NEXT: v_mul_lo_u32 v8, v3, v6
; GCN-NEXT: v_mul_hi_u32 v6, v3, v6 ; GCN-NEXT: v_mul_hi_u32 v6, v3, v6
; GCN-NEXT: v_addc_u32_e32 v5, vcc, v10, v5, vcc ; GCN-NEXT: v_addc_u32_e32 v5, vcc, v10, v5, vcc
; GCN-NEXT: v_add_i32_e32 v7, vcc, v8, v7 ; GCN-NEXT: v_add_i32_e32 v7, vcc, v7, v8
; GCN-NEXT: v_addc_u32_e32 v5, vcc, v5, v6, vcc ; GCN-NEXT: v_addc_u32_e32 v5, vcc, v5, v6, vcc
; GCN-NEXT: v_addc_u32_e32 v6, vcc, v11, v9, vcc ; GCN-NEXT: v_addc_u32_e32 v6, vcc, v11, v9, vcc
; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4 ; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4
; GCN-NEXT: v_add_i32_e64 v2, s[4:5], v2, v4 ; GCN-NEXT: v_add_i32_e64 v2, s[4:5], v2, v4
; GCN-NEXT: v_addc_u32_e32 v5, vcc, v10, v6, vcc ; GCN-NEXT: v_addc_u32_e32 v5, vcc, v10, v6, vcc
; GCN-NEXT: v_mul_hi_u32 v6, v2, s6 ; GCN-NEXT: v_mul_hi_u32 v6, v2, s6
; GCN-NEXT: v_addc_u32_e64 v4, vcc, v3, v5, s[4:5] ; GCN-NEXT: v_addc_u32_e64 v4, vcc, v3, v5, s[4:5]
; GCN-NEXT: v_mul_lo_u32 v7, v4, s6 ; GCN-NEXT: v_mul_lo_u32 v7, v4, s6
▲ Show 20 Lines • Show All 346 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/urem64.ll

Show All 35 Lines
; GCN-NEXT: v_mul_lo_u32 v7, v0, v4 ; GCN-NEXT: v_mul_lo_u32 v7, v0, v4
; GCN-NEXT: v_mul_hi_u32 v9, v0, v4 ; GCN-NEXT: v_mul_hi_u32 v9, v0, v4
; GCN-NEXT: v_mul_lo_u32 v8, v3, v6 ; GCN-NEXT: v_mul_lo_u32 v8, v3, v6
; GCN-NEXT: v_mul_hi_u32 v6, v3, v6 ; GCN-NEXT: v_mul_hi_u32 v6, v3, v6
; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v7 ; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v7
; GCN-NEXT: v_addc_u32_e32 v7, vcc, v2, v9, vcc ; GCN-NEXT: v_addc_u32_e32 v7, vcc, v2, v9, vcc
; GCN-NEXT: v_mul_hi_u32 v9, v3, v4 ; GCN-NEXT: v_mul_hi_u32 v9, v3, v4
; GCN-NEXT: v_mul_lo_u32 v4, v3, v4 ; GCN-NEXT: v_mul_lo_u32 v4, v3, v4
; GCN-NEXT: v_add_i32_e32 v5, vcc, v8, v5 ; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v8
; GCN-NEXT: v_addc_u32_e32 v5, vcc, v7, v6, vcc ; GCN-NEXT: v_addc_u32_e32 v5, vcc, v7, v6, vcc
; GCN-NEXT: v_addc_u32_e32 v6, vcc, v9, v1, vcc ; GCN-NEXT: v_addc_u32_e32 v6, vcc, v9, v1, vcc
; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4 ; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4
; GCN-NEXT: v_add_i32_e64 v0, s[0:1], v0, v4 ; GCN-NEXT: v_add_i32_e64 v0, s[0:1], v0, v4
; GCN-NEXT: v_addc_u32_e32 v5, vcc, v2, v6, vcc ; GCN-NEXT: v_addc_u32_e32 v5, vcc, v2, v6, vcc
; GCN-NEXT: v_addc_u32_e64 v4, vcc, v3, v5, s[0:1] ; GCN-NEXT: v_addc_u32_e64 v4, vcc, v3, v5, s[0:1]
; GCN-NEXT: v_mul_lo_u32 v6, s2, v4 ; GCN-NEXT: v_mul_lo_u32 v6, s2, v4
; GCN-NEXT: v_mul_hi_u32 v7, s2, v0 ; GCN-NEXT: v_mul_hi_u32 v7, s2, v0
Show All 23 Lines
; GCN-NEXT: v_mul_hi_u32 v5, s10, v0 ; GCN-NEXT: v_mul_hi_u32 v5, s10, v0
; GCN-NEXT: v_mul_hi_u32 v6, s10, v3 ; GCN-NEXT: v_mul_hi_u32 v6, s10, v3
; GCN-NEXT: v_mul_hi_u32 v7, s11, v3 ; GCN-NEXT: v_mul_hi_u32 v7, s11, v3
; GCN-NEXT: v_mul_lo_u32 v3, s11, v3 ; GCN-NEXT: v_mul_lo_u32 v3, s11, v3
; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4 ; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4
; GCN-NEXT: v_addc_u32_e32 v5, vcc, v2, v6, vcc ; GCN-NEXT: v_addc_u32_e32 v5, vcc, v2, v6, vcc
; GCN-NEXT: v_mul_lo_u32 v6, s11, v0 ; GCN-NEXT: v_mul_lo_u32 v6, s11, v0
; GCN-NEXT: v_mul_hi_u32 v0, s11, v0 ; GCN-NEXT: v_mul_hi_u32 v0, s11, v0
; GCN-NEXT: v_add_i32_e32 v4, vcc, v6, v4 ; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v6
; GCN-NEXT: v_addc_u32_e32 v0, vcc, v5, v0, vcc ; GCN-NEXT: v_addc_u32_e32 v0, vcc, v5, v0, vcc
; GCN-NEXT: v_addc_u32_e32 v1, vcc, v7, v1, vcc ; GCN-NEXT: v_addc_u32_e32 v1, vcc, v7, v1, vcc
; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v3 ; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v3
; GCN-NEXT: v_addc_u32_e32 v1, vcc, v2, v1, vcc ; GCN-NEXT: v_addc_u32_e32 v1, vcc, v2, v1, vcc
; GCN-NEXT: v_mul_lo_u32 v1, s12, v1 ; GCN-NEXT: v_mul_lo_u32 v1, s12, v1
; GCN-NEXT: v_mul_hi_u32 v2, s12, v0 ; GCN-NEXT: v_mul_hi_u32 v2, s12, v0
; GCN-NEXT: v_mul_lo_u32 v3, s13, v0 ; GCN-NEXT: v_mul_lo_u32 v3, s13, v0
; GCN-NEXT: v_mul_lo_u32 v0, s12, v0 ; GCN-NEXT: v_mul_lo_u32 v0, s12, v0
▲ Show 20 Lines • Show All 687 Lines • ▼ Show 20 Lines
; GCN-NEXT: v_mul_lo_u32 v7, v0, v4 ; GCN-NEXT: v_mul_lo_u32 v7, v0, v4
; GCN-NEXT: v_mul_hi_u32 v9, v0, v4 ; GCN-NEXT: v_mul_hi_u32 v9, v0, v4
; GCN-NEXT: v_mul_hi_u32 v8, v3, v6 ; GCN-NEXT: v_mul_hi_u32 v8, v3, v6
; GCN-NEXT: v_mul_lo_u32 v6, v3, v6 ; GCN-NEXT: v_mul_lo_u32 v6, v3, v6
; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v7 ; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v7
; GCN-NEXT: v_mul_hi_u32 v10, v3, v4 ; GCN-NEXT: v_mul_hi_u32 v10, v3, v4
; GCN-NEXT: v_addc_u32_e32 v7, vcc, v2, v9, vcc ; GCN-NEXT: v_addc_u32_e32 v7, vcc, v2, v9, vcc
; GCN-NEXT: v_mul_lo_u32 v4, v3, v4 ; GCN-NEXT: v_mul_lo_u32 v4, v3, v4
; GCN-NEXT: v_add_i32_e32 v5, vcc, v6, v5 ; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v6
; GCN-NEXT: v_addc_u32_e32 v5, vcc, v7, v8, vcc ; GCN-NEXT: v_addc_u32_e32 v5, vcc, v7, v8, vcc
; GCN-NEXT: v_addc_u32_e32 v6, vcc, v10, v1, vcc ; GCN-NEXT: v_addc_u32_e32 v6, vcc, v10, v1, vcc
; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4 ; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4
; GCN-NEXT: v_add_i32_e64 v0, s[0:1], v0, v4 ; GCN-NEXT: v_add_i32_e64 v0, s[0:1], v0, v4
; GCN-NEXT: v_addc_u32_e32 v5, vcc, v2, v6, vcc ; GCN-NEXT: v_addc_u32_e32 v5, vcc, v2, v6, vcc
; GCN-NEXT: v_addc_u32_e64 v4, vcc, v3, v5, s[0:1] ; GCN-NEXT: v_addc_u32_e64 v4, vcc, v3, v5, s[0:1]
; GCN-NEXT: v_mul_lo_u32 v6, s2, v4 ; GCN-NEXT: v_mul_lo_u32 v6, s2, v4
; GCN-NEXT: v_mul_hi_u32 v7, s2, v0 ; GCN-NEXT: v_mul_hi_u32 v7, s2, v0
▲ Show 20 Lines • Show All 184 Lines • ▼ Show 20 Lines
; GCN-NEXT: v_mul_hi_u32 v9, v1, v2 ; GCN-NEXT: v_mul_hi_u32 v9, v1, v2
; GCN-NEXT: v_mul_lo_u32 v2, v1, v2 ; GCN-NEXT: v_mul_lo_u32 v2, v1, v2
; GCN-NEXT: v_add_i32_e32 v5, vcc, v6, v5 ; GCN-NEXT: v_add_i32_e32 v5, vcc, v6, v5
; GCN-NEXT: v_mul_lo_u32 v6, v1, v4 ; GCN-NEXT: v_mul_lo_u32 v6, v1, v4
; GCN-NEXT: v_mul_hi_u32 v4, v1, v4 ; GCN-NEXT: v_mul_hi_u32 v4, v1, v4
; GCN-NEXT: v_addc_u32_e32 v3, vcc, v8, v3, vcc ; GCN-NEXT: v_addc_u32_e32 v3, vcc, v8, v3, vcc
; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_mov_b32 s8, s4 ; GCN-NEXT: s_mov_b32 s8, s4
; GCN-NEXT: v_add_i32_e32 v5, vcc, v6, v5 ; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v6
; GCN-NEXT: v_addc_u32_e32 v3, vcc, v3, v4, vcc ; GCN-NEXT: v_addc_u32_e32 v3, vcc, v3, v4, vcc
; GCN-NEXT: v_addc_u32_e32 v4, vcc, v9, v7, vcc ; GCN-NEXT: v_addc_u32_e32 v4, vcc, v9, v7, vcc
; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2 ; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2
; GCN-NEXT: v_add_i32_e64 v0, s[0:1], v0, v2 ; GCN-NEXT: v_add_i32_e64 v0, s[0:1], v0, v2
; GCN-NEXT: v_addc_u32_e32 v3, vcc, v8, v4, vcc ; GCN-NEXT: v_addc_u32_e32 v3, vcc, v8, v4, vcc
; GCN-NEXT: v_mul_hi_u32 v4, v0, s2 ; GCN-NEXT: v_mul_hi_u32 v4, v0, s2
; GCN-NEXT: v_addc_u32_e64 v2, vcc, v1, v3, s[0:1] ; GCN-NEXT: v_addc_u32_e64 v2, vcc, v1, v3, s[0:1]
; GCN-NEXT: v_mul_lo_u32 v5, v2, s2 ; GCN-NEXT: v_mul_lo_u32 v5, v2, s2
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; GCN-NEXT: v_mul_hi_u32 v3, s6, v0 ; GCN-NEXT: v_mul_hi_u32 v3, s6, v0
; GCN-NEXT: v_mul_hi_u32 v4, s6, v1 ; GCN-NEXT: v_mul_hi_u32 v4, s6, v1
; GCN-NEXT: v_mul_hi_u32 v5, s7, v1 ; GCN-NEXT: v_mul_hi_u32 v5, s7, v1
; GCN-NEXT: v_mul_lo_u32 v1, s7, v1 ; GCN-NEXT: v_mul_lo_u32 v1, s7, v1
; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2 ; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2
; GCN-NEXT: v_addc_u32_e32 v3, vcc, v8, v4, vcc ; GCN-NEXT: v_addc_u32_e32 v3, vcc, v8, v4, vcc
; GCN-NEXT: v_mul_lo_u32 v4, s7, v0 ; GCN-NEXT: v_mul_lo_u32 v4, s7, v0
; GCN-NEXT: v_mul_hi_u32 v0, s7, v0 ; GCN-NEXT: v_mul_hi_u32 v0, s7, v0
; GCN-NEXT: v_add_i32_e32 v2, vcc, v4, v2 ; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v4
; GCN-NEXT: v_addc_u32_e32 v0, vcc, v3, v0, vcc ; GCN-NEXT: v_addc_u32_e32 v0, vcc, v3, v0, vcc
; GCN-NEXT: v_addc_u32_e32 v2, vcc, v5, v7, vcc ; GCN-NEXT: v_addc_u32_e32 v2, vcc, v5, v7, vcc
; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v1 ; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v1
; GCN-NEXT: v_addc_u32_e32 v1, vcc, v8, v2, vcc ; GCN-NEXT: v_addc_u32_e32 v1, vcc, v8, v2, vcc
; GCN-NEXT: v_mul_hi_u32 v2, v0, 24 ; GCN-NEXT: v_mul_hi_u32 v2, v0, 24
; GCN-NEXT: v_mul_lo_u32 v1, v1, 24 ; GCN-NEXT: v_mul_lo_u32 v1, v1, 24
; GCN-NEXT: v_mul_lo_u32 v0, v0, 24 ; GCN-NEXT: v_mul_lo_u32 v0, v0, 24
; GCN-NEXT: v_add_i32_e32 v1, vcc, v2, v1 ; GCN-NEXT: v_add_i32_e32 v1, vcc, v2, v1
▲ Show 20 Lines • Show All 631 Lines • Show Last 20 Lines