[ARM] Precommit test for D101898

[tmatheson]

Minimize the CHECK lines in the test

[tmatheson]

Add tests for v8m.baseline

llvm/test/CodeGen/ARM/atomicrmw_exclusive_monitor_ints.ll

+; Test the instruction sequences produced by atomicrmw instructions. In
+; particular, ensure there are no stores/spills inserted between the exclusive
+; load and stores, which would invalidate the exclusive monitor.
+
+; RUN: llc -mtriple=armv8-none-linux-gnu -O0 -o - %s | FileCheck %s --check-prefix=CHECK --check-prefix=ARM
+; RUN: llc -mtriple=armv6-none-linux-gnu -O0 -o - %s | FileCheck %s --check-prefix=CHECK --check-prefix=ARM
+; RUN: llc -mtriple=thumbv7-none-linux-gnu -O0 -o - %s | FileCheck %s --check-prefix=CHECK --check-prefix=ARM
+; RUN: llc -mtriple=thumbv6-none-linux-gnu -O0 -o - %s | FileCheck %s --check-prefix=CHECK --check-prefix=THUMB1
+
+@atomic_i8 = external global i8
+@atomic_i16 = external global i16
+@atomic_i32 = external global i32
+@atomic_i64 = external global i64
+
+define i8 @test_xchg_i8() {
+; CHECK-LABEL: test_xchg_i8:
+; ARM: ldrexb
+; ARM: str
+; ARM: strexb
+; THUMB1: bl __sync_lock_test_and_set_1
+entry:
+  %0 = atomicrmw xchg i8* @atomic_i8, i8 1 monotonic
+  ret i8 %0
+}
+define i8 @test_add_i8() {
+; CHECK-LABEL: test_add_i8:
+; ARM: ldrexb
+; ARM: str
+; ARM: strexb
+; THUMB1: bl __sync_fetch_and_add_1
+entry:
+  %0 = atomicrmw add i8* @atomic_i8, i8 1 monotonic
+  ret i8 %0
+}
+define i8 @test_sub_i8() {
+; CHECK-LABEL: test_sub_i8:
+; ARM: ldrexb
+; ARM: str
+; ARM: strexb
+; THUMB1: bl __sync_fetch_and_sub_1
+entry:
+  %0 = atomicrmw sub i8* @atomic_i8, i8 1 monotonic
+  ret i8 %0
+}
+define i8 @test_and_i8() {
+; CHECK-LABEL: test_and_i8:
+; ARM: ldrexb
+; ARM: str
+; ARM: strexb
+; THUMB1: bl __sync_fetch_and_and_1
+entry:
+  %0 = atomicrmw and i8* @atomic_i8, i8 1 monotonic
+  ret i8 %0
+}
+define i8 @test_nand_i8() {
+; CHECK-LABEL: test_nand_i8:
+; ARM: ldrexb
+; ARM: str
+; ARM: strexb
+; THUMB1: bl __sync_fetch_and_nand_1
+entry:
+  %0 = atomicrmw nand i8* @atomic_i8, i8 1 monotonic
+  ret i8 %0
+}
+define i8 @test_or_i8() {
+; CHECK-LABEL: test_or_i8:
+; ARM: ldrexb
+; ARM: str
+; ARM: strexb
+; THUMB1: bl __sync_fetch_and_or_1
+entry:
+  %0 = atomicrmw or i8* @atomic_i8, i8 1 monotonic
+  ret i8 %0
+}
+define i8 @test_xor_i8() {
+; CHECK-LABEL: test_xor_i8:
+; ARM: ldrexb
+; ARM: str
+; ARM: strexb
+; THUMB1: bl __sync_fetch_and_xor_1
+entry:
+  %0 = atomicrmw xor i8* @atomic_i8, i8 1 monotonic
+  ret i8 %0
+}
+define i8 @test_max_i8() {
+; CHECK-LABEL: test_max_i8:
+; ARM: ldrexb
+; ARM: str
+; ARM: strexb
+; THUMB1: bl __sync_fetch_and_max_1
+entry:
+  %0 = atomicrmw max i8* @atomic_i8, i8 1 monotonic
+  ret i8 %0
+}
+define i8 @test_min_i8() {
+; CHECK-LABEL: test_min_i8:
+; ARM: ldrexb
+; ARM: str
+; ARM: strexb
+; THUMB1: bl __sync_fetch_and_min_1
+entry:
+  %0 = atomicrmw min i8* @atomic_i8, i8 1 monotonic
+  ret i8 %0
+}
+define i8 @test_umax_i8() {
+; CHECK-LABEL: test_umax_i8:
+; ARM: ldrexb
+; ARM: str
+; ARM: strexb
+; THUMB1: bl __sync_fetch_and_umax_1
+entry:
+  %0 = atomicrmw umax i8* @atomic_i8, i8 1 monotonic
+  ret i8 %0
+}
+define i8 @test_umin_i8() {
+; CHECK-LABEL: test_umin_i8:
+; ARM: ldrexb
+; ARM: str
+; ARM: strexb
+; THUMB1: bl __sync_fetch_and_umin_1
+entry:
+  %0 = atomicrmw umin i8* @atomic_i8, i8 1 monotonic
+  ret i8 %0
+}
+
+
+define i16 @test_xchg_i16() {
+; CHECK-LABEL: test_xchg_i16:
+; ARM: ldrexh
+; ARM: str
+; ARM: strexh
+; THUMB1: bl __sync_lock_test_and_set_2
+entry:
+  %0 = atomicrmw xchg i16* @atomic_i16, i16 1 monotonic
+  ret i16 %0
+}
+define i16 @test_add_i16() {
+; CHECK-LABEL: test_add_i16:
+; ARM: ldrexh
+; ARM: str
+; ARM: strexh
+; THUMB1: bl __sync_fetch_and_add_2
+entry:
+  %0 = atomicrmw add i16* @atomic_i16, i16 1 monotonic
+  ret i16 %0
+}
+define i16 @test_sub_i16() {
+; CHECK-LABEL: test_sub_i16:
+; ARM: ldrexh
+; ARM: str
+; ARM: strexh
+; THUMB1: bl __sync_fetch_and_sub_2
+entry:
+  %0 = atomicrmw sub i16* @atomic_i16, i16 1 monotonic
+  ret i16 %0
+}
+define i16 @test_and_i16() {
+; CHECK-LABEL: test_and_i16:
+; ARM: ldrexh
+; ARM: str
+; ARM: strexh
+; THUMB1: bl __sync_fetch_and_and_2
+entry:
+  %0 = atomicrmw and i16* @atomic_i16, i16 1 monotonic
+  ret i16 %0
+}
+define i16 @test_nand_i16() {
+; CHECK-LABEL: test_nand_i16:
+; ARM: ldrexh
+; ARM: str
+; ARM: strexh
+; THUMB1: bl __sync_fetch_and_nand_2
+entry:
+  %0 = atomicrmw nand i16* @atomic_i16, i16 1 monotonic
+  ret i16 %0
+}
+define i16 @test_or_i16() {
+; CHECK-LABEL: test_or_i16:
+; ARM: ldrexh
+; ARM: str
+; ARM: strexh
+; THUMB1: bl __sync_fetch_and_or_2
+entry:
+  %0 = atomicrmw or i16* @atomic_i16, i16 1 monotonic
+  ret i16 %0
+}
+define i16 @test_xor_i16() {
+; CHECK-LABEL: test_xor_i16:
+; ARM: ldrexh
+; ARM: str
+; ARM: strexh
+; THUMB1: bl __sync_fetch_and_xor_2
+entry:
+  %0 = atomicrmw xor i16* @atomic_i16, i16 1 monotonic
+  ret i16 %0
+}
+define i16 @test_max_i16() {
+; CHECK-LABEL: test_max_i16:
+; ARM: ldrexh
+; ARM: str
+; ARM: strexh
+; THUMB1: bl __sync_fetch_and_max_2
+entry:
+  %0 = atomicrmw max i16* @atomic_i16, i16 1 monotonic
+  ret i16 %0
+}
+define i16 @test_min_i16() {
+; CHECK-LABEL: test_min_i16:
+; ARM: ldrexh
+; ARM: str
+; ARM: strexh
+; THUMB1: bl __sync_fetch_and_min_2
+entry:
+  %0 = atomicrmw min i16* @atomic_i16, i16 1 monotonic
+  ret i16 %0
+}
+define i16 @test_umax_i16() {
+; CHECK-LABEL: test_umax_i16:
+; ARM: ldrexh
+; ARM: str
+; ARM: strexh
+; THUMB1: bl __sync_fetch_and_umax_2
+entry:
+  %0 = atomicrmw umax i16* @atomic_i16, i16 1 monotonic
+  ret i16 %0
+}
+define i16 @test_umin_i16() {
+; CHECK-LABEL: test_umin_i16:
+; ARM: ldrexh
+; ARM: str
+; ARM: strexh
+; THUMB1: bl __sync_fetch_and_umin_2
+entry:
+  %0 = atomicrmw umin i16* @atomic_i16, i16 1 monotonic
+  ret i16 %0
+}
+
+
+define i32 @test_xchg_i32() {
+; CHECK-LABEL: test_xchg_i32:
+; ARM: ldrex
+; ARM: str
+; ARM: strex
+; THUMB1: bl __sync_lock_test_and_set_4
+entry:
+  %0 = atomicrmw xchg i32* @atomic_i32, i32 1 monotonic
+  ret i32 %0
+}
+define i32 @test_add_i32() {
+; CHECK-LABEL: test_add_i32:
+; ARM: ldrex
+; ARM: str
+; ARM: strex
+; THUMB1: bl __sync_fetch_and_add_4
+entry:
+  %0 = atomicrmw add i32* @atomic_i32, i32 1 monotonic
+  ret i32 %0
+}
+define i32 @test_sub_i32() {
+; CHECK-LABEL: test_sub_i32:
+; ARM: ldrex
+; ARM: str
+; ARM: strex
+; THUMB1: bl __sync_fetch_and_sub_4
+entry:
+  %0 = atomicrmw sub i32* @atomic_i32, i32 1 monotonic
+  ret i32 %0
+}
+define i32 @test_and_i32() {
+; CHECK-LABEL: test_and_i32:
+; ARM: ldrex
+; ARM: str
+; ARM: strex
+; THUMB1: bl __sync_fetch_and_and_4
+entry:
+  %0 = atomicrmw and i32* @atomic_i32, i32 1 monotonic
+  ret i32 %0
+}
+define i32 @test_nand_i32() {
+; CHECK-LABEL: test_nand_i32:
+; ARM: ldrex
+; ARM: str
+; ARM: strex
+; THUMB1: bl __sync_fetch_and_nand_4
+entry:
+  %0 = atomicrmw nand i32* @atomic_i32, i32 1 monotonic
+  ret i32 %0
+}
+define i32 @test_or_i32() {
+; CHECK-LABEL: test_or_i32:
+; ARM: ldrex
+; ARM: str
+; ARM: strex
+; THUMB1: bl __sync_fetch_and_or_4
+entry:
+  %0 = atomicrmw or i32* @atomic_i32, i32 1 monotonic
+  ret i32 %0
+}
+define i32 @test_xor_i32() {
+; CHECK-LABEL: test_xor_i32:
+; ARM: ldrex
+; ARM: str
+; ARM: strex
+; THUMB1: bl __sync_fetch_and_xor_4
+entry:
+  %0 = atomicrmw xor i32* @atomic_i32, i32 1 monotonic
+  ret i32 %0
+}
+define i32 @test_max_i32() {
+; CHECK-LABEL: test_max_i32:
+; ARM: ldrex
+; ARM: str
+; ARM: strex
+; THUMB1: bl __sync_fetch_and_max_4
+entry:
+  %0 = atomicrmw max i32* @atomic_i32, i32 1 monotonic
+  ret i32 %0
+}
+define i32 @test_min_i32() {
+; CHECK-LABEL: test_min_i32:
+; ARM: ldrex
+; ARM: str
+; ARM: strex
+
+; THUMB1: bl __sync_fetch_and_min_4
+entry:
+  %0 = atomicrmw min i32* @atomic_i32, i32 1 monotonic
+  ret i32 %0
+}
+define i32 @test_umax_i32() {
+; CHECK-LABEL: test_umax_i32:
+; ARM: ldrex
+; ARM: str
+; ARM: strex
+; THUMB1: bl __sync_fetch_and_umax_4
+entry:
+  %0 = atomicrmw umax i32* @atomic_i32, i32 1 monotonic
+  ret i32 %0
+}
+define i32 @test_umin_i32() {
+; CHECK-LABEL: test_umin_i32:
+; ARM: ldrex
+; ARM: str
+; ARM: strex
+; THUMB1: bl __sync_fetch_and_umin_4
+entry:
+  %0 = atomicrmw umin i32* @atomic_i32, i32 1 monotonic
+  ret i32 %0
+}
+
+define i64 @test_xchg_i64() {
+; CHECK-LABEL: test_xchg_i64:
+; ARM: ldrexd
+; ARM: str
+; ARM: strexd
+; THUMB1: bl __sync_lock_test_and_set_8
+entry:
+  %0 = atomicrmw xchg i64* @atomic_i64, i64 1 monotonic
+  ret i64 %0
+}
+define i64 @test_add_i64() {
+; CHECK-LABEL: test_add_i64:
+; ARM: ldrexd
+; ARM: str
+; ARM: strexd
+; THUMB1: bl __sync_fetch_and_add_8
+entry:
+  %0 = atomicrmw add i64* @atomic_i64, i64 1 monotonic
+  ret i64 %0
+}
+define i64 @test_sub_i64() {
+; CHECK-LABEL: test_sub_i64:
+; ARM: ldrexd
+; ARM: str
+; ARM: strexd
+; THUMB1: bl __sync_fetch_and_sub_8
+entry:
+  %0 = atomicrmw sub i64* @atomic_i64, i64 1 monotonic
+  ret i64 %0
+}
+define i64 @test_and_i64() {
+; CHECK-LABEL: test_and_i64:
+; ARM: ldrexd
+; ARM: str
+; ARM: strexd
+; THUMB1: bl __sync_fetch_and_and_8
+entry:
+  %0 = atomicrmw and i64* @atomic_i64, i64 1 monotonic
+  ret i64 %0
+}
+define i64 @test_nand_i64() {
+; CHECK-LABEL: test_nand_i64:
+; ARM: ldrexd
+; ARM: str
+; ARM: strexd
+; THUMB1: bl __sync_fetch_and_nand_8
+entry:
+  %0 = atomicrmw nand i64* @atomic_i64, i64 1 monotonic
+  ret i64 %0
+}
+define i64 @test_or_i64() {
+; CHECK-LABEL: test_or_i64:
+; ARM: ldrexd
+; ARM: str
+; ARM: strexd
+; THUMB1: bl __sync_fetch_and_or_8
+entry:
+  %0 = atomicrmw or i64* @atomic_i64, i64 1 monotonic
+  ret i64 %0
+}
+define i64 @test_xor_i64() {
+; CHECK-LABEL: test_xor_i64:
+; ARM: ldrexd
+; ARM: str
+; ARM: strexd
+; THUMB1: bl __sync_fetch_and_xor_8
+entry:
+  %0 = atomicrmw xor i64* @atomic_i64, i64 1 monotonic
+  ret i64 %0
+}
+
+define i64 @test_max_i64() {
+; CHECK-LABEL: test_max_i64:
+; ARM: ldrexd
+; ARM: str
+; ARM: strexd
+; THUMB1: bl __sync_fetch_and_max_8
+entry:
+  %0 = atomicrmw max i64* @atomic_i64, i64 1 monotonic
+  ret i64 %0
+}
+define i64 @test_min_i64() {
+; CHECK-LABEL: test_min_i64:
+; ARM: ldrexd
+; ARM: str
+; ARM: strexd
+; THUMB1: bl __sync_fetch_and_min_8
+entry:
+  %0 = atomicrmw min i64* @atomic_i64, i64 1 monotonic
+  ret i64 %0
+}
+define i64 @test_umax_i64() {
+; CHECK-LABEL: test_umax_i64:
+; ARM: ldrexd
+; ARM: str
+; ARM: strexd
+; THUMB1: bl __sync_fetch_and_umax_8
+entry:
+  %0 = atomicrmw umax i64* @atomic_i64, i64 1 monotonic
+  ret i64 %0
+}
+define i64 @test_umin_i64() {
+; CHECK-LABEL: test_umin_i64:
+; ARM: ldrexd
+; ARM: str
+; ARM: strexd
+; THUMB1: bl __sync_fetch_and_umin_8
+entry:
+  %0 = atomicrmw umin i64* @atomic_i64, i64 1 monotonic
+  ret i64 %0
+}