[AArch64][GlobalISel] Use a single MachineIRBuilder for most of isel. NFC.

[aemerson]

Summary

This is a long overdue cleanup. Not every use is eliminated, I stuck to uses that were directly being called from select(), and not the render functions.

[paquette]

Nice cleanup, LGTM.

llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp

public:
 
   bool select(MachineInstr &I) override;
   static const char *getName() { return DEBUG_TYPE; }
 
   void setupMF(MachineFunction &MF, GISelKnownBits *KB,
                CodeGenCoverage &CoverageInfo, ProfileSummaryInfo *PSI,
                BlockFrequencyInfo *BFI) override {
     InstructionSelector::setupMF(MF, KB, CoverageInfo, PSI, BFI);
+    MIB.setMF(MF);
 
     // hasFnAttribute() is expensive to call on every BRCOND selection, so
     // cache it here for each run of the selector.
     ProduceNonFlagSettingCondBr =
         !MF.getFunction().hasFnAttribute(Attribute::SpeculativeLoadHardening);
     MFReturnAddr = Register();
 
     processPHIs(MF);
   }
 
 private:
   /// tblgen-erated 'select' implementation, used as the initial selector for
   /// the patterns that don't require complex C++.
   bool selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const;
 
   // A lowering phase that runs before any selection attempts.
   // Returns true if the instruction was modified.
   bool preISelLower(MachineInstr &I);
 
   // An early selection function that runs before the selectImpl() call.
-  bool earlySelect(MachineInstr &I) const;
+  bool earlySelect(MachineInstr &I);
 
   // Do some preprocessing of G_PHIs before we begin selection.
   void processPHIs(MachineFunction &MF);
 
-  bool earlySelectSHL(MachineInstr &I, MachineRegisterInfo &MRI) const;
+  bool earlySelectSHL(MachineInstr &I, MachineRegisterInfo &MRI);
 
   /// Eliminate same-sized cross-bank copies into stores before selectImpl().
   bool contractCrossBankCopyIntoStore(MachineInstr &I,
                                       MachineRegisterInfo &MRI);
 
   bool convertPtrAddToAdd(MachineInstr &I, MachineRegisterInfo &MRI);
 
   bool selectVaStartAAPCS(MachineInstr &I, MachineFunction &MF,
private:
   bool tryOptCompareBranchFedByICmp(MachineInstr &I, MachineInstr &ICmp,
                                     MachineIRBuilder &MIB) const;
   bool tryOptAndIntoCompareBranch(MachineInstr &AndInst, bool Invert,
                                   MachineBasicBlock *DstMBB,
                                   MachineIRBuilder &MIB) const;
   ///@}
 
   bool selectCompareBranch(MachineInstr &I, MachineFunction &MF,
-                           MachineRegisterInfo &MRI) const;
+                           MachineRegisterInfo &MRI);
 
-  bool selectVectorAshrLshr(MachineInstr &I, MachineRegisterInfo &MRI) const;
-  bool selectVectorSHL(MachineInstr &I, MachineRegisterInfo &MRI) const;
+  bool selectVectorAshrLshr(MachineInstr &I, MachineRegisterInfo &MRI);
+  bool selectVectorSHL(MachineInstr &I, MachineRegisterInfo &MRI);
 
   // Helper to generate an equivalent of scalar_to_vector into a new register,
   // returned via 'Dst'.
   MachineInstr *emitScalarToVector(unsigned EltSize,
                                    const TargetRegisterClass *DstRC,
                                    Register Scalar,
                                    MachineIRBuilder &MIRBuilder) const;
 
private:
 
   /// Emit a sequence of instructions representing a constant \p CV for a
   /// vector register \p Dst. (E.g. a MOV, or a load from a constant pool.)
   ///
   /// \returns the last instruction in the sequence on success, and nullptr
   /// otherwise.
   MachineInstr *emitConstantVector(Register Dst, Constant *CV,
                                    MachineIRBuilder &MIRBuilder,
-                                   MachineRegisterInfo &MRI) const;
+                                   MachineRegisterInfo &MRI);
 
-  bool selectInsertElt(MachineInstr &I, MachineRegisterInfo &MRI) const;
+  bool selectInsertElt(MachineInstr &I, MachineRegisterInfo &MRI);
   bool tryOptConstantBuildVec(MachineInstr &MI, LLT DstTy,
-                              MachineRegisterInfo &MRI) const;
-  bool selectBuildVector(MachineInstr &I, MachineRegisterInfo &MRI) const;
-  bool selectMergeValues(MachineInstr &I, MachineRegisterInfo &MRI) const;
-  bool selectUnmergeValues(MachineInstr &I, MachineRegisterInfo &MRI) const;
-
-  bool selectShuffleVector(MachineInstr &I, MachineRegisterInfo &MRI) const;
-  bool selectExtractElt(MachineInstr &I, MachineRegisterInfo &MRI) const;
-  bool selectConcatVectors(MachineInstr &I, MachineRegisterInfo &MRI) const;
-  bool selectSplitVectorUnmerge(MachineInstr &I,
-                                MachineRegisterInfo &MRI) const;
+                              MachineRegisterInfo &MRI);
+  bool selectBuildVector(MachineInstr &I, MachineRegisterInfo &MRI);
+  bool selectMergeValues(MachineInstr &I, MachineRegisterInfo &MRI);
+  bool selectUnmergeValues(MachineInstr &I, MachineRegisterInfo &MRI);
+
+  bool selectShuffleVector(MachineInstr &I, MachineRegisterInfo &MRI);
+  bool selectExtractElt(MachineInstr &I, MachineRegisterInfo &MRI);
+  bool selectConcatVectors(MachineInstr &I, MachineRegisterInfo &MRI);
+  bool selectSplitVectorUnmerge(MachineInstr &I, MachineRegisterInfo &MRI);
   bool selectIntrinsicWithSideEffects(MachineInstr &I,
-                                      MachineRegisterInfo &MRI) const;
+                                      MachineRegisterInfo &MRI);
   bool selectIntrinsic(MachineInstr &I, MachineRegisterInfo &MRI);
-  bool selectVectorICmp(MachineInstr &I, MachineRegisterInfo &MRI) const;
+  bool selectVectorICmp(MachineInstr &I, MachineRegisterInfo &MRI);
   bool selectIntrinsicTrunc(MachineInstr &I, MachineRegisterInfo &MRI) const;
   bool selectIntrinsicRound(MachineInstr &I, MachineRegisterInfo &MRI) const;
-  bool selectJumpTable(MachineInstr &I, MachineRegisterInfo &MRI) const;
-  bool selectBrJT(MachineInstr &I, MachineRegisterInfo &MRI) const;
-  bool selectTLSGlobalValue(MachineInstr &I, MachineRegisterInfo &MRI) const;
-  bool selectReduction(MachineInstr &I, MachineRegisterInfo &MRI) const;
+  bool selectJumpTable(MachineInstr &I, MachineRegisterInfo &MRI);
+  bool selectBrJT(MachineInstr &I, MachineRegisterInfo &MRI);
+  bool selectTLSGlobalValue(MachineInstr &I, MachineRegisterInfo &MRI);
+  bool selectReduction(MachineInstr &I, MachineRegisterInfo &MRI);
 
   unsigned emitConstantPoolEntry(const Constant *CPVal,
                                  MachineFunction &MF) const;
   MachineInstr *emitLoadFromConstantPool(const Constant *CPVal,
                                          MachineIRBuilder &MIRBuilder) const;
 
   // Emit a vector concat operation.
   MachineInstr *emitVectorConcat(Optional<Register> Dst, Register Op1,
private:
   void renderFPImm16(MachineInstrBuilder &MIB, const MachineInstr &MI,
                      int OpIdx = -1) const;
   void renderFPImm32(MachineInstrBuilder &MIB, const MachineInstr &MI,
                      int OpIdx = -1) const;
   void renderFPImm64(MachineInstrBuilder &MIB, const MachineInstr &MI,
                      int OpIdx = -1) const;
 
   // Materialize a GlobalValue or BlockAddress using a movz+movk sequence.
-  void materializeLargeCMVal(MachineInstr &I, const Value *V,
-                             unsigned OpFlags) const;
+  void materializeLargeCMVal(MachineInstr &I, const Value *V, unsigned OpFlags);
 
   // Optimization methods.
-  bool tryOptSelect(MachineInstr &MI) const;
+  bool tryOptSelect(MachineInstr &MI);
   MachineInstr *tryFoldIntegerCompare(MachineOperand &LHS, MachineOperand &RHS,
                                       MachineOperand &Predicate,
                                       MachineIRBuilder &MIRBuilder) const;
 
   /// Return true if \p MI is a load or store of \p NumBytes bytes.
   bool isLoadStoreOfNumBytes(const MachineInstr &MI, unsigned NumBytes) const;
 
   /// Returns true if \p MI is guaranteed to have the high-half of a 64-bit
private:
 
   bool ProduceNonFlagSettingCondBr = false;
 
   // Some cached values used during selection.
   // We use LR as a live-in register, and we keep track of it here as it can be
   // clobbered by calls.
   Register MFReturnAddr;
 
+  MachineIRBuilder MIB;
+
 #define GET_GLOBALISEL_PREDICATES_DECL
 #include "AArch64GenGlobalISel.inc"
 #undef GET_GLOBALISEL_PREDICATES_DECL
 
 // We declare the temporaries used by selectImpl() in the class to minimize the
 // cost of constructing placeholder values.
 #define GET_GLOBALISEL_TEMPORARIES_DECL
 #include "AArch64GenGlobalISel.inc"
bool AArch64InstructionSelector::selectCompareBranchFedByICmp(
   emitIntegerCompare(ICmp.getOperand(2), ICmp.getOperand(3), PredOp, MIB);
   const AArch64CC::CondCode CC = changeICMPPredToAArch64CC(
       static_cast<CmpInst::Predicate>(PredOp.getPredicate()));
   MIB.buildInstr(AArch64::Bcc, {}, {}).addImm(CC).addMBB(DestMBB);
   I.eraseFromParent();
   return true;
 }
 
 bool AArch64InstructionSelector::selectCompareBranch(
-    MachineInstr &I, MachineFunction &MF, MachineRegisterInfo &MRI) const {
+    MachineInstr &I, MachineFunction &MF, MachineRegisterInfo &MRI) {
   Register CondReg = I.getOperand(0).getReg();
   MachineInstr *CCMI = MRI.getVRegDef(CondReg);
   if (CCMI->getOpcode() == TargetOpcode::G_TRUNC) {
     CondReg = CCMI->getOperand(1).getReg();
     CCMI = MRI.getVRegDef(CondReg);
   }
 
   // Try to select the G_BRCOND using whatever is feeding the condition if
   // possible.
-  MachineIRBuilder MIB(I);
   unsigned CCMIOpc = CCMI->getOpcode();
   if (CCMIOpc == TargetOpcode::G_FCMP)
     return selectCompareBranchFedByFCmp(I, *CCMI, MIB);
   if (CCMIOpc == TargetOpcode::G_ICMP)
     return selectCompareBranchFedByICmp(I, *CCMI, MIB);
 
   // Speculation tracking/SLH assumes that optimized TB(N)Z/CB(N)Z
   // instructions will not be produced, as they are conditional branch
static Optional<int64_t> getVectorSHLImm(LLT SrcTy, Register Reg, MachineRegisterInfo &MRI) {
   case 64:
     if (Imm > 63)
       return None;
     break;
   }
   return Imm;
 }
 
-bool AArch64InstructionSelector::selectVectorSHL(
-    MachineInstr &I, MachineRegisterInfo &MRI) const {
+bool AArch64InstructionSelector::selectVectorSHL(MachineInstr &I,
+                                                 MachineRegisterInfo &MRI) {
   assert(I.getOpcode() == TargetOpcode::G_SHL);
   Register DstReg = I.getOperand(0).getReg();
   const LLT Ty = MRI.getType(DstReg);
   Register Src1Reg = I.getOperand(1).getReg();
   Register Src2Reg = I.getOperand(2).getReg();
 
   if (!Ty.isVector())
     return false;
if (Ty == LLT::vector(2, 64)) {
     Opc = ImmVal ? AArch64::SHLv16i8_shift : AArch64::USHLv16i8;
   } else if (Ty == LLT::vector(8, 8)) {
     Opc = ImmVal ? AArch64::SHLv8i8_shift : AArch64::USHLv8i8;
   } else {
     LLVM_DEBUG(dbgs() << "Unhandled G_SHL type");
     return false;
   }
 
-  MachineIRBuilder MIB(I);
   auto Shl = MIB.buildInstr(Opc, {DstReg}, {Src1Reg});
   if (ImmVal)
     Shl.addImm(*ImmVal);
   else
     Shl.addUse(Src2Reg);
   constrainSelectedInstRegOperands(*Shl, TII, TRI, RBI);
   I.eraseFromParent();
   return true;
 }
 
 bool AArch64InstructionSelector::selectVectorAshrLshr(
-    MachineInstr &I, MachineRegisterInfo &MRI) const {
+    MachineInstr &I, MachineRegisterInfo &MRI) {
   assert(I.getOpcode() == TargetOpcode::G_ASHR ||
          I.getOpcode() == TargetOpcode::G_LSHR);
   Register DstReg = I.getOperand(0).getReg();
   const LLT Ty = MRI.getType(DstReg);
   Register Src1Reg = I.getOperand(1).getReg();
   Register Src2Reg = I.getOperand(2).getReg();
 
   if (!Ty.isVector())
bool AArch64InstructionSelector::selectVectorAshrLshr(
   } else if (Ty == LLT::vector(8, 8)) {
     Opc = IsASHR ? AArch64::SSHLv8i8 : AArch64::USHLv8i8;
     NegOpc = AArch64::NEGv8i8;
   } else {
     LLVM_DEBUG(dbgs() << "Unhandled G_ASHR type");
     return false;
   }
 
-  MachineIRBuilder MIB(I);
   auto Neg = MIB.buildInstr(NegOpc, {RC}, {Src2Reg});
   constrainSelectedInstRegOperands(*Neg, TII, TRI, RBI);
   auto SShl = MIB.buildInstr(Opc, {DstReg}, {Src1Reg, Neg});
   constrainSelectedInstRegOperands(*SShl, TII, TRI, RBI);
   I.eraseFromParent();
   return true;
 }
 
MIB = BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(AArch64::STRXui))
             .addImm(0)
             .addMemOperand(*I.memoperands_begin());
 
   constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI);
   I.eraseFromParent();
   return true;
 }
 
 void AArch64InstructionSelector::materializeLargeCMVal(
-    MachineInstr &I, const Value *V, unsigned OpFlags) const {
+    MachineInstr &I, const Value *V, unsigned OpFlags) {
   MachineBasicBlock &MBB = *I.getParent();
   MachineFunction &MF = *MBB.getParent();
   MachineRegisterInfo &MRI = MF.getRegInfo();
-  MachineIRBuilder MIB(I);
 
   auto MovZ = MIB.buildInstr(AArch64::MOVZXi, {&AArch64::GPR64RegClass}, {});
   MovZ->addOperand(MF, I.getOperand(1));
   MovZ->getOperand(1).setTargetFlags(OpFlags | AArch64II::MO_G0 |
                                      AArch64II::MO_NC);
   MovZ->addOperand(MF, MachineOperand::CreateImm(0));
   constrainSelectedInstRegOperands(*MovZ, TII, TRI, RBI);
 
if (SrcTy.isVector())
       return false;
     assert(!ShiftTy.isVector() && "unexpected vector shift ty");
     if (SrcTy.getSizeInBits() != 32 || ShiftTy.getSizeInBits() != 64)
       return false;
     auto *AmtMI = MRI.getVRegDef(ShiftReg);
     assert(AmtMI && "could not find a vreg definition for shift amount");
     if (AmtMI->getOpcode() != TargetOpcode::G_CONSTANT) {
       // Insert a subregister copy to implement a 64->32 trunc
-      MachineIRBuilder MIB(I);
       auto Trunc = MIB.buildInstr(TargetOpcode::COPY, {SrcTy}, {})
                        .addReg(ShiftReg, 0, AArch64::sub_32);
       MRI.setRegBank(Trunc.getReg(0), RBI.getRegBank(AArch64::GPRRegBankID));
       I.getOperand(2).setReg(Trunc.getReg(0));
     }
     return true;
   }
   case TargetOpcode::G_STORE: {
     bool Changed = contractCrossBankCopyIntoStore(I, MRI);
     MachineOperand &SrcOp = I.getOperand(0);
     if (MRI.getType(SrcOp.getReg()).isPointer()) {
       // Allow matching with imported patterns for stores of pointers. Unlike
       // G_LOAD/G_PTR_ADD, we may not have selected all users. So, emit a copy
       // and constrain.
-      MachineIRBuilder MIB(I);
       auto Copy = MIB.buildCopy(LLT::scalar(64), SrcOp);
       Register NewSrc = Copy.getReg(0);
       SrcOp.setReg(NewSrc);
       RBI.constrainGenericRegister(NewSrc, AArch64::GPR64RegClass, MRI);
       Changed = true;
     }
     return Changed;
   }
case TargetOpcode::G_LOAD: {
     MRI.setType(DstReg, LLT::scalar(64));
     return true;
   }
   case AArch64::G_DUP: {
     // Convert the type from p0 to s64 to help selection.
     LLT DstTy = MRI.getType(I.getOperand(0).getReg());
     if (!DstTy.getElementType().isPointer())
       return false;
-    MachineIRBuilder MIB(I);
     auto NewSrc = MIB.buildCopy(LLT::scalar(64), I.getOperand(1).getReg());
     MRI.setType(I.getOperand(0).getReg(),
                 DstTy.changeElementType(LLT::scalar(64)));
     MRI.setRegClass(NewSrc.getReg(0), &AArch64::GPR64RegClass);
     I.getOperand(1).setReg(NewSrc.getReg(0));
     return true;
   }
   case TargetOpcode::G_UITOFP:
bool AArch64InstructionSelector::convertPtrAddToAdd(
     MachineInstr &I, MachineRegisterInfo &MRI) {
   assert(I.getOpcode() == TargetOpcode::G_PTR_ADD && "Expected G_PTR_ADD");
   Register DstReg = I.getOperand(0).getReg();
   Register AddOp1Reg = I.getOperand(1).getReg();
   const LLT PtrTy = MRI.getType(DstReg);
   if (PtrTy.getAddressSpace() != 0)
     return false;
 
-  MachineIRBuilder MIB(I);
   const LLT CastPtrTy = PtrTy.isVector() ? LLT::vector(2, 64) : LLT::scalar(64);
   auto PtrToInt = MIB.buildPtrToInt(CastPtrTy, AddOp1Reg);
   // Set regbanks on the registers.
   if (PtrTy.isVector())
     MRI.setRegBank(PtrToInt.getReg(0), RBI.getRegBank(AArch64::FPRRegBankID));
   else
     MRI.setRegBank(PtrToInt.getReg(0), RBI.getRegBank(AArch64::GPRRegBankID));
 
bool AArch64InstructionSelector::convertPtrAddToAdd(
   Register NegatedReg;
   if (!mi_match(I.getOperand(2).getReg(), MRI, m_Neg(m_Reg(NegatedReg))))
     return true;
   I.getOperand(2).setReg(NegatedReg);
   I.setDesc(TII.get(TargetOpcode::G_SUB));
   return true;
 }
 
-bool AArch64InstructionSelector::earlySelectSHL(
-    MachineInstr &I, MachineRegisterInfo &MRI) const {
+bool AArch64InstructionSelector::earlySelectSHL(MachineInstr &I,
+                                                MachineRegisterInfo &MRI) {
   // We try to match the immediate variant of LSL, which is actually an alias
   // for a special case of UBFM. Otherwise, we fall back to the imported
   // selector which will match the register variant.
   assert(I.getOpcode() == TargetOpcode::G_SHL && "unexpected op");
   const auto &MO = I.getOperand(2);
   auto VRegAndVal = getConstantVRegVal(MO.getReg(), MRI);
   if (!VRegAndVal)
     return false;
 
   const LLT DstTy = MRI.getType(I.getOperand(0).getReg());
   if (DstTy.isVector())
     return false;
   bool Is64Bit = DstTy.getSizeInBits() == 64;
   auto Imm1Fn = Is64Bit ? selectShiftA_64(MO) : selectShiftA_32(MO);
   auto Imm2Fn = Is64Bit ? selectShiftB_64(MO) : selectShiftB_32(MO);
-  MachineIRBuilder MIB(I);
 
   if (!Imm1Fn || !Imm2Fn)
     return false;
 
   auto NewI =
       MIB.buildInstr(Is64Bit ? AArch64::UBFMXri : AArch64::UBFMWri,
                      {I.getOperand(0).getReg()}, {I.getOperand(1).getReg()});
 
if (RBI.getRegBank(StoreSrcReg, MRI, TRI) ==
       RBI.getRegBank(DefDstReg, MRI, TRI))
     return false;
 
   // We have a cross-bank copy, which is entering a store. Let's fold it.
   I.getOperand(0).setReg(DefDstReg);
   return true;
 }
 
-bool AArch64InstructionSelector::earlySelect(MachineInstr &I) const {
+bool AArch64InstructionSelector::earlySelect(MachineInstr &I) {
   assert(I.getParent() && "Instruction should be in a basic block!");
   assert(I.getParent()->getParent() && "Instruction should be in a function!");
 
   MachineBasicBlock &MBB = *I.getParent();
   MachineFunction &MF = *MBB.getParent();
   MachineRegisterInfo &MRI = MF.getRegInfo();
 
   switch (I.getOpcode()) {
   case AArch64::G_DUP: {
     // Before selecting a DUP instruction, check if it is better selected as a
     // MOV or load from a constant pool.
     Register Src = I.getOperand(1).getReg();
     auto ValAndVReg = getConstantVRegValWithLookThrough(Src, MRI);
     if (!ValAndVReg)
       return false;
     LLVMContext &Ctx = MF.getFunction().getContext();
     Register Dst = I.getOperand(0).getReg();
     auto *CV = ConstantDataVector::getSplat(
         MRI.getType(Dst).getNumElements(),
         ConstantInt::get(Type::getIntNTy(Ctx, MRI.getType(Src).getSizeInBits()),
                          ValAndVReg->Value));
-    MachineIRBuilder MIRBuilder(I);
-    if (!emitConstantVector(Dst, CV, MIRBuilder, MRI))
+    if (!emitConstantVector(Dst, CV, MIB, MRI))
       return false;
     I.eraseFromParent();
     return true;
   }
   case TargetOpcode::G_BR: {
     // If the branch jumps to the fallthrough block, don't bother emitting it.
     // Only do this for -O0 for a good code size improvement, because when
     // optimizations are enabled we want to leave this choice to
case TargetOpcode::G_ADD: {
     Register CmpReg = I.getOperand(2).getReg();
     MachineInstr *Cmp = getOpcodeDef(TargetOpcode::G_ICMP, CmpReg, MRI);
     if (!Cmp) {
       std::swap(X, CmpReg);
       Cmp = getOpcodeDef(TargetOpcode::G_ICMP, CmpReg, MRI);
       if (!Cmp)
         return false;
     }
-    MachineIRBuilder MIRBuilder(I);
     auto Pred =
         static_cast<CmpInst::Predicate>(Cmp->getOperand(1).getPredicate());
     emitIntegerCompare(Cmp->getOperand(2), Cmp->getOperand(3),
-                       Cmp->getOperand(1), MIRBuilder);
-    emitCSetForICMP(I.getOperand(0).getReg(), Pred, MIRBuilder, X);
+                       Cmp->getOperand(1), MIB);
+    emitCSetForICMP(I.getOperand(0).getReg(), Pred, MIB, X);
     I.eraseFromParent();
     return true;
   }
   default:
     return false;
   }
 }
 
 bool AArch64InstructionSelector::select(MachineInstr &I) {
   assert(I.getParent() && "Instruction should be in a basic block!");
   assert(I.getParent()->getParent() && "Instruction should be in a function!");
 
   MachineBasicBlock &MBB = *I.getParent();
   MachineFunction &MF = *MBB.getParent();
   MachineRegisterInfo &MRI = MF.getRegInfo();
 
   const AArch64Subtarget *Subtarget =
       &static_cast<const AArch64Subtarget &>(MF.getSubtarget());
   if (Subtarget->requiresStrictAlign()) {
     // We don't support this feature yet.
     LLVM_DEBUG(dbgs() << "AArch64 GISel does not support strict-align yet\n");
     return false;
   }
 
+  MIB.setInstrAndDebugLoc(I);
+
   unsigned Opcode = I.getOpcode();
   // G_PHI requires same handling as PHI
   if (!I.isPreISelOpcode() || Opcode == TargetOpcode::G_PHI) {
     // Certain non-generic instructions also need some special handling.
 
     if (Opcode ==  TargetOpcode::LOAD_STACK_GUARD)
       return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
 
if (earlySelect(I))
     return true;
 
   if (selectImpl(I, *CoverageInfo))
     return true;
 
   LLT Ty =
       I.getOperand(0).isReg() ? MRI.getType(I.getOperand(0).getReg()) : LLT{};
 
-  MachineIRBuilder MIB(I);
-
   switch (Opcode) {
   case TargetOpcode::G_SBFX:
   case TargetOpcode::G_UBFX: {
     static const unsigned OpcTable[2][2] = {
         {AArch64::UBFMWri, AArch64::UBFMXri},
         {AArch64::SBFMWri, AArch64::SBFMXri}};
     bool IsSigned = Opcode == TargetOpcode::G_SBFX;
     unsigned Size = Ty.getSizeInBits();
     unsigned Opc = OpcTable[IsSigned][Size == 64];
     auto Cst1 =
         getConstantVRegValWithLookThrough(I.getOperand(2).getReg(), MRI);
     assert(Cst1 && "Should have gotten a constant for src 1?");
     auto Cst2 =
         getConstantVRegValWithLookThrough(I.getOperand(3).getReg(), MRI);
     assert(Cst2 && "Should have gotten a constant for src 2?");
     auto LSB = Cst1->Value.getZExtValue();
     auto Width = Cst2->Value.getZExtValue();
-    MachineIRBuilder MIB(I);
     auto BitfieldInst =
         MIB.buildInstr(Opc, {I.getOperand(0)}, {I.getOperand(1)})
             .addImm(LSB)
             .addImm(Width);
     I.eraseFromParent();
     return constrainSelectedInstRegOperands(*BitfieldInst, TII, TRI, RBI);
   }
   case TargetOpcode::G_BRCOND:
case AArch64::G_ADD_LOW: {
     MachineInstr *BaseMI = MRI.getVRegDef(I.getOperand(1).getReg());
     if (BaseMI->getOpcode() != AArch64::ADRP) {
       I.setDesc(TII.get(AArch64::ADDXri));
       I.addOperand(MachineOperand::CreateImm(0));
       return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
     }
     assert(TM.getCodeModel() == CodeModel::Small &&
            "Expected small code model");
-    MachineIRBuilder MIB(I);
     auto Op1 = BaseMI->getOperand(1);
     auto Op2 = I.getOperand(2);
     auto MovAddr = MIB.buildInstr(AArch64::MOVaddr, {I.getOperand(0)}, {})
                        .addGlobalAddress(Op1.getGlobal(), Op1.getOffset(),
                                          Op1.getTargetFlags())
                        .addGlobalAddress(Op2.getGlobal(), Op2.getOffset(),
                                          Op2.getTargetFlags());
     I.eraseFromParent();
if (isFP) {
                         : (DefSize == 64 ? AArch64::FPR64RegClass 
                                          : AArch64::FPR128RegClass);
 
       // For 64b values, emit a constant pool load instead.
       // For s32, use a cp load if we have optsize/minsize.
       if (DefSize == 64 || DefSize == 128 ||
           (DefSize == 32 && shouldOptForSize(&MF))) {
         auto *FPImm = I.getOperand(1).getFPImm();
-        MachineIRBuilder MIB(I);
         auto *LoadMI = emitLoadFromConstantPool(FPImm, MIB);
         if (!LoadMI) {
           LLVM_DEBUG(dbgs() << "Failed to load double constant pool entry\n");
           return false;
         }
         MIB.buildCopy({DefReg}, {LoadMI->getOperand(0).getReg()});
         I.eraseFromParent();
         return RBI.constrainGenericRegister(DefReg, FPRRC, MRI);
if (SrcTy.getSizeInBits() > 64) {
       (void)SrcRB;
 
       // Emit the same code as a vector extract.
       // Offset must be a multiple of 64.
       unsigned Offset = I.getOperand(2).getImm();
       if (Offset % 64 != 0)
         return false;
       unsigned LaneIdx = Offset / 64;
-      MachineIRBuilder MIB(I);
       MachineInstr *Extract = emitExtractVectorElt(
           DstReg, DstRB, LLT::scalar(64), SrcReg, LaneIdx, MIB);
       if (!Extract)
         return false;
       I.eraseFromParent();
       return true;
     }
 
case TargetOpcode::G_GLOBAL_VALUE: {
     }
     return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
   }
 
   case TargetOpcode::G_ZEXTLOAD:
   case TargetOpcode::G_LOAD:
   case TargetOpcode::G_STORE: {
     bool IsZExtLoad = I.getOpcode() == TargetOpcode::G_ZEXTLOAD;
-    MachineIRBuilder MIB(I);
-
     LLT PtrTy = MRI.getType(I.getOperand(1).getReg());
 
     if (PtrTy != LLT::pointer(0, 64)) {
       LLVM_DEBUG(dbgs() << "Load/Store pointer has type: " << PtrTy
                         << ", expected: " << LLT::pointer(0, 64) << '\n');
       return false;
     }
 
case TargetOpcode::G_OR: {
     // FIXME: Should the type be always reset in setDesc?
 
     // Now that we selected an opcode, we need to constrain the register
     // operands to use appropriate classes.
     return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
   }
 
   case TargetOpcode::G_PTR_ADD: {
-    MachineIRBuilder MIRBuilder(I);
-    emitADD(I.getOperand(0).getReg(), I.getOperand(1), I.getOperand(2),
-            MIRBuilder);
+    emitADD(I.getOperand(0).getReg(), I.getOperand(1), I.getOperand(2), MIB);
     I.eraseFromParent();
     return true;
   }
   case TargetOpcode::G_SADDO:
   case TargetOpcode::G_UADDO:
   case TargetOpcode::G_SSUBO:
   case TargetOpcode::G_USUBO: {
     // Emit the operation and get the correct condition code.
-    MachineIRBuilder MIRBuilder(I);
     auto OpAndCC = emitOverflowOp(Opcode, I.getOperand(0).getReg(),
-                                  I.getOperand(2), I.getOperand(3), MIRBuilder);
+                                  I.getOperand(2), I.getOperand(3), MIB);
 
     // Now, put the overflow result in the register given by the first operand
     // to the overflow op. CSINC increments the result when the predicate is
     // false, so to get the increment when it's true, we need to use the
     // inverse. In this case, we want to increment when carry is set.
     Register ZReg = AArch64::WZR;
-    auto CsetMI = MIRBuilder
-                      .buildInstr(AArch64::CSINCWr, {I.getOperand(1).getReg()},
-                                  {ZReg, ZReg})
+    auto CsetMI = MIB.buildInstr(AArch64::CSINCWr, {I.getOperand(1).getReg()},
                       .addImm(getInvertedCondCode(OpAndCC.second));
     constrainSelectedInstRegOperands(*CsetMI, TII, TRI, RBI);
     I.eraseFromParent();
     return true;
   }
 
   case TargetOpcode::G_PTRMASK: {
     Register MaskReg = I.getOperand(2).getReg();
case TargetOpcode::G_TRUNC: {
     } else if (DstRB.getID() == AArch64::FPRRegBankID) {
       if (DstTy == LLT::vector(4, 16) && SrcTy == LLT::vector(4, 32)) {
         I.setDesc(TII.get(AArch64::XTNv4i16));
         constrainSelectedInstRegOperands(I, TII, TRI, RBI);
         return true;
       }
 
       if (!SrcTy.isVector() && SrcTy.getSizeInBits() == 128) {
-        MachineIRBuilder MIB(I);
         MachineInstr *Extract = emitExtractVectorElt(
             DstReg, DstRB, LLT::scalar(DstTy.getSizeInBits()), SrcReg, 0, MIB);
         if (!Extract)
           return false;
         I.eraseFromParent();
         return true;
       }
 
case TargetOpcode::G_SEXT: {
 
     if (DstTy.isVector())
       return false; // Should be handled by imported patterns.
 
     assert((*RBI.getRegBank(DefReg, MRI, TRI)).getID() ==
                AArch64::GPRRegBankID &&
            "Unexpected ext regbank");
 
-    MachineIRBuilder MIB(I);
     MachineInstr *ExtI;
 
     // First check if we're extending the result of a load which has a dest type
     // smaller than 32 bits, then this zext is redundant. GPR32 is the smallest
     // GPR register on AArch64 and all loads which are smaller automatically
     // zero-extend the upper bits. E.g.
     // %v(s8) = G_LOAD %p, :: (load 1)
     // %v2(s32) = G_ZEXT %v(s8)
case TargetOpcode::G_SELECT: {
     const Register TReg = I.getOperand(2).getReg();
     const Register FReg = I.getOperand(3).getReg();
 
     if (tryOptSelect(I))
       return true;
 
     // Make sure to use an unused vreg instead of wzr, so that the peephole
     // optimizations will be able to optimize these.
-    MachineIRBuilder MIB(I);
     Register DeadVReg = MRI.createVirtualRegister(&AArch64::GPR32RegClass);
     auto TstMI = MIB.buildInstr(AArch64::ANDSWri, {DeadVReg}, {CondReg})
                      .addImm(AArch64_AM::encodeLogicalImmediate(1, 32));
     constrainSelectedInstRegOperands(*TstMI, TII, TRI, RBI);
     if (!emitSelect(I.getOperand(0).getReg(), TReg, FReg, AArch64CC::NE, MIB))
       return false;
     I.eraseFromParent();
     return true;
   }
   case TargetOpcode::G_ICMP: {
     if (Ty.isVector())
       return selectVectorICmp(I, MRI);
 
     if (Ty != LLT::scalar(32)) {
       LLVM_DEBUG(dbgs() << "G_ICMP result has type: " << Ty
                         << ", expected: " << LLT::scalar(32) << '\n');
       return false;
     }
 
-    MachineIRBuilder MIRBuilder(I);
     auto Pred = static_cast<CmpInst::Predicate>(I.getOperand(1).getPredicate());
     emitIntegerCompare(I.getOperand(2), I.getOperand(3), I.getOperand(1),
-                       MIRBuilder);
-    emitCSetForICMP(I.getOperand(0).getReg(), Pred, MIRBuilder);
+                       MIB);
+    emitCSetForICMP(I.getOperand(0).getReg(), Pred, MIB);
     I.eraseFromParent();
     return true;
   }
 
   case TargetOpcode::G_FCMP: {
-    MachineIRBuilder MIRBuilder(I);
     CmpInst::Predicate Pred =
         static_cast<CmpInst::Predicate>(I.getOperand(1).getPredicate());
-    if (!emitFPCompare(I.getOperand(2).getReg(), I.getOperand(3).getReg(),
-                       MIRBuilder, Pred) ||
-        !emitCSetForFCmp(I.getOperand(0).getReg(), Pred, MIRBuilder))
+    if (!emitFPCompare(I.getOperand(2).getReg(), I.getOperand(3).getReg(), MIB,
+                       Pred) ||
+        !emitCSetForFCmp(I.getOperand(0).getReg(), Pred, MIB))
       return false;
     I.eraseFromParent();
     return true;
   }
   case TargetOpcode::G_VASTART:
     return STI.isTargetDarwin() ? selectVaStartDarwin(I, MF, MRI)
                                 : selectVaStartAAPCS(I, MF, MRI);
   case TargetOpcode::G_INTRINSIC:
#endif
   case TargetOpcode::G_VECREDUCE_FADD:
   case TargetOpcode::G_VECREDUCE_ADD:
     return selectReduction(I, MRI);
   }
 
   return false;
 }
 
-bool AArch64InstructionSelector::selectReduction(
-    MachineInstr &I, MachineRegisterInfo &MRI) const {
+bool AArch64InstructionSelector::selectReduction(MachineInstr &I,
+                                                 MachineRegisterInfo &MRI) {
   Register VecReg = I.getOperand(1).getReg();
   LLT VecTy = MRI.getType(VecReg);
   if (I.getOpcode() == TargetOpcode::G_VECREDUCE_ADD) {
     // For <2 x i32> ADDPv2i32 generates an FPR64 value, so we need to emit
     // a subregister copy afterwards.
     if (VecTy == LLT::vector(2, 32)) {
-      MachineIRBuilder MIB(I);
       Register DstReg = I.getOperand(0).getReg();
       auto AddP = MIB.buildInstr(AArch64::ADDPv2i32, {&AArch64::FPR64RegClass},
                                  {VecReg, VecReg});
       auto Copy = MIB.buildInstr(TargetOpcode::COPY, {DstReg}, {})
                       .addReg(AddP.getReg(0), 0, AArch64::ssub)
                       .getReg(0);
       RBI.constrainGenericRegister(Copy, AArch64::FPR32RegClass, MRI);
       I.eraseFromParent();
if (I.getOpcode() == TargetOpcode::G_VECREDUCE_FADD) {
     }
     I.setDesc(TII.get(Opc));
     return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
   }
   return false;
 }
 
 bool AArch64InstructionSelector::selectBrJT(MachineInstr &I,
-                                            MachineRegisterInfo &MRI) const {
+                                            MachineRegisterInfo &MRI) {
   assert(I.getOpcode() == TargetOpcode::G_BRJT && "Expected G_BRJT");
   Register JTAddr = I.getOperand(0).getReg();
   unsigned JTI = I.getOperand(1).getIndex();
   Register Index = I.getOperand(2).getReg();
-  MachineIRBuilder MIB(I);
 
   Register TargetReg = MRI.createVirtualRegister(&AArch64::GPR64RegClass);
   Register ScratchReg = MRI.createVirtualRegister(&AArch64::GPR64spRegClass);
 
   MF->getInfo<AArch64FunctionInfo>()->setJumpTableEntryInfo(JTI, 4, nullptr);
   auto JumpTableInst = MIB.buildInstr(AArch64::JumpTableDest32,
                                       {TargetReg, ScratchReg}, {JTAddr, Index})
                            .addJumpTableIndex(JTI);
   // Build the indirect branch.
   MIB.buildInstr(AArch64::BR, {}, {TargetReg});
   I.eraseFromParent();
   return constrainSelectedInstRegOperands(*JumpTableInst, TII, TRI, RBI);
 }
 
-bool AArch64InstructionSelector::selectJumpTable(
-    MachineInstr &I, MachineRegisterInfo &MRI) const {
+bool AArch64InstructionSelector::selectJumpTable(MachineInstr &I,
+                                                 MachineRegisterInfo &MRI) {
   assert(I.getOpcode() == TargetOpcode::G_JUMP_TABLE && "Expected jump table");
   assert(I.getOperand(1).isJTI() && "Jump table op should have a JTI!");
 
   Register DstReg = I.getOperand(0).getReg();
   unsigned JTI = I.getOperand(1).getIndex();
   // We generate a MOVaddrJT which will get expanded to an ADRP + ADD later.
-  MachineIRBuilder MIB(I);
   auto MovMI =
     MIB.buildInstr(AArch64::MOVaddrJT, {DstReg}, {})
           .addJumpTableIndex(JTI, AArch64II::MO_PAGE)
           .addJumpTableIndex(JTI, AArch64II::MO_NC | AArch64II::MO_PAGEOFF);
   I.eraseFromParent();
   return constrainSelectedInstRegOperands(*MovMI, TII, TRI, RBI);
 }
 
 bool AArch64InstructionSelector::selectTLSGlobalValue(
-    MachineInstr &I, MachineRegisterInfo &MRI) const {
+    MachineInstr &I, MachineRegisterInfo &MRI) {
   if (!STI.isTargetMachO())
     return false;
   MachineFunction &MF = *I.getParent()->getParent();
   MF.getFrameInfo().setAdjustsStack(true);
 
   const auto &GlobalOp = I.getOperand(1);
   assert(GlobalOp.getOffset() == 0 &&
          "Shouldn't have an offset on TLS globals!");
   const GlobalValue &GV = *GlobalOp.getGlobal();
-  MachineIRBuilder MIB(I);
 
   auto LoadGOT =
       MIB.buildInstr(AArch64::LOADgot, {&AArch64::GPR64commonRegClass}, {})
           .addGlobalAddress(&GV, 0, AArch64II::MO_TLS);
 
   auto Load = MIB.buildInstr(AArch64::LDRXui, {&AArch64::GPR64commonRegClass},
                              {LoadGOT.getReg(0)})
                   .addImm(0);
bool AArch64InstructionSelector::selectIntrinsicRound(
   }
 
   // Legalization would have set us up perfectly for this; we just need to
   // set the opcode and move on.
   I.setDesc(TII.get(Opc));
   return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
 }
 
 bool AArch64InstructionSelector::selectVectorICmp(
-    MachineInstr &I, MachineRegisterInfo &MRI) const {
+    MachineInstr &I, MachineRegisterInfo &MRI) {
   Register DstReg = I.getOperand(0).getReg();
   LLT DstTy = MRI.getType(DstReg);
   Register SrcReg = I.getOperand(2).getReg();
   Register Src2Reg = I.getOperand(3).getReg();
   LLT SrcTy = MRI.getType(SrcReg);
 
   unsigned SrcEltSize = SrcTy.getElementType().getSizeInBits();
   unsigned NumElts = DstTy.getNumElements();
bool AArch64InstructionSelector::selectVectorICmp(
 
   unsigned NotOpc = Pred == ICmpInst::ICMP_NE ? AArch64::NOTv8i8 : 0;
   if (SrcTy.getSizeInBits() == 128)
     NotOpc = NotOpc ? AArch64::NOTv16i8 : 0;
 
   if (SwapOperands)
     std::swap(SrcReg, Src2Reg);
 
-  MachineIRBuilder MIB(I);
   auto Cmp = MIB.buildInstr(Opc, {SrcRC}, {SrcReg, Src2Reg});
   constrainSelectedInstRegOperands(*Cmp, TII, TRI, RBI);
 
   // Invert if we had a 'ne' cc.
   if (NotOpc) {
     Cmp = MIB.buildInstr(NotOpc, {DstReg}, {Cmp});
     constrainSelectedInstRegOperands(*Cmp, TII, TRI, RBI);
   } else {
case 32:
     return BuildFn(AArch64::ssub);
   case 64:
     return BuildFn(AArch64::dsub);
   default:
     return nullptr;
   }
 }
 
 bool AArch64InstructionSelector::selectMergeValues(
-    MachineInstr &I, MachineRegisterInfo &MRI) const {
+    MachineInstr &I, MachineRegisterInfo &MRI) {
   assert(I.getOpcode() == TargetOpcode::G_MERGE_VALUES && "unexpected opcode");
   const LLT DstTy = MRI.getType(I.getOperand(0).getReg());
   const LLT SrcTy = MRI.getType(I.getOperand(1).getReg());
   assert(!DstTy.isVector() && !SrcTy.isVector() && "invalid merge operation");
   const RegisterBank &RB = *RBI.getRegBank(I.getOperand(1).getReg(), MRI, TRI);
 
   if (I.getNumOperands() != 3)
     return false;
 
   // Merging 2 s64s into an s128.
   if (DstTy == LLT::scalar(128)) {
     if (SrcTy.getSizeInBits() != 64)
       return false;
-    MachineIRBuilder MIB(I);
     Register DstReg = I.getOperand(0).getReg();
     Register Src1Reg = I.getOperand(1).getReg();
     Register Src2Reg = I.getOperand(2).getReg();
     auto Tmp = MIB.buildInstr(TargetOpcode::IMPLICIT_DEF, {DstTy}, {});
     MachineInstr *InsMI =
         emitLaneInsert(None, Tmp.getReg(0), Src1Reg, /* LaneIdx */ 0, RB, MIB);
     if (!InsMI)
       return false;
MachineInstr *LaneCopyMI =
       MIRBuilder.buildInstr(CopyOpc, {*DstReg}, {InsertReg}).addImm(LaneIdx);
   constrainSelectedInstRegOperands(*LaneCopyMI, TII, TRI, RBI);
 
   // Make sure that we actually constrain the initial copy.
   RBI.constrainGenericRegister(*DstReg, *DstRC, MRI);
   return LaneCopyMI;
 }
 
 bool AArch64InstructionSelector::selectExtractElt(
-    MachineInstr &I, MachineRegisterInfo &MRI) const {
+    MachineInstr &I, MachineRegisterInfo &MRI) {
   assert(I.getOpcode() == TargetOpcode::G_EXTRACT_VECTOR_ELT &&
          "unexpected opcode!");
   Register DstReg = I.getOperand(0).getReg();
   const LLT NarrowTy = MRI.getType(DstReg);
   const Register SrcReg = I.getOperand(1).getReg();
   const LLT WideTy = MRI.getType(SrcReg);
   (void)WideTy;
   assert(WideTy.getSizeInBits() >= NarrowTy.getSizeInBits() &&
bool AArch64InstructionSelector::selectExtractElt(
   }
 
   // Find the index to extract from.
   auto VRegAndVal = getConstantVRegValWithLookThrough(LaneIdxOp.getReg(), MRI);
   if (!VRegAndVal)
     return false;
   unsigned LaneIdx = VRegAndVal->Value.getSExtValue();
 
-  MachineIRBuilder MIRBuilder(I);
 
   const RegisterBank &DstRB = *RBI.getRegBank(DstReg, MRI, TRI);
   MachineInstr *Extract = emitExtractVectorElt(DstReg, DstRB, NarrowTy, SrcReg,
-                                               LaneIdx, MIRBuilder);
+                                               LaneIdx, MIB);
   if (!Extract)
     return false;
 
   I.eraseFromParent();
   return true;
 }
 
 bool AArch64InstructionSelector::selectSplitVectorUnmerge(
-    MachineInstr &I, MachineRegisterInfo &MRI) const {
+    MachineInstr &I, MachineRegisterInfo &MRI) {
   unsigned NumElts = I.getNumOperands() - 1;
   Register SrcReg = I.getOperand(NumElts).getReg();
   const LLT NarrowTy = MRI.getType(I.getOperand(0).getReg());
   const LLT SrcTy = MRI.getType(SrcReg);
 
   assert(NarrowTy.isVector() && "Expected an unmerge into vectors");
   if (SrcTy.getSizeInBits() > 128) {
     LLVM_DEBUG(dbgs() << "Unexpected vector type for vec split unmerge");
     return false;
   }
 
-  MachineIRBuilder MIB(I);
-
   // We implement a split vector operation by treating the sub-vectors as
   // scalars and extracting them.
   const RegisterBank &DstRB =
       *RBI.getRegBank(I.getOperand(0).getReg(), MRI, TRI);
   for (unsigned OpIdx = 0; OpIdx < NumElts; ++OpIdx) {
     Register Dst = I.getOperand(OpIdx).getReg();
     MachineInstr *Extract =
         emitExtractVectorElt(Dst, DstRB, NarrowTy, SrcReg, OpIdx, MIB);
     if (!Extract)
       return false;
   }
   I.eraseFromParent();
   return true;
 }
 
-bool AArch64InstructionSelector::selectUnmergeValues(
-    MachineInstr &I, MachineRegisterInfo &MRI) const {
+bool AArch64InstructionSelector::selectUnmergeValues(MachineInstr &I,
+                                                     MachineRegisterInfo &MRI) {
   assert(I.getOpcode() == TargetOpcode::G_UNMERGE_VALUES &&
          "unexpected opcode");
 
   // TODO: Handle unmerging into GPRs and from scalars to scalars.
   if (RBI.getRegBank(I.getOperand(0).getReg(), MRI, TRI)->getID() !=
           AArch64::FPRRegBankID ||
       RBI.getRegBank(I.getOperand(1).getReg(), MRI, TRI)->getID() !=
           AArch64::FPRRegBankID) {
bool AArch64InstructionSelector::selectUnmergeValues(MachineInstr &I,
   assert((WideTy.isVector() || WideTy.getSizeInBits() == 128) &&
          "can only unmerge from vector or s128 types!");
   assert(WideTy.getSizeInBits() > NarrowTy.getSizeInBits() &&
          "source register size too small!");
 
   if (!NarrowTy.isScalar())
     return selectSplitVectorUnmerge(I, MRI);
 
-  MachineIRBuilder MIB(I);
-
   // Choose a lane copy opcode and subregister based off of the size of the
   // vector's elements.
   unsigned CopyOpc = 0;
   unsigned ExtractSubReg = 0;
   if (!getLaneCopyOpcode(CopyOpc, ExtractSubReg, NarrowTy.getSizeInBits()))
     return false;
 
   // Set up for the lane copies.
if (!RC) {
     return false;
   }
 
   RBI.constrainGenericRegister(CopyTo, *RC, MRI);
   I.eraseFromParent();
   return true;
 }
 
 bool AArch64InstructionSelector::selectConcatVectors(
-    MachineInstr &I, MachineRegisterInfo &MRI) const {
+    MachineInstr &I, MachineRegisterInfo &MRI)  {
   assert(I.getOpcode() == TargetOpcode::G_CONCAT_VECTORS &&
          "Unexpected opcode");
   Register Dst = I.getOperand(0).getReg();
   Register Op1 = I.getOperand(1).getReg();
   Register Op2 = I.getOperand(2).getReg();
-  MachineIRBuilder MIRBuilder(I);
-  MachineInstr *ConcatMI = emitVectorConcat(Dst, Op1, Op2, MIRBuilder);
+  MachineInstr *ConcatMI = emitVectorConcat(Dst, Op1, Op2, MIB);
   if (!ConcatMI)
     return false;
   I.eraseFromParent();
   return true;
 }
 
 unsigned
 AArch64InstructionSelector::emitConstantPoolEntry(const Constant *CPVal,
case TargetOpcode::G_UADDO:
     return std::make_pair(emitADDS(Dst, LHS, RHS, MIRBuilder), AArch64CC::HS);
   case TargetOpcode::G_SSUBO:
     return std::make_pair(emitSUBS(Dst, LHS, RHS, MIRBuilder), AArch64CC::VS);
   case TargetOpcode::G_USUBO:
     return std::make_pair(emitSUBS(Dst, LHS, RHS, MIRBuilder), AArch64CC::LO);
   }
 }
 
-bool AArch64InstructionSelector::tryOptSelect(MachineInstr &I) const {
-  MachineIRBuilder MIB(I);
+bool AArch64InstructionSelector::tryOptSelect(MachineInstr &I) {
   MachineRegisterInfo &MRI = *MIB.getMRI();
   // We want to recognize this pattern:
   //
   // $z = G_FCMP pred, $x, $y
   // ...
   // $w = G_SELECT $z, $a, $b
   //
   // Where the value of $z is *only* ever used by the G_SELECT (possibly with
if (!CmpInst::isUnsigned(P) && LHSDef &&
 
     return emitTST(LHSDef->getOperand(1),
                    LHSDef->getOperand(2), MIRBuilder);
   }
 
   return nullptr;
 }
 
 bool AArch64InstructionSelector::selectShuffleVector(
-    MachineInstr &I, MachineRegisterInfo &MRI) const {
+    MachineInstr &I, MachineRegisterInfo &MRI) {
   const LLT DstTy = MRI.getType(I.getOperand(0).getReg());
   Register Src1Reg = I.getOperand(1).getReg();
   const LLT Src1Ty = MRI.getType(Src1Reg);
   Register Src2Reg = I.getOperand(2).getReg();
   const LLT Src2Ty = MRI.getType(Src2Reg);
   ArrayRef<int> Mask = I.getOperand(3).getShuffleMask();
 
   MachineBasicBlock &MBB = *I.getParent();
for (int Val : Mask) {
     // optimized in future, e.g. to select DUP etc.
     Val = Val < 0 ? 0 : Val;
     for (unsigned Byte = 0; Byte < BytesPerElt; ++Byte) {
       unsigned Offset = Byte + Val * BytesPerElt;
       CstIdxs.emplace_back(ConstantInt::get(Type::getInt8Ty(Ctx), Offset));
     }
   }
 
-  MachineIRBuilder MIRBuilder(I);
-
   // Use a constant pool to load the index vector for TBL.
   Constant *CPVal = ConstantVector::get(CstIdxs);
-  MachineInstr *IndexLoad = emitLoadFromConstantPool(CPVal, MIRBuilder);
+  MachineInstr *IndexLoad = emitLoadFromConstantPool(CPVal, MIB);
   if (!IndexLoad) {
     LLVM_DEBUG(dbgs() << "Could not load from a constant pool");
     return false;
   }
 
   if (DstTy.getSizeInBits() != 128) {
     assert(DstTy.getSizeInBits() == 64 && "Unexpected shuffle result ty");
     // This case can be done with TBL1.
-    MachineInstr *Concat = emitVectorConcat(None, Src1Reg, Src2Reg, MIRBuilder);
+    MachineInstr *Concat = emitVectorConcat(None, Src1Reg, Src2Reg, MIB);
     if (!Concat) {
       LLVM_DEBUG(dbgs() << "Could not do vector concat for tbl1");
       return false;
     }
 
     // The constant pool load will be 64 bits, so need to convert to FPR128 reg.
-    IndexLoad =
-        emitScalarToVector(64, &AArch64::FPR128RegClass,
-                           IndexLoad->getOperand(0).getReg(), MIRBuilder);
+    IndexLoad = emitScalarToVector(64, &AArch64::FPR128RegClass,
+                                   IndexLoad->getOperand(0).getReg(), MIB);
 
-    auto TBL1 = MIRBuilder.buildInstr(
+    auto TBL1 = MIB.buildInstr(
         AArch64::TBLv16i8One, {&AArch64::FPR128RegClass},
         {Concat->getOperand(0).getReg(), IndexLoad->getOperand(0).getReg()});
     constrainSelectedInstRegOperands(*TBL1, TII, TRI, RBI);
 
     auto Copy =
-        MIRBuilder
-            .buildInstr(TargetOpcode::COPY, {I.getOperand(0).getReg()}, {})
+        MIB.buildInstr(TargetOpcode::COPY, {I.getOperand(0).getReg()}, {})
             .addReg(TBL1.getReg(0), 0, AArch64::dsub);
     RBI.constrainGenericRegister(Copy.getReg(0), AArch64::FPR64RegClass, MRI);
     I.eraseFromParent();
     return true;
   }
 
   // For TBL2 we need to emit a REG_SEQUENCE to tie together two consecutive
   // Q registers for regalloc.
-  auto RegSeq = MIRBuilder
-                    .buildInstr(TargetOpcode::REG_SEQUENCE,
-                                {&AArch64::QQRegClass}, {Src1Reg})
+  auto RegSeq = MIB.buildInstr(TargetOpcode::REG_SEQUENCE,
                     .addImm(AArch64::qsub0)
                     .addUse(Src2Reg)
                     .addImm(AArch64::qsub1);
 
-  auto TBL2 = MIRBuilder.buildInstr(AArch64::TBLv16i8Two, {I.getOperand(0)},
-                                    {RegSeq, IndexLoad->getOperand(0)});
+  auto TBL2 = MIB.buildInstr(AArch64::TBLv16i8Two, {I.getOperand(0)},
   constrainSelectedInstRegOperands(*RegSeq, TII, TRI, RBI);
   constrainSelectedInstRegOperands(*TBL2, TII, TRI, RBI);
   I.eraseFromParent();
   return true;
 }
 
 MachineInstr *AArch64InstructionSelector::emitLaneInsert(
     Optional<Register> DstReg, Register SrcReg, Register EltReg,
InsElt = MIRBuilder.buildInstr(Opc, {*DstReg}, {SrcReg})
                  .addImm(LaneIdx)
                  .addUse(EltReg);
   }
 
   constrainSelectedInstRegOperands(*InsElt, TII, TRI, RBI);
   return InsElt;
 }
 
-bool AArch64InstructionSelector::selectInsertElt(
-    MachineInstr &I, MachineRegisterInfo &MRI) const {
+bool AArch64InstructionSelector::selectInsertElt(MachineInstr &I,
+                                                 MachineRegisterInfo &MRI) {
   assert(I.getOpcode() == TargetOpcode::G_INSERT_VECTOR_ELT);
 
   // Get information on the destination.
   Register DstReg = I.getOperand(0).getReg();
   const LLT DstTy = MRI.getType(DstReg);
   unsigned VecSize = DstTy.getSizeInBits();
 
   // Get information on the element we want to insert into the destination.
bool AArch64InstructionSelector::selectInsertElt(MachineInstr &I,
   auto VRegAndVal = getConstantVRegValWithLookThrough(IdxReg, MRI);
   if (!VRegAndVal)
     return false;
   unsigned LaneIdx = VRegAndVal->Value.getSExtValue();
 
   // Perform the lane insert.
   Register SrcReg = I.getOperand(1).getReg();
   const RegisterBank &EltRB = *RBI.getRegBank(EltReg, MRI, TRI);
-  MachineIRBuilder MIRBuilder(I);
 
   if (VecSize < 128) {
     // If the vector we're inserting into is smaller than 128 bits, widen it
     // to 128 to do the insert.
-    MachineInstr *ScalarToVec = emitScalarToVector(
-        VecSize, &AArch64::FPR128RegClass, SrcReg, MIRBuilder);
+    MachineInstr *ScalarToVec =
+        emitScalarToVector(VecSize, &AArch64::FPR128RegClass, SrcReg, MIB);
     if (!ScalarToVec)
       return false;
     SrcReg = ScalarToVec->getOperand(0).getReg();
   }
 
   // Create an insert into a new FPR128 register.
   // Note that if our vector is already 128 bits, we end up emitting an extra
   // register.
   MachineInstr *InsMI =
-      emitLaneInsert(None, SrcReg, EltReg, LaneIdx, EltRB, MIRBuilder);
+      emitLaneInsert(None, SrcReg, EltReg, LaneIdx, EltRB, MIB);
 
   if (VecSize < 128) {
     // If we had to widen to perform the insert, then we have to demote back to
     // the original size to get the result we want.
     Register DemoteVec = InsMI->getOperand(0).getReg();
     const TargetRegisterClass *RC =
         getMinClassForRegBank(*RBI.getRegBank(DemoteVec, MRI, TRI), VecSize);
     if (RC != &AArch64::FPR32RegClass && RC != &AArch64::FPR64RegClass) {
       LLVM_DEBUG(dbgs() << "Unsupported register class!\n");
       return false;
     }
     unsigned SubReg = 0;
     if (!getSubRegForClass(RC, TRI, SubReg))
       return false;
     if (SubReg != AArch64::ssub && SubReg != AArch64::dsub) {
       LLVM_DEBUG(dbgs() << "Unsupported destination size! (" << VecSize
                         << "\n");
       return false;
     }
-    MIRBuilder.buildInstr(TargetOpcode::COPY, {DstReg}, {})
+    MIB.buildInstr(TargetOpcode::COPY, {DstReg}, {})
         .addReg(DemoteVec, 0, SubReg);
     RBI.constrainGenericRegister(DstReg, *RC, MRI);
   } else {
     // No widening needed.
     InsMI->getOperand(0).setReg(DstReg);
     constrainSelectedInstRegOperands(*InsMI, TII, TRI, RBI);
   }
 
   I.eraseFromParent();
   return true;
 }
 
 MachineInstr *
 AArch64InstructionSelector::emitConstantVector(Register Dst, Constant *CV,
                                                MachineIRBuilder &MIRBuilder,
-                                               MachineRegisterInfo &MRI) const {
+                                               MachineRegisterInfo &MRI) {
   LLT DstTy = MRI.getType(Dst);
   unsigned DstSize = DstTy.getSizeInBits();
   if (CV->isNullValue()) {
     if (DstSize == 128) {
       auto Mov =
           MIRBuilder.buildInstr(AArch64::MOVIv2d_ns, {Dst}, {}).addImm(0);
       constrainSelectedInstRegOperands(*Mov, TII, TRI, RBI);
       return &*Mov;
AArch64InstructionSelector::emitConstantVector(Register Dst, Constant *CV,
 
   auto Copy = MIRBuilder.buildCopy(Dst, CPLoad->getOperand(0));
   RBI.constrainGenericRegister(
       Dst, *MRI.getRegClass(CPLoad->getOperand(0).getReg()), MRI);
   return &*Copy;
 }
 
 bool AArch64InstructionSelector::tryOptConstantBuildVec(
-    MachineInstr &I, LLT DstTy, MachineRegisterInfo &MRI) const {
+    MachineInstr &I, LLT DstTy, MachineRegisterInfo &MRI) {
   assert(I.getOpcode() == TargetOpcode::G_BUILD_VECTOR);
   unsigned DstSize = DstTy.getSizeInBits();
   assert(DstSize <= 128 && "Unexpected build_vec type!");
   if (DstSize < 32)
     return false;
   // Check if we're building a constant vector, in which case we want to
   // generate a constant pool load instead of a vector insert sequence.
   SmallVector<Constant *, 16> Csts;
   for (unsigned Idx = 1; Idx < I.getNumOperands(); ++Idx) {
     // Try to find G_CONSTANT or G_FCONSTANT
     auto *OpMI =
         getOpcodeDef(TargetOpcode::G_CONSTANT, I.getOperand(Idx).getReg(), MRI);
     if (OpMI)
       Csts.emplace_back(
           const_cast<ConstantInt *>(OpMI->getOperand(1).getCImm()));
     else if ((OpMI = getOpcodeDef(TargetOpcode::G_FCONSTANT,
                                   I.getOperand(Idx).getReg(), MRI)))
       Csts.emplace_back(
           const_cast<ConstantFP *>(OpMI->getOperand(1).getFPImm()));
     else
       return false;
   }
   Constant *CV = ConstantVector::get(Csts);
-  MachineIRBuilder MIB(I);
   if (!emitConstantVector(I.getOperand(0).getReg(), CV, MIB, MRI))
     return false;
   I.eraseFromParent();
   return true;
 }
 
-bool AArch64InstructionSelector::selectBuildVector(
-    MachineInstr &I, MachineRegisterInfo &MRI) const {
+bool AArch64InstructionSelector::selectBuildVector(MachineInstr &I,
+                                                   MachineRegisterInfo &MRI) {
   assert(I.getOpcode() == TargetOpcode::G_BUILD_VECTOR);
   // Until we port more of the optimized selections, for now just use a vector
   // insert sequence.
   const LLT DstTy = MRI.getType(I.getOperand(0).getReg());
   const LLT EltTy = MRI.getType(I.getOperand(1).getReg());
   unsigned EltSize = EltTy.getSizeInBits();
 
   if (tryOptConstantBuildVec(I, DstTy, MRI))
     return true;
   if (EltSize < 16 || EltSize > 64)
     return false; // Don't support all element types yet.
   const RegisterBank &RB = *RBI.getRegBank(I.getOperand(1).getReg(), MRI, TRI);
-  MachineIRBuilder MIRBuilder(I);
 
   const TargetRegisterClass *DstRC = &AArch64::FPR128RegClass;
   MachineInstr *ScalarToVec =
       emitScalarToVector(DstTy.getElementType().getSizeInBits(), DstRC,
-                         I.getOperand(1).getReg(), MIRBuilder);
+                         I.getOperand(1).getReg(), MIB);
   if (!ScalarToVec)
     return false;
 
   Register DstVec = ScalarToVec->getOperand(0).getReg();
   unsigned DstSize = DstTy.getSizeInBits();
 
   // Keep track of the last MI we inserted. Later on, we might be able to save
   // a copy using it.
   MachineInstr *PrevMI = nullptr;
   for (unsigned i = 2, e = DstSize / EltSize + 1; i < e; ++i) {
     // Note that if we don't do a subregister copy, we can end up making an
     // extra register.
     PrevMI = &*emitLaneInsert(None, DstVec, I.getOperand(i).getReg(), i - 1, RB,
-                              MIRBuilder);
+                              MIB);
     DstVec = PrevMI->getOperand(0).getReg();
   }
 
   // If DstTy's size in bits is less than 128, then emit a subregister copy
   // from DstVec to the last register we've defined.
   if (DstSize < 128) {
     // Force this to be FPR using the destination vector.
     const TargetRegisterClass *RC =
if (SubReg != AArch64::ssub && SubReg != AArch64::dsub) {
       LLVM_DEBUG(dbgs() << "Unsupported destination size! (" << DstSize
                         << "\n");
       return false;
     }
 
     Register Reg = MRI.createVirtualRegister(RC);
     Register DstReg = I.getOperand(0).getReg();
 
-    MIRBuilder.buildInstr(TargetOpcode::COPY, {DstReg}, {})
-        .addReg(DstVec, 0, SubReg);
+    MIB.buildInstr(TargetOpcode::COPY, {DstReg}, {}).addReg(DstVec, 0, SubReg);
     MachineOperand &RegOp = I.getOperand(1);
     RegOp.setReg(Reg);
     RBI.constrainGenericRegister(DstReg, *RC, MRI);
   } else {
     // We don't need a subregister copy. Save a copy by re-using the
     // destination register on the final insert.
     assert(PrevMI && "PrevMI was null?");
     PrevMI->getOperand(0).setReg(I.getOperand(0).getReg());
auto IntrinOp = find_if(I.operands(), [&](const MachineOperand &Op) {
     return Op.isIntrinsicID();
   });
   if (IntrinOp == I.operands_end())
     return 0;
   return IntrinOp->getIntrinsicID();
 }
 
 bool AArch64InstructionSelector::selectIntrinsicWithSideEffects(
-    MachineInstr &I, MachineRegisterInfo &MRI) const {
+    MachineInstr &I, MachineRegisterInfo &MRI) {
   // Find the intrinsic ID.
   unsigned IntrinID = findIntrinsicID(I);
   if (!IntrinID)
     return false;
-  MachineIRBuilder MIRBuilder(I);
 
   // Select the instruction.
   switch (IntrinID) {
   default:
     return false;
   case Intrinsic::trap:
-    MIRBuilder.buildInstr(AArch64::BRK, {}, {}).addImm(1);
+    MIB.buildInstr(AArch64::BRK, {}, {}).addImm(1);
     break;
   case Intrinsic::debugtrap:
-    MIRBuilder.buildInstr(AArch64::BRK, {}, {}).addImm(0xF000);
+    MIB.buildInstr(AArch64::BRK, {}, {}).addImm(0xF000);
     break;
   case Intrinsic::ubsantrap:
-    MIRBuilder.buildInstr(AArch64::BRK, {}, {})
+    MIB.buildInstr(AArch64::BRK, {}, {})
         .addImm(I.getOperand(1).getImm() | ('U' << 8));
     break;
   }
 
   I.eraseFromParent();
   return true;
 }
 
 bool AArch64InstructionSelector::selectIntrinsic(MachineInstr &I,
                                                  MachineRegisterInfo &MRI) {
   unsigned IntrinID = findIntrinsicID(I);
   if (!IntrinID)
     return false;
-  MachineIRBuilder MIRBuilder(I);
 
   switch (IntrinID) {
   default:
     break;
   case Intrinsic::aarch64_crypto_sha1h: {
     Register DstReg = I.getOperand(0).getReg();
     Register SrcReg = I.getOperand(2).getReg();
 
     // FIXME: Should this be an assert?
     if (MRI.getType(DstReg).getSizeInBits() != 32 ||
         MRI.getType(SrcReg).getSizeInBits() != 32)
       return false;
 
     // The operation has to happen on FPRs. Set up some new FPR registers for
     // the source and destination if they are on GPRs.
     if (RBI.getRegBank(SrcReg, MRI, TRI)->getID() != AArch64::FPRRegBankID) {
       SrcReg = MRI.createVirtualRegister(&AArch64::FPR32RegClass);
-      MIRBuilder.buildCopy({SrcReg}, {I.getOperand(2)});
+      MIB.buildCopy({SrcReg}, {I.getOperand(2)});
 
       // Make sure the copy ends up getting constrained properly.
       RBI.constrainGenericRegister(I.getOperand(2).getReg(),
                                    AArch64::GPR32RegClass, MRI);
     }
 
     if (RBI.getRegBank(DstReg, MRI, TRI)->getID() != AArch64::FPRRegBankID)
       DstReg = MRI.createVirtualRegister(&AArch64::FPR32RegClass);
 
     // Actually insert the instruction.
-    auto SHA1Inst = MIRBuilder.buildInstr(AArch64::SHA1Hrr, {DstReg}, {SrcReg});
+    auto SHA1Inst = MIB.buildInstr(AArch64::SHA1Hrr, {DstReg}, {SrcReg});
     constrainSelectedInstRegOperands(*SHA1Inst, TII, TRI, RBI);
 
     // Did we create a new register for the destination?
     if (DstReg != I.getOperand(0).getReg()) {
       // Yep. Copy the result of the instruction back into the original
       // destination.
-      MIRBuilder.buildCopy({I.getOperand(0)}, {DstReg});
+      MIB.buildCopy({I.getOperand(0)}, {DstReg});
       RBI.constrainGenericRegister(I.getOperand(0).getReg(),
                                    AArch64::GPR32RegClass, MRI);
     }
 
     I.eraseFromParent();
     return true;
   }
   case Intrinsic::frameaddress:
if (Depth == 0 && IntrinID == Intrinsic::returnaddress) {
         // Insert the copy from LR/X30 into the entry block, before it can be
         // clobbered by anything.
         MFI.setReturnAddressIsTaken(true);
         MFReturnAddr = getFunctionLiveInPhysReg(MF, TII, AArch64::LR,
                                                 AArch64::GPR64RegClass);
       }
 
       if (STI.hasPAuth()) {
-        MIRBuilder.buildInstr(AArch64::XPACI, {DstReg}, {MFReturnAddr});
+        MIB.buildInstr(AArch64::XPACI, {DstReg}, {MFReturnAddr});
       } else {
-        MIRBuilder.buildCopy({Register(AArch64::LR)}, {MFReturnAddr});
-        MIRBuilder.buildInstr(AArch64::XPACLRI);
-        MIRBuilder.buildCopy({DstReg}, {Register(AArch64::LR)});
+        MIB.buildCopy({Register(AArch64::LR)}, {MFReturnAddr});
+        MIB.buildInstr(AArch64::XPACLRI);
+        MIB.buildCopy({DstReg}, {Register(AArch64::LR)});
       }
 
       I.eraseFromParent();
       return true;
     }
 
     MFI.setFrameAddressIsTaken(true);
     Register FrameAddr(AArch64::FP);
     while (Depth--) {
       Register NextFrame = MRI.createVirtualRegister(&AArch64::GPR64spRegClass);
       auto Ldr =
-          MIRBuilder.buildInstr(AArch64::LDRXui, {NextFrame}, {FrameAddr})
-              .addImm(0);
+          MIB.buildInstr(AArch64::LDRXui, {NextFrame}, {FrameAddr}).addImm(0);
       constrainSelectedInstRegOperands(*Ldr, TII, TRI, RBI);
       FrameAddr = NextFrame;
     }
 
     if (IntrinID == Intrinsic::frameaddress)
-      MIRBuilder.buildCopy({DstReg}, {FrameAddr});
+      MIB.buildCopy({DstReg}, {FrameAddr});
     else {
       MFI.setReturnAddressIsTaken(true);
 
       if (STI.hasPAuth()) {
         Register TmpReg = MRI.createVirtualRegister(&AArch64::GPR64RegClass);
-        MIRBuilder.buildInstr(AArch64::LDRXui, {TmpReg}, {FrameAddr}).addImm(1);
-        MIRBuilder.buildInstr(AArch64::XPACI, {DstReg}, {TmpReg});
+        MIB.buildInstr(AArch64::LDRXui, {TmpReg}, {FrameAddr}).addImm(1);
+        MIB.buildInstr(AArch64::XPACI, {DstReg}, {TmpReg});
       } else {
-        MIRBuilder.buildInstr(AArch64::LDRXui, {Register(AArch64::LR)}, {FrameAddr}).addImm(1);
-        MIRBuilder.buildInstr(AArch64::XPACLRI);
-        MIRBuilder.buildCopy({DstReg}, {Register(AArch64::LR)});
+        MIB.buildInstr(AArch64::LDRXui, {Register(AArch64::LR)}, {FrameAddr})
+            .addImm(1);
+        MIB.buildInstr(AArch64::XPACLRI);
+        MIB.buildCopy({DstReg}, {Register(AArch64::LR)});
       }
     }
 
     I.eraseFromParent();
     return true;
   }
   }
   return false;