[X86][AVX] foldShuffleOfHorizOp - don't attempt to handle 256-bit X86ISD::VBROADCAST (PR49971)

[RKSimon]

Summary

NOTE: This is for the 12.x release branch ONLY

Minimal patch to avoid the issue encountered in PR49971 (it's already been dealt with in trunk through a larger refactor that can't be easily merged).

Bail for non-128-bit vector broadcasts of (F)HADD/SUB ops - the existing logic doesn't correctly deal with the fact that the broadcast will splat across the 128-bit lanes.

[wristow]

Clear simple, safe fix. And I've verified it fixes the problem we ran into downstream.
LGTM

[RKSimon]

@spatel @craig.topper Since this is a patch for a release branch please can we get a second approval?

[spatel]

LGTM

[RKSimon]

@tstellar Are you OK with merging this patch to 12.x (when the time comes) or do you need us to do anything else? Cheers, Simon.

[tstellar]

Can you file a bug for this?

[RKSimon]

In D101104#2716938, @tstellar wrote:

Can you file a bug for this?

https://bugs.llvm.org/show_bug.cgi?id=49971

[RKSimon]

@tstellar Committed this to release/12.x at rG25dd67ef882c327f9b6a3082cab6c33c9ff52d42

llvm/lib/Target/X86/X86ISelLowering.cpp

                        HorizOp.getValueType(), X, X);
   };
 
   // When the operands of a horizontal math op are identical, the low half of
   // the result is the same as the high half. If a target shuffle is also
   // replicating low and high halves (and without changing the type/length of
   // the vector), we don't need the shuffle.
   if (Opcode == X86ISD::MOVDDUP || Opcode == X86ISD::VBROADCAST) {
+    if (Opcode == X86ISD::VBROADCAST && !VT.is128BitVector())
+      return SDValue();
     if (HOp.getScalarValueSizeInBits() == 64 && HOp.getValueType() == VT) {
       // movddup (hadd X, X) --> hadd X, X
       // broadcast (extract_vec_elt (hadd X, X), 0) --> hadd X, X
       assert((HOp.getValueType() == MVT::v2f64 ||
               HOp.getValueType() == MVT::v4f64) && "Unexpected type for h-op");
       return updateHOp(HOp, DAG);
     }
     return SDValue();

llvm/test/CodeGen/X86/horizontal-shuffle-3.ll

 ; CHECK-NEXT:    vpshufd {{.*#+}} ymm0 = ymm0[0,2,1,3,4,6,5,7]
 ; CHECK-NEXT:    ret{{[l|q]}}
   %5 = tail call <8 x i32> @llvm.x86.avx2.phsub.d(<8 x i32> %0, <8 x i32> %1) #5
   %6 = tail call <8 x i32> @llvm.x86.avx2.phsub.d(<8 x i32> %2, <8 x i32> %3) #5
   %7 = shufflevector <8 x i32> %5, <8 x i32> %6, <8 x i32> <i32 2, i32 10, i32 3, i32 11, i32 6, i32 14, i32 7, i32 15>
   ret <8 x i32> %7
 }
 
+define <4 x double> @PR49971(<4 x double> %0) {
+; CHECK-LABEL: PR49971:
+; CHECK:       ## %bb.0:
+; CHECK-NEXT:    vhaddpd %xmm0, %xmm0, %xmm0
+; CHECK-NEXT:    vbroadcastsd %xmm0, %ymm0
+; CHECK-NEXT:    ret{{[l|q]}}
+  %2 = tail call <4 x double> @llvm.x86.avx.hadd.pd.256(<4 x double> %0, <4 x double> %0)
+  %3 = shufflevector <4 x double> %2, <4 x double> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 1>
+  ret <4 x double> %3
+}
+
 declare <8 x float> @llvm.x86.avx.hadd.ps.256(<8 x float>, <8 x float>)
 declare <8 x float> @llvm.x86.avx.hsub.ps.256(<8 x float>, <8 x float>)
 declare <4 x double> @llvm.x86.avx.hadd.pd.256(<4 x double>, <4 x double>)
 declare <4 x double> @llvm.x86.avx.hsub.pd.256(<4 x double>, <4 x double>)
 
 declare <16 x i16> @llvm.x86.avx2.phadd.w(<16 x i16>, <16 x i16>)
 declare <8 x i32> @llvm.x86.avx2.phadd.d(<8 x i32>, <8 x i32>)
 declare <16 x i16> @llvm.x86.avx2.phsub.w(<16 x i16>, <16 x i16>)
 declare <8 x i32> @llvm.x86.avx2.phsub.d(<8 x i32>, <8 x i32>)
 
 declare <32 x i8> @llvm.x86.avx2.packsswb(<16 x i16>, <16 x i16>)
 declare <16 x i16> @llvm.x86.avx2.packssdw(<8 x i32>, <8 x i32>)
 declare <32 x i8> @llvm.x86.avx2.packuswb(<16 x i16>, <16 x i16>)
 declare <16 x i16> @llvm.x86.avx2.packusdw(<8 x i32>, <8 x i32>)