AArch64: support mixed-size vector fp <-> int conversions in GlobalISel.

[t.p.northover]

Summary

Fairly simple, just a few extra patterns to handle the extra instructions.

[paquette]

LGTM

[arsenm]

llvm/test/CodeGen/AArch64/GlobalISel/select-fp-casts.mir

644–646

Should drop the registers section and use the modern ":regbank" syntax

[aemerson]

If these patterns are intended to fire only when using GlobalISel, then we have a separate file for those, AArch64InstrGISel.td.

llvm/utils/TableGen/GlobalISelEmitter.cpp

4467

debug line

[t.p.northover]

Thanks, committed as 2e72f6b5d with Amara & Matt's comments addressed (and the stray commented dump removed).

llvm/lib/Target/AArch64/AArch64InstrInfo.td

def : InstAlias<"uxtl2.4s $dst, $src1",
                 (USHLLv8i16_shift V128:$dst, V128:$src1, 0)>;
 def : InstAlias<"uxtl2 $dst.4s, $src1.8h",
                 (USHLLv8i16_shift V128:$dst, V128:$src1, 0)>;
 def : InstAlias<"uxtl2.2d $dst, $src1",
                 (USHLLv4i32_shift V128:$dst, V128:$src1, 0)>;
 def : InstAlias<"uxtl2 $dst.2d, $src1.4s",
                 (USHLLv4i32_shift V128:$dst, V128:$src1, 0)>;
 
+let Predicates = [HasNEON] in {
+  def : Pat<(v2f64 (sint_to_fp v2i32:$src)),
+            (SCVTFv2f64 (SSHLLv2i32_shift V64:$src, 0))>;
+  def : Pat<(v2f64 (uint_to_fp v2i32:$src)),
+            (UCVTFv2f64 (USHLLv2i32_shift V64:$src, 0))>;
+  def : Pat<(v2f32 (sint_to_fp v2i64:$src)),
+            (FCVTNv2i32 (SCVTFv2f64 V128:$src))>;
+  def : Pat<(v2f32 (uint_to_fp v2i64:$src)),
+            (FCVTNv2i32 (UCVTFv2f64 V128:$src))>;
+
+  def : Pat<(v2i64 (fp_to_sint v2f32:$src)),
+            (FCVTZSv2f64 (FCVTLv2i32 V64:$src))>;
+  def : Pat<(v2i64 (fp_to_uint v2f32:$src)),
+            (FCVTZUv2f64 (FCVTLv2i32 V64:$src))>;
+  def : Pat<(v2i32 (fp_to_sint v2f64:$src)),
+            (XTNv2i32 (FCVTZSv2f64 V128:$src))>;
+  def : Pat<(v2i32 (fp_to_uint v2f64:$src)),
+            (XTNv2i32 (FCVTZUv2f64 V128:$src))>;
+
+}
+
 // If an integer is about to be converted to a floating point value,
 // just load it on the floating point unit.
 // These patterns are more complex because floating point loads do not
 // support sign extension.
 // The sign extension has to be explicitly added and is only supported for
 // one step: byte-to-half, half-to-word, word-to-doubleword.
 // SCVTF GPR -> FPR is 9 cycles.
 // SCVTF FPR -> FPR is 4 cyclces.

llvm/test/CodeGen/AArch64/GlobalISel/select-fp-casts.mir

registers:
   - { id: 0, class: fpr }
   - { id: 1, class: fpr }
 
 body:             |
   bb.0:
     liveins: $d0
     ; CHECK-LABEL: name: fptrunc_v4s16_v4s32_fpr
     ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
-    ; CHECK: [[FCVTNv4i16:%[0-9]+]]:fpr64 = FCVTNv4i16 [[COPY]]
-    ; CHECK: $d0 = COPY [[FCVTNv4i16]]
+    ; CHECK: [[FCVTNv4i16_:%[0-9]+]]:fpr64 = FCVTNv4i16 [[COPY]]
+    ; CHECK: $d0 = COPY [[FCVTNv4i16_]]
     %0(<4 x s32>) = COPY $q0
     %1(<4 x s16>) = G_FPTRUNC %0
     $d0 = COPY %1(<4 x s16>)
 ...
 
 ---
 name:            fptrunc_v2s32_v2s64_fpr
 legalized:       true
 regBankSelected: true
 
 registers:
   - { id: 0, class: fpr }
   - { id: 1, class: fpr }
 
 body:             |
   bb.0:
     liveins: $q0
     ; CHECK-LABEL: name: fptrunc_v2s32_v2s64_fpr
     ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
-    ; CHECK: [[FCVTNv2i32:%[0-9]+]]:fpr64 = FCVTNv2i32 [[COPY]]
-    ; CHECK: $d0 = COPY [[FCVTNv2i32]]
+    ; CHECK: [[FCVTNv2i32_:%[0-9]+]]:fpr64 = FCVTNv2i32 [[COPY]]
+    ; CHECK: $d0 = COPY [[FCVTNv2i32_]]
     %0(<2 x s64>) = COPY $q0
     %1(<2 x s32>) = G_FPTRUNC %0
     $d0 = COPY %1(<2 x s32>)
 ...
 
 ---
 name:            fpext_s32_s16_fpr
 legalized:       true
registers:
   - { id: 0, class: fpr }
   - { id: 1, class: fpr }
 
 body:             |
   bb.0:
     liveins: $d0
     ; CHECK-LABEL: name: fpext_v4s32_v4s16_fpr
     ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
-    ; CHECK: [[FCVTLv4i16:%[0-9]+]]:fpr128 = FCVTLv4i16 [[COPY]]
-    ; CHECK: $q0 = COPY [[FCVTLv4i16]]
+    ; CHECK: [[FCVTLv4i16_:%[0-9]+]]:fpr128 = FCVTLv4i16 [[COPY]]
+    ; CHECK: $q0 = COPY [[FCVTLv4i16_]]
     %0(<4 x s16>) = COPY $d0
     %1(<4 x s32>) = G_FPEXT %0
     $q0 = COPY %1(<4 x s32>)
 ...
 
 ---
 name:            fpext_v2s64_v2s32_fpr
 legalized:       true
 regBankSelected: true
 
 registers:
   - { id: 0, class: fpr }
   - { id: 1, class: fpr }
 
 body:             |
   bb.0:
     liveins: $d0
     ; CHECK-LABEL: name: fpext_v2s64_v2s32_fpr
     ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
-    ; CHECK: [[FCVTLv2i32:%[0-9]+]]:fpr128 = FCVTLv2i32 [[COPY]]
-    ; CHECK: $q0 = COPY [[FCVTLv2i32]]
+    ; CHECK: [[FCVTLv2i32_:%[0-9]+]]:fpr128 = FCVTLv2i32 [[COPY]]
+    ; CHECK: $q0 = COPY [[FCVTLv2i32_]]
     %0(<2 x s32>) = COPY $d0
     %1(<2 x s64>) = G_FPEXT %0
     $q0 = COPY %1(<2 x s64>)
 ...
 
 ---
 name:            sitofp_s32_s32_fpr_gpr
 legalized:       true
registers:
   - { id: 1, class: fpr }
 
 body:             |
   bb.0:
     liveins: $s0
 
     ; CHECK-LABEL: name: sitofp_s32_s32_fpr_fpr
     ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
-    ; CHECK: [[SCVTFv1i32:%[0-9]+]]:fpr32 = SCVTFv1i32 [[COPY]]
-    ; CHECK: $s0 = COPY [[SCVTFv1i32]]
+    ; CHECK: [[SCVTFv1i32_:%[0-9]+]]:fpr32 = SCVTFv1i32 [[COPY]]
+    ; CHECK: $s0 = COPY [[SCVTFv1i32_]]
     %0(s32) = COPY $s0
     %1(s32) = G_SITOFP %0
     $s0 = COPY %1(s32)
 ...
 
 ---
 name:            uitofp_s32_s32_fpr_fpr
 legalized:       true
 regBankSelected: true
 
 registers:
   - { id: 0, class: fpr }
   - { id: 1, class: fpr }
 
 body:             |
   bb.0:
     liveins: $s0
 
     ; CHECK-LABEL: name: uitofp_s32_s32_fpr_fpr
     ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
-    ; CHECK: [[UCVTFv1i32:%[0-9]+]]:fpr32 = UCVTFv1i32 [[COPY]]
-    ; CHECK: $s0 = COPY [[UCVTFv1i32]]
+    ; CHECK: [[UCVTFv1i32_:%[0-9]+]]:fpr32 = UCVTFv1i32 [[COPY]]
+    ; CHECK: $s0 = COPY [[UCVTFv1i32_]]
     %0(s32) = COPY $s0
     %1(s32) = G_UITOFP %0
     $s0 = COPY %1(s32)
 ...
 
 ---
 name:            sitofp_s32_s64_fpr
 legalized:       true

 registers:
   - { id: 0, class: fpr }
   - { id: 1, class: fpr }
 
 body:             |
   bb.0:
     liveins: $s0
 
-    ; CHECK-LABEL: name: sitofp_s64_s32_fpr
+    ; CHECK-LABEL: name: sitofp_s64_s32_fpr_both
     ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
-    ; CHECK: [[COPY2:%[0-9]+]]:gpr32 = COPY [[COPY]]
-    ; CHECK: [[SCVTFUWDri:%[0-9]+]]:fpr64 = SCVTFUWDri [[COPY2]]
+    ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]]
+    ; CHECK: [[SCVTFUWDri:%[0-9]+]]:fpr64 = SCVTFUWDri [[COPY1]]
     ; CHECK: $d0 = COPY [[SCVTFUWDri]]
     %0(s32) = COPY $s0
     %1(s64) = G_SITOFP %0
     $d0 = COPY %1(s64)
 ...
 
 ---
 name:            sitofp_s64_s64_fpr
bb.0:
     ; CHECK-LABEL: name: fptoui_s64_s64_gpr
     ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
     ; CHECK: [[FCVTZUUXDr:%[0-9]+]]:gpr64 = FCVTZUUXDr [[COPY]]
     ; CHECK: $x0 = COPY [[FCVTZUUXDr]]
     %0(s64) = COPY $d0
     %1(s64) = G_FPTOUI %0
     $x0 = COPY %1(s64)
 ...
+
+---
+name:            sitofp_v2s64_v2s32
+legalized:       true
+regBankSelected: true
+
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+
+body:             |
+  bb.0:
+    liveins: $d0
+
+    ; CHECK-LABEL: name: sitofp_v2s64_v2s32
+    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; CHECK: [[SSHLLv2i32_shift:%[0-9]+]]:fpr128 = SSHLLv2i32_shift [[COPY]], 0
+    ; CHECK: [[SCVTFv2f64_:%[0-9]+]]:fpr128 = SCVTFv2f64 [[SSHLLv2i32_shift]]
+    ; CHECK: $q0 = COPY [[SCVTFv2f64_]]
+    %0(<2 x s32>) = COPY $d0
+    %1(<2 x s64>) = G_SITOFP %0
+    $q0 = COPY %1(<2 x s64>)
+...
+
+---
+name:            uitofp_v2s64_v2s32
+legalized:       true
+regBankSelected: true
+
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+
+body:             |
+  bb.0:
+    liveins: $d0
+
+    ; CHECK-LABEL: name: uitofp_v2s64_v2s32
+    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; CHECK: [[USHLLv2i32_shift:%[0-9]+]]:fpr128 = USHLLv2i32_shift [[COPY]], 0
+    ; CHECK: [[UCVTFv2f64_:%[0-9]+]]:fpr128 = UCVTFv2f64 [[USHLLv2i32_shift]]
+    ; CHECK: $q0 = COPY [[UCVTFv2f64_]]
+    %0(<2 x s32>) = COPY $d0
+    %1(<2 x s64>) = G_UITOFP %0
+    $q0 = COPY %1(<2 x s64>)
+...
+
+---
+name:            sitofp_v2s32_v2s64
+legalized:       true
+regBankSelected: true
+
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+
+body:             |
+  bb.0:
+    liveins: $q0
+
+    ; CHECK-LABEL: name: sitofp_v2s32_v2s64
+    ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; CHECK: [[SCVTFv2f64_:%[0-9]+]]:fpr128 = SCVTFv2f64 [[COPY]]
+    ; CHECK: [[FCVTNv2i32_:%[0-9]+]]:fpr64 = FCVTNv2i32 [[SCVTFv2f64_]]
+    ; CHECK: $d0 = COPY [[FCVTNv2i32_]]
+    %0(<2 x s64>) = COPY $q0
+    %1(<2 x s32>) = G_SITOFP %0
+    $d0 = COPY %1(<2 x s32>)
+...
+
+---
+name:            uitofp_v2s32_v2s64
+legalized:       true
+regBankSelected: true
+
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+
+body:             |
+  bb.0:
+    liveins: $q0
+
+    ; CHECK-LABEL: name: uitofp_v2s32_v2s64
+    ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; CHECK: [[UCVTFv2f64_:%[0-9]+]]:fpr128 = UCVTFv2f64 [[COPY]]
+    ; CHECK: [[FCVTNv2i32_:%[0-9]+]]:fpr64 = FCVTNv2i32 [[UCVTFv2f64_]]
+    ; CHECK: $d0 = COPY [[FCVTNv2i32_]]
+    %0(<2 x s64>) = COPY $q0
+    %1(<2 x s32>) = G_UITOFP %0
+    $d0 = COPY %1(<2 x s32>)
+...
+
+---
+name:            fptosi_v2s64_v2s32
+legalized:       true
+regBankSelected: true
+
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+
+body:             |
+  bb.0:
+    liveins: $d0
+
+    ; CHECK-LABEL: name: fptosi_v2s64_v2s32
+    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; CHECK: [[FCVTLv2i32_:%[0-9]+]]:fpr128 = FCVTLv2i32 [[COPY]]
+    ; CHECK: [[FCVTZSv2f64_:%[0-9]+]]:fpr128 = FCVTZSv2f64 [[FCVTLv2i32_]]
+    ; CHECK: $q0 = COPY [[FCVTZSv2f64_]]
+    %0(<2 x s32>) = COPY $d0
+    %1(<2 x s64>) = G_FPTOSI %0
+    $q0 = COPY %1(<2 x s64>)
+...
+
+---
+name:            fptoui_v2s64_v2s32
+legalized:       true
+regBankSelected: true
+
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+
+body:             |
+  bb.0:
+    liveins: $d0
+
+    ; CHECK-LABEL: name: fptoui_v2s64_v2s32
+    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; CHECK: [[FCVTLv2i32_:%[0-9]+]]:fpr128 = FCVTLv2i32 [[COPY]]
+    ; CHECK: [[FCVTZUv2f64_:%[0-9]+]]:fpr128 = FCVTZUv2f64 [[FCVTLv2i32_]]
+    ; CHECK: $q0 = COPY [[FCVTZUv2f64_]]
+    %0(<2 x s32>) = COPY $d0
+    %1(<2 x s64>) = G_FPTOUI %0
+    $q0 = COPY %1(<2 x s64>)
+...
+
+---
+name:            fptosi_v2s32_v2s64
+legalized:       true
+regBankSelected: true
+
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+
+body:             |
+  bb.0:
+    liveins: $q0
+
+    ; CHECK-LABEL: name: fptosi_v2s32_v2s64
+    ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; CHECK: [[FCVTZSv2f64_:%[0-9]+]]:fpr128 = FCVTZSv2f64 [[COPY]]
+    ; CHECK: [[XTNv2i32_:%[0-9]+]]:fpr64 = XTNv2i32 [[FCVTZSv2f64_]]
+    ; CHECK: $d0 = COPY [[XTNv2i32_]]
+    %0(<2 x s64>) = COPY $q0
+    %1(<2 x s32>) = G_FPTOSI %0
+    $d0 = COPY %1(<2 x s32>)
+...
+
+---
+name:            fptoui_v2s32_v2s64
+legalized:       true
+regBankSelected: true
+
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+
+body:             |
+  bb.0:
+    liveins: $q0
+
+    ; CHECK-LABEL: name: fptoui_v2s32_v2s64
+    ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; CHECK: [[FCVTZUv2f64_:%[0-9]+]]:fpr128 = FCVTZUv2f64 [[COPY]]
+    ; CHECK: [[XTNv2i32_:%[0-9]+]]:fpr64 = XTNv2i32 [[FCVTZUv2f64_]]
+    ; CHECK: $d0 = COPY [[XTNv2i32_]]
+    %0(<2 x s64>) = COPY $q0
+    %1(<2 x s32>) = G_FPTOUI %0
+    $d0 = COPY %1(<2 x s32>)
+...

llvm/utils/TableGen/GlobalISelEmitter.cpp

if (ChildRec->isSubClassOf("ComplexPattern")) {
           *ComplexPattern->second, DstChild->getName(),
           OM.getAllocatedTemporariesBaseID());
       return InsertPt;
     }
 
     return failedImport(
         "Dst pattern child def is an unsupported tablegen class");
   }
-
+  //DstChild->dump();
   return failedImport("Dst pattern child is an unsupported kind");
 }
 
 Expected<BuildMIAction &> GlobalISelEmitter::createAndImportInstructionRenderer(
     RuleMatcher &M, InstructionMatcher &InsnMatcher, const TreePatternNode *Src,
     const TreePatternNode *Dst) {
   auto InsertPtOrError = createInstructionRenderer(M.actions_end(), M, Dst);
   if (auto Error = InsertPtOrError.takeError())