This is an archive of the discontinued LLVM Phabricator instance.

Differential D100642

[AMDGPU][MC] Corrected parsing of carry in/out operands in VOP3
ClosedPublic

Authored by dp on Apr 16 2021, 5:12 AM.

Details

Reviewers
rampitec
Commits
rGbcc29e0fcf24: [AMDGPU][MC] Corrected parsing of carry in/out operands in VOP3
Summary

Disabled constants as carry in/out operands. See bug 48711.

Diff Detail

Event Timeline

dp created this revision.Apr 16 2021, 5:12 AM
Herald added subscribers: kerbowa, hiraditya, t-tye and 7 others. · View Herald TranscriptApr 16 2021, 5:12 AM
dp requested review of this revision.Apr 16 2021, 5:12 AM
Herald added a project: Restricted Project. · View Herald TranscriptApr 16 2021, 5:12 AM
Herald added subscribers: llvm-commits, wdng. · View Herald Transcript
Harbormaster completed remote builds in B99145: Diff 338068.Apr 16 2021, 5:48 AM
dp updated this revision to Diff 338087.Apr 16 2021, 6:38 AM

Updated to silence the linter.

Harbormaster completed remote builds in B99157: Diff 338087.Apr 16 2021, 7:19 AM
rampitec accepted this revision.Apr 16 2021, 9:49 AM
This revision is now accepted and ready to land.Apr 16 2021, 9:49 AM
Closed by commit rGbcc29e0fcf24: [AMDGPU][MC] Corrected parsing of carry in/out operands in VOP3 (authored by dp). · Explain WhyApr 19 2021, 3:43 AM
This revision was automatically updated to reflect the committed changes.
dp added a commit: rGbcc29e0fcf24: [AMDGPU][MC] Corrected parsing of carry in/out operands in VOP3.

Revision Contents

PathSize
llvm/
lib/
Target/
AMDGPU/
AsmParser/
5 lines
test/
MC/
AMDGPU/
24 lines
12 lines

Diff 338087

llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 1,916 Lines • ▼ Show 20 Linesbool AMDGPUOperand::isSDWAInt16Operand() const {
return isSDWAOperand(MVT::i16); return isSDWAOperand(MVT::i16);
} }
bool AMDGPUOperand::isSDWAInt32Operand() const { bool AMDGPUOperand::isSDWAInt32Operand() const {
return isSDWAOperand(MVT::i32); return isSDWAOperand(MVT::i32);
} }
bool AMDGPUOperand::isBoolReg() const { bool AMDGPUOperand::isBoolReg() const {
return (AsmParser->getFeatureBits()[AMDGPU::FeatureWavefrontSize64] && isSCSrcB64()) || auto FB = AsmParser->getFeatureBits();
(AsmParser->getFeatureBits()[AMDGPU::FeatureWavefrontSize32] && isSCSrcB32()); return isReg() && ((FB[AMDGPU::FeatureWavefrontSize64] && isSCSrcB64()) ||
(FB[AMDGPU::FeatureWavefrontSize32] && isSCSrcB32()));
} }
uint64_t AMDGPUOperand::applyInputFPModifiers(uint64_t Val, unsigned Size) const uint64_t AMDGPUOperand::applyInputFPModifiers(uint64_t Val, unsigned Size) const
{ {
assert(isImmTy(ImmTyNone) && Imm.Mods.hasFPModifiers()); assert(isImmTy(ImmTyNone) && Imm.Mods.hasFPModifiers());
assert(Size == 2 || Size == 4 || Size == 8); assert(Size == 2 || Size == 4 || Size == 8);
const uint64_t FpSignMask = (1ULL << (Size * 8 - 1)); const uint64_t FpSignMask = (1ULL << (Size * 8 - 1));
▲ Show 20 Lines • Show All 6,315 Lines • Show Last 20 Lines

llvm/test/MC/AMDGPU/gfx10_asm_err.s

Show First 20 Lines • Show All 267 Lines • ▼ Show 20 Lines
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// DPP8. // DPP8.
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
v_mov_b32_dpp v5, v1 dpp8:[0,1,2,3,4,5,6,7] v_mov_b32_dpp v5, v1 dpp8:[0,1,2,3,4,5,6,7]
// GFX6-7: error: dpp variant of this instruction is not supported // GFX6-7: error: dpp variant of this instruction is not supported
// GFX8-9: error: not a valid operand // GFX8-9: error: not a valid operand
//===----------------------------------------------------------------------===//
// VOP2 E64.
//===----------------------------------------------------------------------===//
v_add_co_ci_u32 v5, 0, v1, v2, vcc
// GFX6-7: error: instruction not supported on this GPU
// GFX8-9: error: instruction not supported on this GPU
// GFX10: error: invalid operand for instruction
v_add_co_ci_u32 v5, vcc, v1, v2, 0
// GFX6-7: error: instruction not supported on this GPU
// GFX8-9: error: instruction not supported on this GPU
// GFX10: error: invalid operand for instruction
v_add_co_ci_u32 v5, 0, v1, v2, vcc_lo
// GFX6-7: error: instruction not supported on this GPU
// GFX8-9: error: instruction not supported on this GPU
// GFX10: error: invalid operand for instruction
v_add_co_ci_u32 v5, vcc_lo, v1, v2, 0
// GFX6-7: error: instruction not supported on this GPU
// GFX8-9: error: instruction not supported on this GPU
// GFX10: error: invalid operand for instruction

llvm/test/MC/AMDGPU/vop2-err.s

Show First 20 Lines • Show All 50 Lines • ▼ Show 20 Lines
// CHECK: error: invalid operand for instruction // CHECK: error: invalid operand for instruction
v_addc_u32_e32 v1, vcc, v2, v3, s0 v_addc_u32_e32 v1, vcc, v2, v3, s0
// CHECK: error: invalid operand for instruction // CHECK: error: invalid operand for instruction
v_addc_u32_e32 v1, -1, v2, v3, s0 v_addc_u32_e32 v1, -1, v2, v3, s0
// CHECK: error: invalid operand for instruction // CHECK: error: invalid operand for instruction
v_addc_u32 v1, -1, v2, v3, vcc
// CHECK: error: invalid operand for instruction
v_addc_u32 v1, vcc, v2, v3, 0
// CHECK: error: invalid operand for instruction
v_addc_u32_e64 v1, s[0:1], v2, v3, 123 v_addc_u32_e64 v1, s[0:1], v2, v3, 123
// CHECK: error: invalid operand for instruction // CHECK: error: invalid operand for instruction
v_addc_u32_e64 v1, 0, v2, v3, s[0:1]
// CHECK: error: invalid operand for instruction
v_addc_u32_e64 v1, s[0:1], v2, v3, 0
// CHECK: error: invalid operand for instruction
v_addc_u32 v1, s[0:1], v2, v3, 123 v_addc_u32 v1, s[0:1], v2, v3, 123
// CHECK: error: invalid operand for instruction // CHECK: error: invalid operand for instruction
// TODO: Constant bus restrictions // TODO: Constant bus restrictions