[MIPS][lldb-server] Add 32-bit register context and read/write FP registers on mips64

[slthakur]

Summary

• Added support for read/write FP registers in FR1 mode.
• Added 32 bit register context for mips32.

[tberghammer]

NativeRegisterContextLinux_mips.cpp and NativeRegisterContextLinux_mips64.cpp are both enabled at the same time (when mips is defined) what will cause a conflict because both implements NativeRegisterContextLinux::CreateHostNativeRegisterContextLinux for creating the appropriate register context. I don't know what is the relationship between mips and mips64 (if they should exist next to each outher as i386 and x86_64 or they are completely different ones as arm and aarch64) but you have to do something to always create the right context and have exactly one CreateHostNativeRegisterContextLinux implementation when mips is defined.

Please upload a revision with full context and where the base revision already contains D9935 to make it easier to review.

source/Core/RegisterValue.cpp

88–111 ↗

(On Diff #26503)

We shouldn't have architecture specific code in RegisterValue.

If I understand it correctly your problem is that both single and double precision floats can be stored in the same register and you want to display them correctly. I suggest to use alias registers for this issue (eg.: f1 -> hex, flt1 -> float, dbl1 -> double) in the register context so it will work in an architecture independent way. A similar solution is used on i386 and on x86_64 for handling the integer registers with the only difference that in that case you can address both part of the bigger register.

source/Plugins/Process/Utility/RegisterContextLinux_mips.cpp

112–113

These registers should have uint encoding and hex format

[clayborg]

source/Core/RegisterValue.cpp

88–111 ↗

(On Diff #26503)

RegisterValue.cpp shouldn't have arch specific stuff. Like tberghammer said, just make registers that have different names if needed. But you really shouldn't have to do this as you can view registers using a different format:

(lldb) register read s31
s31 = 2.125
(lldb) register read --format hex s31
S31 = 0x40080000

This would display a float or double register as hex. If you need to show parts of a register you do make different registers. Registers through the GDB remote protocol with qRegisterInfo or the target.xml, can claim they are part of another register (RegisterInfo.value_regs). So if you have a 'f0' register for mips that is a double you can define a register that is "f0" whose size is 64 bits, and then make a "f0_low" (or some other better name) whose values_regs specifies the register number of "f0". When this register is read, it will then read the "f0" register and then take part of that value based off of the offset and size in the RegisterInfo structure.

[slthakur]

Hi @clayborg, @tberghammer,

NativeRegisterContextLinux_mips.cpp and NativeRegisterContextLinux_mips64.cpp are both enabled at the same time (when mips is defined) what will cause a conflict because both implements NativeRegisterContextLinux::CreateHostNativeRegisterContextLinux for creating the appropriate register context.

I will remove the NativeRegisterContextLinux_mips.cpp. NativeRegisterContextLinux_mips64.cpp will work for both mips and mips64.

We shouldn't have architecture specific code in RegisterValue

As @clayborg suggested, we can let the user use the --format option for printing float or double or hex values for floating point registers for now.

I will updated this patch with full context and address all review comments.

Thanks.

[slthakur]

• Shifted code for defining g_register_infos_mips* to RegisterInfos_mips* classes.
• Shifted lldb internals codes for registers to lldb-mips64-register-enums.h.
• Addressed review comments by @tberghammer and @clayborg.

[tberghammer]

The general concept looks good.
For the mips specific part I don't have enough knowledge to verify, but I noticed one serious issue (see inline comment).

source/Plugins/Process/Linux/NativeRegisterContextLinux_mips64.cpp

478–498

• The error message says "failed to read floating point register" after a WriteFPR() call what seems to be wrong.
• You do a write before setting the value of the register from the argument.

Based on the two observation I am not sure if the general concept in the function is correct and those are just 2 typos or if the content of the function is accidentally swapped with the content of a ReadRegister function

[slthakur]

Corrected WriteFPR function.

[slthakur]

Corrected another typo in file name discription in RegisterInfo_mips* files.

[tberghammer]

Looks good, but see 2 minor comments inline

source/Core/ArchSpec.cpp

1161

You are missing a break here (or if it is intentional then please add a comment)

1175

You are missing a break here (or if it is intentional then please add a comment)

[slthakur]

Addressed review comments

[clayborg]

Looks good.

include/lldb/Core/ArchSpec.h

enum Core
 
         kCore_x86_64_first  = eCore_x86_64_x86_64,
         kCore_x86_64_last   = eCore_x86_64_x86_64h,
 
         kCore_hexagon_first  = eCore_hexagon_generic,
         kCore_hexagon_last   = eCore_hexagon_hexagonv5,
 
         kCore_kalimba_first = eCore_kalimba3,
-        kCore_kalimba_last = eCore_kalimba5
+        kCore_kalimba_last = eCore_kalimba5,
+
+        kCore_mips32_first  = eCore_mips32,
+        kCore_mips32_last   = eCore_mips32r6,
+
+        kCore_mips32el_first  = eCore_mips32el,
+        kCore_mips32el_last   = eCore_mips32r6el,
+
+        kCore_mips64_first  = eCore_mips64,
+        kCore_mips64_last   = eCore_mips64r6,
+
+        kCore_mips64el_first  = eCore_mips64el,
+        kCore_mips64el_last   = eCore_mips64r6el
     };
 
     typedef void (* StopInfoOverrideCallbackType)(lldb_private::Thread &thread);
 
     //------------------------------------------------------------------
     /// Default constructor.
     ///
     /// Default constructor that initializes the object with invalid

source/Core/ArchSpec.cpp

static const CoreDefinition g_core_definitions[] =
     { eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb  , ArchSpec::eCore_thumbv7k        , "thumbv7k"  },
     { eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb  , ArchSpec::eCore_thumbv7m        , "thumbv7m"  },
     { eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb  , ArchSpec::eCore_thumbv7em       , "thumbv7em" },
     { eByteOrderLittle, 8, 4, 4, llvm::Triple::aarch64, ArchSpec::eCore_arm_arm64       , "arm64"     },
     { eByteOrderLittle, 8, 4, 4, llvm::Triple::aarch64, ArchSpec::eCore_arm_armv8       , "armv8"     },
     { eByteOrderLittle, 8, 4, 4, llvm::Triple::aarch64, ArchSpec::eCore_arm_aarch64     , "aarch64"   },
 
     // mips32, mips32r2, mips32r3, mips32r5, mips32r6
-    { eByteOrderBig   , 4, 4, 4, llvm::Triple::mips  , ArchSpec::eCore_mips32         , "mips32"      },
-    { eByteOrderBig   , 4, 4, 4, llvm::Triple::mips  , ArchSpec::eCore_mips32r2       , "mips32r2"    },
-    { eByteOrderBig   , 4, 4, 4, llvm::Triple::mips  , ArchSpec::eCore_mips32r3       , "mips32r3"    },
-    { eByteOrderBig   , 4, 4, 4, llvm::Triple::mips  , ArchSpec::eCore_mips32r5       , "mips32r5"    },
-    { eByteOrderBig   , 4, 4, 4, llvm::Triple::mips  , ArchSpec::eCore_mips32r6       , "mips32r6"    },
-    { eByteOrderLittle, 4, 4, 4, llvm::Triple::mipsel, ArchSpec::eCore_mips32el       , "mips32el"    },
-    { eByteOrderLittle, 4, 4, 4, llvm::Triple::mipsel, ArchSpec::eCore_mips32r2el     , "mips32r2el"  },
-    { eByteOrderLittle, 4, 4, 4, llvm::Triple::mipsel, ArchSpec::eCore_mips32r3el     , "mips32r3el"  },
-    { eByteOrderLittle, 4, 4, 4, llvm::Triple::mipsel, ArchSpec::eCore_mips32r5el     , "mips32r5el"  },
-    { eByteOrderLittle, 4, 4, 4, llvm::Triple::mipsel, ArchSpec::eCore_mips32r6el     , "mips32r6el"  },
+    { eByteOrderBig   , 4, 4, 4, llvm::Triple::mips  , ArchSpec::eCore_mips32         , "mips"      },
+    { eByteOrderBig   , 4, 4, 4, llvm::Triple::mips  , ArchSpec::eCore_mips32r2       , "mipsr2"    },
+    { eByteOrderBig   , 4, 4, 4, llvm::Triple::mips  , ArchSpec::eCore_mips32r3       , "mipsr3"    },
+    { eByteOrderBig   , 4, 4, 4, llvm::Triple::mips  , ArchSpec::eCore_mips32r5       , "mipsr5"    },
+    { eByteOrderBig   , 4, 4, 4, llvm::Triple::mips  , ArchSpec::eCore_mips32r6       , "mipsr6"    },
+    { eByteOrderLittle, 4, 4, 4, llvm::Triple::mipsel, ArchSpec::eCore_mips32el       , "mipsel"    },
+    { eByteOrderLittle, 4, 4, 4, llvm::Triple::mipsel, ArchSpec::eCore_mips32r2el     , "mipsr2el"  },
+    { eByteOrderLittle, 4, 4, 4, llvm::Triple::mipsel, ArchSpec::eCore_mips32r3el     , "mipsr3el"  },
+    { eByteOrderLittle, 4, 4, 4, llvm::Triple::mipsel, ArchSpec::eCore_mips32r5el     , "mipsr5el"  },
+    { eByteOrderLittle, 4, 4, 4, llvm::Triple::mipsel, ArchSpec::eCore_mips32r6el     , "mipsr6el"  },
     
     // mips64, mips64r2, mips64r3, mips64r5, mips64r6
     { eByteOrderBig   , 8, 4, 4, llvm::Triple::mips64  , ArchSpec::eCore_mips64         , "mips64"      },
     { eByteOrderBig   , 8, 4, 4, llvm::Triple::mips64  , ArchSpec::eCore_mips64r2       , "mips64r2"    },
     { eByteOrderBig   , 8, 4, 4, llvm::Triple::mips64  , ArchSpec::eCore_mips64r3       , "mips64r3"    },
     { eByteOrderBig   , 8, 4, 4, llvm::Triple::mips64  , ArchSpec::eCore_mips64r5       , "mips64r5"    },
     { eByteOrderBig   , 8, 4, 4, llvm::Triple::mips64  , ArchSpec::eCore_mips64r6       , "mips64r6"    },
     { eByteOrderLittle, 8, 4, 4, llvm::Triple::mips64el, ArchSpec::eCore_mips64el       , "mips64el"    },
case ArchSpec::eCore_arm_arm64:
             if (core2 == ArchSpec::eCore_arm_aarch64)
                 return true;
             if (core2 == ArchSpec::eCore_arm_armv8)
                 return true;
             try_inverse = false;
         }
         break;
 
+    case ArchSpec::eCore_mips64:
+    case ArchSpec::eCore_mips64r2:
+    case ArchSpec::eCore_mips64r3:
+    case ArchSpec::eCore_mips64r5:
+    case ArchSpec::eCore_mips64r6:
+        if (!enforce_exact_match)
+        {
+            if (core2 >= ArchSpec::kCore_mips32_first && core2 <= (core1 - 10))
+                return true;
+            if (core2 >= ArchSpec::kCore_mips64_first && core2 <= (core1 - 1))
+                return true;
+            try_inverse = false;
+        }
+        break;
+    
+    case ArchSpec::eCore_mips64el:
+    case ArchSpec::eCore_mips64r2el:
+    case ArchSpec::eCore_mips64r3el:
+    case ArchSpec::eCore_mips64r5el:
+    case ArchSpec::eCore_mips64r6el:
+        if (!enforce_exact_match)
+        {
+            if (core2 >= ArchSpec::kCore_mips32el_first && core2 <= (core1 - 10))
+                return true;
+            if (core2 >= ArchSpec::kCore_mips64el_first && core2 <= (core1 - 1))
+                return true;
+            try_inverse = false;
+        }
+        break;
+
     default:
         break;
     }
     if (try_inverse)
         return cores_match (core2, core1, false, enforce_exact_match);
     return false;
 }
 

source/Plugins/Platform/Linux/PlatformLinux.cpp

else
         {
             case 0: triple.setArchName("x86_64"); break;
             case 1: triple.setArchName("i386"); break;
             case 2: triple.setArchName("arm"); break;
             case 3: triple.setArchName("aarch64"); break;
             case 4: triple.setArchName("mips64"); break;
             case 5: triple.setArchName("hexagon"); break;
             case 6: triple.setArchName("mips"); break;
+            case 7: triple.setArchName("mips64el"); break;
+            case 8: triple.setArchName("mipsel"); break;
             default: return false;
         }
         // Leave the vendor as "llvm::Triple:UnknownVendor" and don't specify the vendor by
         // calling triple.SetVendorName("unknown") so that it is a "unspecified unknown".
         // This means when someone calls triple.GetVendorName() it will return an empty string
         // which indicates that the vendor can be set when two architectures are merged
 
         // Now set the triple into "arch" and return true

source/Plugins/Process/Linux/NativeProcessLinux.cpp

switch (m_arch.GetMachine ())
 
         case llvm::Triple::x86:
         case llvm::Triple::x86_64:
             actual_opcode_size = static_cast<uint32_t> (sizeof(g_i386_opcode));
             return Error ();
 
         case llvm::Triple::mips64:
         case llvm::Triple::mips64el:
+        case llvm::Triple::mips:
+        case llvm::Triple::mipsel:
             actual_opcode_size = static_cast<uint32_t> (sizeof(g_mips64_opcode));
             return Error ();
         
         default:
             assert(false && "CPU type not supported!");
             return Error ("CPU type not supported");
     }
 }
case llvm::Triple::arm:
         }
 
     case llvm::Triple::x86:
     case llvm::Triple::x86_64:
         trap_opcode_bytes = g_i386_opcode;
         actual_opcode_size = sizeof(g_i386_opcode);
         return Error ();
 
+    case llvm::Triple::mips:
     case llvm::Triple::mips64:
         trap_opcode_bytes = g_mips64_opcode;
         actual_opcode_size = sizeof(g_mips64_opcode);
         return Error ();
 
+    case llvm::Triple::mipsel:
     case llvm::Triple::mips64el:
         trap_opcode_bytes = g_mips64el_opcode;
         actual_opcode_size = sizeof(g_mips64el_opcode);
         return Error ();
 
     default:
         assert(false && "CPU type not supported!");
         return Error ("CPU type not supported");

source/Plugins/Process/Linux/NativeRegisterContextLinux_mips64.h

 //===-- NativeRegisterContextLinux_mips64.h ---------------------*- C++ -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 
 #if defined (__mips__)
 
 #ifndef lldb_NativeRegisterContextLinux_mips64_h
 #define lldb_NativeRegisterContextLinux_mips64_h
 
 #include "Plugins/Process/Linux/NativeRegisterContextLinux.h"
 #include "Plugins/Process/Utility/RegisterContext_mips64.h"
-#include "Plugins/Process/Utility/RegisterContextLinux_mips64.h"
-
+#include "Plugins/Process/Utility/lldb-mips64-register-enums.h"
 
 namespace lldb_private {
 namespace process_linux {
 
     class NativeProcessLinux;
 
-    // ---------------------------------------------------------------------------
-    // Internal codes for mips64 GP registers.
-    // ---------------------------------------------------------------------------
-    enum
-    {
-        k_first_gp_reg_mips64,
-        gp_reg_r0_mips64 = k_first_gp_reg_mips64,
-        gp_reg_r1_mips64,
-        gp_reg_r2_mips64,
-        gp_reg_r3_mips64,
-        gp_reg_r4_mips64,
-        gp_reg_r5_mips64,
-        gp_reg_r6_mips64,
-        gp_reg_r7_mips64,
-        gp_reg_r8_mips64,
-        gp_reg_r9_mips64,
-        gp_reg_r10_mips64,
-        gp_reg_r11_mips64,
-        gp_reg_r12_mips64,
-        gp_reg_r13_mips64,
-        gp_reg_r14_mips64,
-        gp_reg_r15_mips64,
-        gp_reg_r16_mips64,
-        gp_reg_r17_mips64,
-        gp_reg_r18_mips64,
-        gp_reg_r19_mips64,
-        gp_reg_r20_mips64,
-        gp_reg_r21_mips64,
-        gp_reg_r22_mips64,
-        gp_reg_r23_mips64,
-        gp_reg_r24_mips64,
-        gp_reg_r25_mips64,
-        gp_reg_r26_mips64,
-        gp_reg_r27_mips64,
-        gp_reg_r28_mips64,
-        gp_reg_r29_mips64,
-        gp_reg_r30_mips64,
-        gp_reg_r31_mips64,
-        gp_reg_mullo_mips64,
-        gp_reg_mulhi_mips64,
-        gp_reg_pc_mips64,
-        gp_reg_badvaddr_mips64,
-        gp_reg_sr_mips64,
-        gp_reg_cause_mips64,
-        k_num_gp_reg_mips64,
-    };
-
     class NativeRegisterContextLinux_mips64 : public NativeRegisterContextLinux
     {
     public:
         NativeRegisterContextLinux_mips64 (const ArchSpec& target_arch,
                                            NativeThreadProtocol &native_thread, 
                                            uint32_t concrete_frame_idx);
 
         uint32_t
protected:
                                       const char* reg_name,
                                       uint32_t size,
                                       RegisterValue &value) override;
 
         NativeProcessLinux::OperationUP
         GetWriteRegisterValueOperation(uint32_t offset,
                                        const char* reg_name,
                                        const RegisterValue &value) override;
+
+        bool
+        IsFPR(uint32_t reg_index) const;
+
+        void*
+        GetGPRBuffer() override { return &m_gpr_mips64; }
+
+        void*
+        GetFPRBuffer() override { return &m_fpr; }
+
+        size_t
+        GetFPRSize() override { return sizeof(FPR_mips); }
+
+    private:
+        // Info about register ranges.
+        struct RegInfo
+        {
+            uint32_t num_registers;
+            uint32_t num_gpr_registers;
+            uint32_t num_fpr_registers;
+
+            uint32_t last_gpr;
+            uint32_t first_fpr;
+            uint32_t last_fpr;
+        };
+
+        RegInfo m_reg_info;
+        
+        uint64_t m_gpr_mips64[k_num_gpr_registers_mips64];
+
+        FPR_mips m_fpr;
     };
 
 } // namespace process_linux
 } // namespace lldb_private
 
 #endif // #ifndef lldb_NativeRegisterContextLinux_mips64_h
 
 #endif // defined (__mips__)

source/Plugins/Process/Linux/NativeRegisterContextLinux_mips64.cpp

 #include "NativeRegisterContextLinux_mips64.h"
 
 // C Includes
 // C++ Includes
 
 // Other libraries and framework includes
 #include "lldb/Core/Error.h"
 #include "lldb/Core/RegisterValue.h"
+#include "lldb/Core/Log.h"
+#include "lldb/Core/DataBufferHeap.h"
+#include "lldb/Host/HostInfo.h"
 
 #include "Plugins/Process/Linux/NativeProcessLinux.h"
 #include "Plugins/Process/Linux/Procfs.h"
 #include "Plugins/Process/Utility/RegisterContextLinux_mips64.h"
+#include "Plugins/Process/Utility/RegisterContextLinux_mips.h"
 
 using namespace lldb_private;
 using namespace lldb_private::process_linux;
 
 // ----------------------------------------------------------------------------
 // Private namespace.
 // ----------------------------------------------------------------------------
 
 namespace
 {
+    // mips general purpose registers.
+    const uint32_t
+    g_gp_regnums_mips[] =
+    {
+        gpr_zero_mips,
+        gpr_r1_mips,
+        gpr_r2_mips,
+        gpr_r3_mips,
+        gpr_r4_mips,
+        gpr_r5_mips,
+        gpr_r6_mips,
+        gpr_r7_mips,
+        gpr_r8_mips,
+        gpr_r9_mips,
+        gpr_r10_mips,
+        gpr_r11_mips,
+        gpr_r12_mips,
+        gpr_r13_mips,
+        gpr_r14_mips,
+        gpr_r15_mips,
+        gpr_r16_mips,
+        gpr_r17_mips,
+        gpr_r18_mips,
+        gpr_r19_mips,
+        gpr_r20_mips,
+        gpr_r21_mips,
+        gpr_r22_mips,
+        gpr_r23_mips,
+        gpr_r24_mips,
+        gpr_r25_mips,
+        gpr_r26_mips,
+        gpr_r27_mips,
+        gpr_gp_mips,
+        gpr_sp_mips,
+        gpr_r30_mips,
+        gpr_ra_mips,
+        gpr_mullo_mips,
+        gpr_mulhi_mips,
+        gpr_pc_mips,
+        gpr_badvaddr_mips,
+        gpr_sr_mips,
+        gpr_cause_mips,
+        LLDB_INVALID_REGNUM     // register sets need to end with this flag
+    };
+
+    static_assert((sizeof(g_gp_regnums_mips) / sizeof(g_gp_regnums_mips[0])) - 1 == k_num_gpr_registers_mips,
+                  "g_gp_regnums_mips has wrong number of register infos");
+
+    // mips floating point registers.
+    const uint32_t
+    g_fp_regnums_mips[] =
+    {
+        fpr_f0_mips,
+        fpr_f1_mips,
+        fpr_f2_mips,
+        fpr_f3_mips,
+        fpr_f4_mips,
+        fpr_f5_mips,
+        fpr_f6_mips,
+        fpr_f7_mips,
+        fpr_f8_mips,
+        fpr_f9_mips,
+        fpr_f10_mips,
+        fpr_f11_mips,
+        fpr_f12_mips,
+        fpr_f13_mips,
+        fpr_f14_mips,
+        fpr_f15_mips,
+        fpr_f16_mips,
+        fpr_f17_mips,
+        fpr_f18_mips,
+        fpr_f19_mips,
+        fpr_f20_mips,
+        fpr_f21_mips,
+        fpr_f22_mips,
+        fpr_f23_mips,
+        fpr_f24_mips,
+        fpr_f25_mips,
+        fpr_f26_mips,
+        fpr_f27_mips,
+        fpr_f28_mips,
+        fpr_f29_mips,
+        fpr_f30_mips,
+        fpr_f31_mips,
+        fpr_fcsr_mips,
+        fpr_fir_mips,
+        LLDB_INVALID_REGNUM     // register sets need to end with this flag
+    };
+
+    static_assert((sizeof(g_fp_regnums_mips) / sizeof(g_fp_regnums_mips[0])) - 1 == k_num_fpr_registers_mips,
+                  "g_fp_regnums_mips has wrong number of register infos");
+
     // mips64 general purpose registers.
     const uint32_t
     g_gp_regnums_mips64[] =
     {
-        gp_reg_r0_mips64,
-        gp_reg_r1_mips64,
-        gp_reg_r2_mips64,
-        gp_reg_r3_mips64,
-        gp_reg_r4_mips64,
-        gp_reg_r5_mips64,
-        gp_reg_r6_mips64,
-        gp_reg_r7_mips64,
-        gp_reg_r8_mips64,
-        gp_reg_r9_mips64,
-        gp_reg_r10_mips64,
-        gp_reg_r11_mips64,
-        gp_reg_r12_mips64,
-        gp_reg_r13_mips64,
-        gp_reg_r14_mips64,
-        gp_reg_r15_mips64,
-        gp_reg_r16_mips64,
-        gp_reg_r17_mips64,
-        gp_reg_r18_mips64,
-        gp_reg_r19_mips64,
-        gp_reg_r20_mips64,
-        gp_reg_r21_mips64,
-        gp_reg_r22_mips64,
-        gp_reg_r23_mips64,
-        gp_reg_r24_mips64,
-        gp_reg_r25_mips64,
-        gp_reg_r26_mips64,
-        gp_reg_r27_mips64,
-        gp_reg_r28_mips64,
-        gp_reg_r29_mips64,
-        gp_reg_r30_mips64,
-        gp_reg_r31_mips64,
-        gp_reg_mullo_mips64,
-        gp_reg_mulhi_mips64,
-        gp_reg_pc_mips64,
-        gp_reg_badvaddr_mips64,
-        gp_reg_sr_mips64,
-        gp_reg_cause_mips64,
+        gpr_zero_mips64,
+        gpr_r1_mips64,
+        gpr_r2_mips64,
+        gpr_r3_mips64,
+        gpr_r4_mips64,
+        gpr_r5_mips64,
+        gpr_r6_mips64,
+        gpr_r7_mips64,
+        gpr_r8_mips64,
+        gpr_r9_mips64,
+        gpr_r10_mips64,
+        gpr_r11_mips64,
+        gpr_r12_mips64,
+        gpr_r13_mips64,
+        gpr_r14_mips64,
+        gpr_r15_mips64,
+        gpr_r16_mips64,
+        gpr_r17_mips64,
+        gpr_r18_mips64,
+        gpr_r19_mips64,
+        gpr_r20_mips64,
+        gpr_r21_mips64,
+        gpr_r22_mips64,
+        gpr_r23_mips64,
+        gpr_r24_mips64,
+        gpr_r25_mips64,
+        gpr_r26_mips64,
+        gpr_r27_mips64,
+        gpr_gp_mips64,
+        gpr_sp_mips64,
+        gpr_r30_mips64,
+        gpr_ra_mips64,
+        gpr_mullo_mips64,
+        gpr_mulhi_mips64,
+        gpr_pc_mips64,
+        gpr_badvaddr_mips64,
+        gpr_sr_mips64,
+        gpr_cause_mips64,
+        gpr_ic_mips64,
+        gpr_dummy_mips64,
         LLDB_INVALID_REGNUM     // register sets need to end with this flag
     };
 
-    static_assert((sizeof(g_gp_regnums_mips64) / sizeof(g_gp_regnums_mips64[0])) - 1 == k_num_gp_reg_mips64,
+    static_assert((sizeof(g_gp_regnums_mips64) / sizeof(g_gp_regnums_mips64[0])) - 1 == k_num_gpr_registers_mips64,
                   "g_gp_regnums_mips64 has wrong number of register infos");
 
+    // mips64 floating point registers.
+    const uint32_t
+    g_fp_regnums_mips64[] =
+    {
+        fpr_f0_mips64,
+        fpr_f1_mips64,
+        fpr_f2_mips64,
+        fpr_f3_mips64,
+        fpr_f4_mips64,
+        fpr_f5_mips64,
+        fpr_f6_mips64,
+        fpr_f7_mips64,
+        fpr_f8_mips64,
+        fpr_f9_mips64,
+        fpr_f10_mips64,
+        fpr_f11_mips64,
+        fpr_f12_mips64,
+        fpr_f13_mips64,
+        fpr_f14_mips64,
+        fpr_f15_mips64,
+        fpr_f16_mips64,
+        fpr_f17_mips64,
+        fpr_f18_mips64,
+        fpr_f19_mips64,
+        fpr_f20_mips64,
+        fpr_f21_mips64,
+        fpr_f22_mips64,
+        fpr_f23_mips64,
+        fpr_f24_mips64,
+        fpr_f25_mips64,
+        fpr_f26_mips64,
+        fpr_f27_mips64,
+        fpr_f28_mips64,
+        fpr_f29_mips64,
+        fpr_f30_mips64,
+        fpr_f31_mips64,
+        fpr_fcsr_mips64,
+        fpr_fir_mips64,
+        LLDB_INVALID_REGNUM     // register sets need to end with this flag
+    };
+
+    static_assert((sizeof(g_fp_regnums_mips64) / sizeof(g_fp_regnums_mips64[0])) - 1 == k_num_fpr_registers_mips64,
+                  "g_fp_regnums_mips64 has wrong number of register infos");
+
     // Number of register sets provided by this context.
     enum
     {
-        k_num_register_sets = 1
+        k_num_register_sets = 2
+    };
+
+    // Register sets for mips.
+    static const RegisterSet
+    g_reg_sets_mips[k_num_register_sets] =
+    {
+        { "General Purpose Registers",  "gpr", k_num_gpr_registers_mips, g_gp_regnums_mips },
+        { "Floating Point Registers",   "fpu", k_num_fpr_registers_mips, g_fp_regnums_mips }
     };
 
     // Register sets for mips64.
     static const RegisterSet
     g_reg_sets_mips64[k_num_register_sets] =
     {
-        { "General Purpose Registers",  "gpr", k_num_gp_reg_mips64, g_gp_regnums_mips64 }
+        { "General Purpose Registers",  "gpr", k_num_gpr_registers_mips64, g_gp_regnums_mips64 },
+        { "Floating Point Registers",   "fpu", k_num_fpr_registers_mips64, g_fp_regnums_mips64 }
     };
 
     class ReadRegOperation : public NativeProcessLinux::Operation
     {
     public:
         ReadRegOperation(lldb::tid_t tid, uint32_t offset, RegisterValue &value) :
             m_tid(tid),
             m_offset(static_cast<uintptr_t>(offset)),

 NativeRegisterContextLinux*
 NativeRegisterContextLinux::CreateHostNativeRegisterContextLinux(const ArchSpec& target_arch,
                                                                  NativeThreadProtocol &native_thread,
                                                                  uint32_t concrete_frame_idx)
 {
     return new NativeRegisterContextLinux_mips64(target_arch, native_thread, concrete_frame_idx);
 }
 
+#define REG_CONTEXT_SIZE (GetRegisterInfoInterface ().GetGPRSize () + sizeof(FPR_mips))
+
 // ----------------------------------------------------------------------------
 // NativeRegisterContextLinux_mips64 members.
 // ----------------------------------------------------------------------------
 
+static RegisterInfoInterface*
+CreateRegisterInfoInterface(const ArchSpec& target_arch)
+{
+    if (HostInfo::GetArchitecture().GetAddressByteSize() == 4)
+    {
+        // 32-bit hosts run with a RegisterContextLinux_mips context.
+        return new RegisterContextLinux_mips(target_arch);
+    }
+    else
+    {
+        assert((HostInfo::GetArchitecture().GetAddressByteSize() == 8) &&
+               "Register setting path assumes this is a 64-bit host");
+        // mips64 hosts know how to work with 64-bit and 32-bit EXEs using the mips64 register context.
+        return new RegisterContextLinux_mips64 (target_arch);
+    }
+}
+
 NativeRegisterContextLinux_mips64::NativeRegisterContextLinux_mips64 (const ArchSpec& target_arch,
                                                                       NativeThreadProtocol &native_thread, 
                                                                       uint32_t concrete_frame_idx) :
-    NativeRegisterContextLinux (native_thread, concrete_frame_idx, new RegisterContextLinux_mips64 (target_arch))
+    NativeRegisterContextLinux (native_thread, concrete_frame_idx, CreateRegisterInfoInterface(target_arch))
+{
+    switch (target_arch.GetMachine ())
     {
+        case llvm::Triple::mips:
+        case llvm::Triple::mipsel:
+            m_reg_info.num_registers        = k_num_registers_mips;
+            m_reg_info.num_gpr_registers    = k_num_gpr_registers_mips;
+            m_reg_info.num_fpr_registers    = k_num_fpr_registers_mips;
+            m_reg_info.last_gpr             = k_last_gpr_mips;
+            m_reg_info.first_fpr            = k_first_fpr_mips;
+            m_reg_info.last_fpr             = k_last_fpr_mips;
+            break;
+        case llvm::Triple::mips64:
+        case llvm::Triple::mips64el:
+            m_reg_info.num_registers        = k_num_registers_mips64;
+            m_reg_info.num_gpr_registers    = k_num_gpr_registers_mips64;
+            m_reg_info.num_fpr_registers    = k_num_fpr_registers_mips64;
+            m_reg_info.last_gpr             = k_last_gpr_mips64;
+            m_reg_info.first_fpr            = k_first_fpr_mips64;
+            m_reg_info.last_fpr             = k_last_fpr_mips64;
+            break;
+        default:
+            assert(false && "Unhandled target architecture.");
+            break;
+    }
+    
+    // Clear out the FPR state.
+    ::memset(&m_fpr, 0, sizeof(FPR_mips));
 }
 
 uint32_t
 NativeRegisterContextLinux_mips64::GetRegisterSetCount () const
 {
     return k_num_register_sets;
 }
 
 const RegisterSet *
 NativeRegisterContextLinux_mips64::GetRegisterSet (uint32_t set_index) const
 {
     if (set_index >= k_num_register_sets)
         return nullptr;
 
     switch (GetRegisterInfoInterface ().GetTargetArchitecture ().GetMachine ())
     {
         case llvm::Triple::mips64:
         case llvm::Triple::mips64el:
             return &g_reg_sets_mips64[set_index];
+        case llvm::Triple::mips:
+        case llvm::Triple::mipsel:
+            return &g_reg_sets_mips[set_index];
         default:
             assert (false && "Unhandled target architecture.");
             return nullptr;
     }
 
     return nullptr;
 }
 
NativeRegisterContextLinux_mips64::ReadRegister (const RegisterInfo *reg_info, RegisterValue &reg_value)
     const uint32_t reg = reg_info->kinds[lldb::eRegisterKindLLDB];
     if (reg == LLDB_INVALID_REGNUM)
     {
         // This is likely an internal register for lldb use only and should not be directly queried.
         error.SetErrorStringWithFormat ("register \"%s\" is an internal-only lldb register, cannot read directly", reg_info->name);
         return error;
     }
 
+    if (IsFPR(reg))
+    {
+        error = ReadFPR();
+        if (!error.Success())
+        {
+            error.SetErrorString ("failed to read floating point register");
+            return error;
+        }
+        assert (reg_info->byte_offset < sizeof(FPR_mips));
+        uint8_t *src = (uint8_t *)&m_fpr + reg_info->byte_offset;
+        switch (reg_info->byte_size)
+        {
+            case 4:
+                reg_value.SetUInt32(*(uint32_t *)src);
+                break;
+            case 8:
+                reg_value.SetUInt64(*(uint64_t *)src);
+                break;
+            default:
+                assert(false && "Unhandled data size.");
+                error.SetErrorStringWithFormat ("unhandled byte size: %" PRIu32, reg_info->byte_size);
+                break;
+        }
+    }
+    else
+    {
         error = ReadRegisterRaw(reg, reg_value);
-
-    if (error.Success ())
+        if (error.Success())
         {
             // If our return byte size was greater than the return value reg size, then
             // use the type specified by reg_info rather than the uint64_t default
             if (reg_value.GetByteSize() > reg_info->byte_size)
                 reg_value.SetType(reg_info);
         }
+    }
 
     return error;
 }
 
 lldb_private::Error
 NativeRegisterContextLinux_mips64::WriteRegister (const RegisterInfo *reg_info, const RegisterValue &reg_value)
 {
+    Error error;
+
     assert (reg_info && "reg_info is null");
 
     const uint32_t reg_index = reg_info->kinds[lldb::eRegisterKindLLDB];
 
     if (reg_index == LLDB_INVALID_REGNUM)
         return Error ("no lldb regnum for %s", reg_info && reg_info->name ? reg_info->name : "<unknown register>");
 
-    return WriteRegisterRaw(reg_index, reg_value);
+    if (IsFPR(reg_index))
+    {
+        assert (reg_info->byte_offset < sizeof(FPR_mips));
+        uint8_t *dst = (uint8_t *)&m_fpr + reg_info->byte_offset;
+        switch (reg_info->byte_size)
+        {
+            case 4:
+                *(uint32_t *)dst = reg_value.GetAsUInt32();
+                break;
+            case 8:
+                *(uint64_t *)dst = reg_value.GetAsUInt64();
+                break;
+            default:
+                assert(false && "Unhandled data size.");
+                error.SetErrorStringWithFormat ("unhandled byte size: %" PRIu32, reg_info->byte_size);
+                break;
+        }
+        error = WriteFPR();
+        if (!error.Success())
+        {
+            error.SetErrorString ("failed to write floating point register");
+            return error;
+        }
+    }
+    else
+    {
+        error = WriteRegisterRaw(reg_index, reg_value);
+    }
+
+    return error;
 }
 
 Error
 NativeRegisterContextLinux_mips64::ReadAllRegisterValues (lldb::DataBufferSP &data_sp)
 {
     Error error;
-    error.SetErrorString ("MIPS TODO: NativeRegisterContextLinux_mips64::ReadAllRegisterValues not implemented");
+
+    data_sp.reset (new DataBufferHeap (REG_CONTEXT_SIZE, 0));
+    if (!data_sp)
+    {
+        error.SetErrorStringWithFormat ("failed to allocate DataBufferHeap instance of size %" PRIu64, REG_CONTEXT_SIZE);
+        return error;
+    }
+
+    error = ReadGPR();
+    if (!error.Success())
+    {
+        error.SetErrorString ("ReadGPR() failed");
+        return error;
+    }
+
+    error = ReadFPR();
+    if (!error.Success())
+    {
+        error.SetErrorString ("ReadFPR() failed");
+        return error;
+    }
+
+    uint8_t *dst = data_sp->GetBytes ();
+    if (dst == nullptr)
+    {
+        error.SetErrorStringWithFormat ("DataBufferHeap instance of size %" PRIu64 " returned a null pointer", REG_CONTEXT_SIZE);
+        return error;
+    }
+
+    ::memcpy (dst, &m_gpr_mips64, GetRegisterInfoInterface ().GetGPRSize ());
+    dst += GetRegisterInfoInterface ().GetGPRSize ();
+
+    ::memcpy (dst, &m_fpr, sizeof(FPR_mips));
+
     return error;
 }
 
 Error
 NativeRegisterContextLinux_mips64::WriteAllRegisterValues (const lldb::DataBufferSP &data_sp)
 {
     Error error;
-    error.SetErrorString ("MIPS TODO: NativeRegisterContextLinux_mips64::WriteAllRegisterValues not implemented");
+
+    if (!data_sp)
+    {
+        error.SetErrorStringWithFormat ("NativeRegisterContextLinux_mips64::%s invalid data_sp provided", __FUNCTION__);
+        return error;
+    }
+
+    if (data_sp->GetByteSize () != REG_CONTEXT_SIZE)
+    {
+        error.SetErrorStringWithFormat ("NativeRegisterContextLinux_mips64::%s data_sp contained mismatched data size, expected %" PRIu64 ", actual %" PRIu64, __FUNCTION__, REG_CONTEXT_SIZE, data_sp->GetByteSize ());
+        return error;
+    }
+
+
+    uint8_t *src = data_sp->GetBytes ();
+    if (src == nullptr)
+    {
+        error.SetErrorStringWithFormat ("NativeRegisterContextLinux_mips64::%s DataBuffer::GetBytes() returned a null pointer", __FUNCTION__);
         return error;
     }
+    ::memcpy (&m_gpr_mips64, src, GetRegisterInfoInterface ().GetGPRSize ());
+    src += GetRegisterInfoInterface ().GetGPRSize ();
+
+    ::memcpy (&m_fpr, src, sizeof(FPR_mips));
+
+    error = WriteGPR();
+    if (!error.Success())
+    {
+        error.SetErrorStringWithFormat ("NativeRegisterContextLinux_mips64::%s WriteGPR() failed", __FUNCTION__);
+        return error;
+    }
+
+    error = WriteFPR();
+    if (!error.Success())
+    {
+        error.SetErrorStringWithFormat ("NativeRegisterContextLinux_mips64::%s WriteFPR() failed", __FUNCTION__);
+        return error;
+    }
+
+    return error;
+}
+
+bool
+NativeRegisterContextLinux_mips64::IsFPR(uint32_t reg_index) const
+{
+    return (m_reg_info.first_fpr <= reg_index && reg_index <= m_reg_info.last_fpr);
+}
 
 Error
 NativeRegisterContextLinux_mips64::IsWatchpointHit (uint32_t wp_index, bool &is_hit)
 {
     is_hit = false;
     return Error("MIPS TODO: NativeRegisterContextLinux_mips64::IsWatchpointHit not implemented");
 }
 

source/Plugins/Process/Utility/CMakeLists.txt

add_lldb_library(lldbPluginProcessUtility
   RegisterContextFreeBSD_powerpc.cpp
   RegisterContextFreeBSD_x86_64.cpp
   RegisterContextHistory.cpp
   RegisterContextLinux_arm.cpp
   RegisterContextLinux_arm64.cpp
   RegisterContextLinux_i386.cpp
   RegisterContextLinux_x86_64.cpp
   RegisterContextLinux_mips64.cpp
+  RegisterContextLinux_mips.cpp
   RegisterContextLLDB.cpp
   RegisterContextMacOSXFrameBackchain.cpp
   RegisterContextMach_arm.cpp
   RegisterContextMach_i386.cpp
   RegisterContextMach_x86_64.cpp
   RegisterContextMemory.cpp
   RegisterContextPOSIX_arm.cpp
   RegisterContextPOSIX_arm64.cpp

source/Plugins/Process/Utility/RegisterContextLinux_mips.h

+//===-- RegisterContextLinux_mips.h ---------------------------*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef liblldb_RegisterContextLinux_mips_H_
+#define liblldb_RegisterContextLinux_mips_H_
+
+#include "lldb/lldb-private.h"
+#include "RegisterInfoInterface.h"
+
+class RegisterContextLinux_mips
+    : public lldb_private::RegisterInfoInterface
+{
+public:
+    RegisterContextLinux_mips(const lldb_private::ArchSpec &target_arch);
+
+    size_t
+    GetGPRSize() const override;
+
+    const lldb_private::RegisterInfo *
+    GetRegisterInfo() const override;
+
+    uint32_t
+    GetRegisterCount () const override;
+
+private:
+    const lldb_private::RegisterInfo *m_register_info_p;
+    uint32_t m_register_info_count;
+};
+
+#endif

source/Plugins/Process/Utility/RegisterContextLinux_mips.cpp

+//===-- RegisterContextLinux_mips.cpp ------------------------*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===---------------------------------------------------------------------===//
+
+#include <vector>
+#include <stddef.h>
+
+// For GDB, GCC and DWARF Register numbers
+#include "RegisterContextLinux_mips.h"
+
+// Internal codes for mips registers
+#include "lldb-mips64-register-enums.h"
+#include "RegisterContext_mips64.h"
+
+using namespace lldb_private;
+using namespace lldb;
+
+// GP registers
+typedef struct _GPR
+{
+    uint32_t zero;
+    uint32_t r1;
+    uint32_t r2;
+    uint32_t r3;
+    uint32_t r4;
+    uint32_t r5;
+    uint32_t r6;
+    uint32_t r7;
+    uint32_t r8;
+    uint32_t r9;
+    uint32_t r10;
+    uint32_t r11;
+    uint32_t r12;
+    uint32_t r13;
+    uint32_t r14;
+    uint32_t r15;
+    uint32_t r16;
+    uint32_t r17;
+    uint32_t r18;
+    uint32_t r19;
+    uint32_t r20;
+    uint32_t r21;
+    uint32_t r22;
+    uint32_t r23;
+    uint32_t r24;
+    uint32_t r25;
+    uint32_t r26;
+    uint32_t r27;
+    uint32_t gp;
+    uint32_t sp;
+    uint32_t r30;
+    uint32_t ra;
+    uint32_t mullo;
+    uint32_t mulhi;
+    uint32_t pc;
+    uint32_t badvaddr;
+    uint32_t sr;
+    uint32_t cause;
+} GPR;
+
+//---------------------------------------------------------------------------
+// Include RegisterInfos_mips to declare our g_register_infos_mips structure.
+//---------------------------------------------------------------------------
+#define DECLARE_REGISTER_INFOS_MIPS_STRUCT
+#include "RegisterInfos_mips.h"
+#undef DECLARE_REGISTER_INFOS_MIPS_STRUCT
+
+RegisterContextLinux_mips::RegisterContextLinux_mips(const ArchSpec &target_arch) :
+    RegisterInfoInterface(target_arch)
+{
+}
+
+size_t
+RegisterContextLinux_mips::GetGPRSize() const
+{
+    return sizeof(GPR);
+}
+
+const RegisterInfo *
+RegisterContextLinux_mips::GetRegisterInfo() const
+{
+    switch (m_target_arch.GetMachine())
+    {
+        case llvm::Triple::mips:            
+        case llvm::Triple::mipsel:
+            return g_register_infos_mips;
+        default:
+            assert(false && "Unhandled target architecture.");
+            return NULL;
+    }
+}
+
+uint32_t
+RegisterContextLinux_mips::GetRegisterCount () const
+{
+    return static_cast<uint32_t> (sizeof (g_register_infos_mips) / sizeof (g_register_infos_mips [0]));
+}

source/Plugins/Process/Utility/RegisterContextLinux_mips64.cpp

 
 #include <vector>
 #include <stddef.h>
 
 // For GDB, GCC and DWARF Register numbers
 #include "RegisterContextLinux_mips64.h"
 
 // Internal codes for all mips64 registers
-#include "Plugins/Process/Linux/NativeRegisterContextLinux_mips64.h"
+#include "lldb-mips64-register-enums.h"
 #include "RegisterContext_mips64.h"
 
 using namespace lldb;
 using namespace lldb_private;
-using namespace lldb_private::process_linux;
 
 // GP registers
 typedef struct _GPR
 {
-    uint64_t    gp_reg[32];
-    uint64_t    mul_lo;
-    uint64_t    mul_hi;
-    uint64_t    cp0_epc;
-    uint64_t    cp0_badvaddr;
-    uint64_t    cp0_status;
-    uint64_t    cp0_cause;
+    uint64_t zero;
+    uint64_t r1;
+    uint64_t r2;
+    uint64_t r3;
+    uint64_t r4;
+    uint64_t r5;
+    uint64_t r6;
+    uint64_t r7;
+    uint64_t r8;
+    uint64_t r9;
+    uint64_t r10;
+    uint64_t r11;
+    uint64_t r12;
+    uint64_t r13;
+    uint64_t r14;
+    uint64_t r15;
+    uint64_t r16;
+    uint64_t r17;
+    uint64_t r18;
+    uint64_t r19;
+    uint64_t r20;
+    uint64_t r21;
+    uint64_t r22;
+    uint64_t r23;
+    uint64_t r24;
+    uint64_t r25;
+    uint64_t r26;
+    uint64_t r27;
+    uint64_t gp;
+    uint64_t sp;
+    uint64_t r30;
+    uint64_t ra;
+    uint64_t mullo;
+    uint64_t mulhi;
+    uint64_t pc;
+    uint64_t badvaddr;
+    uint64_t sr;
+    uint64_t cause;
+    uint64_t ic;
+    uint64_t dummy;
 } GPR;
 
-// FP registers
-typedef struct _FPR
-{
-    uint64_t    fp_reg[32];
-    uint64_t    fsr;        /* FPU status register */
-    uint64_t    fcr;        /* FPU control register */
-} FPR;
-
-// Computes the offset of the given GPR/FPR in the user data area.
-#define GPR_OFFSET(regname) (LLVM_EXTENSION offsetof(GPR, regname))
-#define FPR_OFFSET(regname) (LLVM_EXTENSION offsetof(FPR, regname))
-
-// Note that the size and offset will be updated by platform-specific classes.
-#define DEFINE_GPR(member, reg, alt, kind1, kind2, kind3, kind4)                    \
-    { #reg, alt, sizeof(((GPR*)0)->member), GPR_OFFSET(member), eEncodingUint,      \
-      eFormatHex, { kind1, kind2, kind3, kind4, gp_reg_##reg##_mips64 }, NULL, NULL }
-
-#define DEFINE_FPR(member, reg, alt, kind1, kind2, kind3, kind4)                    \
-    { #reg, alt, sizeof(((FPR*)0)->member), FPR_OFFSET(member), eEncodingIEEE754,   \
-      eFormatFloat, { kind1, kind2, kind3, kind4, fp_reg_##reg##_mips64 }, NULL, NULL }
-
-static RegisterInfo
-g_register_infos_mips64[] =
-{
-    DEFINE_GPR (gp_reg[0],  r0,   "zero",   gcc_dwarf_zero_mips64,  gcc_dwarf_zero_mips64,  LLDB_INVALID_REGNUM,    gdb_zero_mips64),
-    DEFINE_GPR (gp_reg[1],  r1,     "at",   gcc_dwarf_r1_mips64,    gcc_dwarf_r1_mips64,    LLDB_INVALID_REGNUM,    gdb_r1_mips64),
-    DEFINE_GPR (gp_reg[2],  r2,     NULL,   gcc_dwarf_r2_mips64,    gcc_dwarf_r2_mips64,    LLDB_INVALID_REGNUM,    gdb_r2_mips64),
-    DEFINE_GPR (gp_reg[3],  r3,     NULL,   gcc_dwarf_r3_mips64,    gcc_dwarf_r3_mips64,    LLDB_INVALID_REGNUM,    gdb_r3_mips64),
-    DEFINE_GPR (gp_reg[4],  r4,     NULL,   gcc_dwarf_r4_mips64,    gcc_dwarf_r4_mips64,    LLDB_REGNUM_GENERIC_ARG1,    gdb_r4_mips64),
-    DEFINE_GPR (gp_reg[5],  r5,     NULL,   gcc_dwarf_r5_mips64,    gcc_dwarf_r5_mips64,    LLDB_REGNUM_GENERIC_ARG2,    gdb_r5_mips64),
-    DEFINE_GPR (gp_reg[6],  r6,     NULL,   gcc_dwarf_r6_mips64,    gcc_dwarf_r6_mips64,    LLDB_REGNUM_GENERIC_ARG3,    gdb_r6_mips64),
-    DEFINE_GPR (gp_reg[7],  r7,     NULL,   gcc_dwarf_r7_mips64,    gcc_dwarf_r7_mips64,    LLDB_REGNUM_GENERIC_ARG4,    gdb_r7_mips64),
-    DEFINE_GPR (gp_reg[8],  r8,     NULL,   gcc_dwarf_r8_mips64,    gcc_dwarf_r8_mips64,    LLDB_INVALID_REGNUM,    gdb_r8_mips64),
-    DEFINE_GPR (gp_reg[9],  r9,     NULL,   gcc_dwarf_r9_mips64,    gcc_dwarf_r9_mips64,    LLDB_INVALID_REGNUM,    gdb_r9_mips64),
-    DEFINE_GPR (gp_reg[10], r10,    NULL,   gcc_dwarf_r10_mips64,   gcc_dwarf_r10_mips64,   LLDB_INVALID_REGNUM,    gdb_r10_mips64),
-    DEFINE_GPR (gp_reg[11], r11,    NULL,   gcc_dwarf_r11_mips64,   gcc_dwarf_r11_mips64,   LLDB_INVALID_REGNUM,    gdb_r11_mips64),
-    DEFINE_GPR (gp_reg[12], r12,    NULL,   gcc_dwarf_r12_mips64,   gcc_dwarf_r12_mips64,   LLDB_INVALID_REGNUM,    gdb_r12_mips64),
-    DEFINE_GPR (gp_reg[13], r13,    NULL,   gcc_dwarf_r13_mips64,   gcc_dwarf_r13_mips64,   LLDB_INVALID_REGNUM,    gdb_r13_mips64),
-    DEFINE_GPR (gp_reg[14], r14,    NULL,   gcc_dwarf_r14_mips64,   gcc_dwarf_r14_mips64,   LLDB_INVALID_REGNUM,    gdb_r14_mips64),
-    DEFINE_GPR (gp_reg[15], r15,    NULL,   gcc_dwarf_r15_mips64,   gcc_dwarf_r15_mips64,   LLDB_INVALID_REGNUM,    gdb_r15_mips64),
-    DEFINE_GPR (gp_reg[16], r16,    NULL,   gcc_dwarf_r16_mips64,   gcc_dwarf_r16_mips64,   LLDB_INVALID_REGNUM,    gdb_r16_mips64),
-    DEFINE_GPR (gp_reg[17], r17,    NULL,   gcc_dwarf_r17_mips64,   gcc_dwarf_r17_mips64,   LLDB_INVALID_REGNUM,    gdb_r17_mips64),
-    DEFINE_GPR (gp_reg[18], r18,    NULL,   gcc_dwarf_r18_mips64,   gcc_dwarf_r18_mips64,   LLDB_INVALID_REGNUM,    gdb_r18_mips64),
-    DEFINE_GPR (gp_reg[19], r19,    NULL,   gcc_dwarf_r19_mips64,   gcc_dwarf_r19_mips64,   LLDB_INVALID_REGNUM,    gdb_r19_mips64),
-    DEFINE_GPR (gp_reg[20], r20,    NULL,   gcc_dwarf_r20_mips64,   gcc_dwarf_r20_mips64,   LLDB_INVALID_REGNUM,    gdb_r20_mips64),
-    DEFINE_GPR (gp_reg[21], r21,    NULL,   gcc_dwarf_r21_mips64,   gcc_dwarf_r21_mips64,   LLDB_INVALID_REGNUM,    gdb_r21_mips64),
-    DEFINE_GPR (gp_reg[22], r22,    NULL,   gcc_dwarf_r22_mips64,   gcc_dwarf_r22_mips64,   LLDB_INVALID_REGNUM,    gdb_r22_mips64),
-    DEFINE_GPR (gp_reg[23], r23,    NULL,   gcc_dwarf_r23_mips64,   gcc_dwarf_r23_mips64,   LLDB_INVALID_REGNUM,    gdb_r23_mips64),
-    DEFINE_GPR (gp_reg[24], r24,    NULL,   gcc_dwarf_r24_mips64,   gcc_dwarf_r24_mips64,   LLDB_INVALID_REGNUM,    gdb_r24_mips64),
-    DEFINE_GPR (gp_reg[25], r25,    NULL,   gcc_dwarf_r25_mips64,   gcc_dwarf_r25_mips64,   LLDB_INVALID_REGNUM,    gdb_r25_mips64),
-    DEFINE_GPR (gp_reg[26], r26,    NULL,   gcc_dwarf_r26_mips64,   gcc_dwarf_r26_mips64,   LLDB_INVALID_REGNUM,    gdb_r26_mips64),
-    DEFINE_GPR (gp_reg[27], r27,    NULL,   gcc_dwarf_r27_mips64,   gcc_dwarf_r27_mips64,   LLDB_INVALID_REGNUM,    gdb_r27_mips64),
-    DEFINE_GPR (gp_reg[28], r28,    "gp",   gcc_dwarf_gp_mips64,    gcc_dwarf_gp_mips64,    LLDB_INVALID_REGNUM,    gdb_gp_mips64),
-    DEFINE_GPR (gp_reg[29], r29,    "sp",   gcc_dwarf_sp_mips64,    gcc_dwarf_sp_mips64,    LLDB_REGNUM_GENERIC_SP, gdb_sp_mips64),
-    DEFINE_GPR (gp_reg[30], r30,    "fp",   gcc_dwarf_r30_mips64,   gcc_dwarf_r30_mips64,   LLDB_REGNUM_GENERIC_FP, gdb_r30_mips64),
-    DEFINE_GPR (gp_reg[31], r31,    "ra",   gcc_dwarf_ra_mips64,    gcc_dwarf_ra_mips64,    LLDB_REGNUM_GENERIC_RA, gdb_ra_mips64),
-    DEFINE_GPR (mul_lo,     mullo,  NULL,   gcc_dwarf_lo_mips64,    gcc_dwarf_lo_mips64,    LLDB_INVALID_REGNUM,    LLDB_INVALID_REGNUM),
-    DEFINE_GPR (mul_hi,     mulhi,  NULL,   gcc_dwarf_hi_mips64,    gcc_dwarf_hi_mips64,    LLDB_INVALID_REGNUM,    LLDB_INVALID_REGNUM),
-    DEFINE_GPR (cp0_epc,    pc,     NULL,   gcc_dwarf_pc_mips64,    gcc_dwarf_pc_mips64,    LLDB_REGNUM_GENERIC_PC, LLDB_INVALID_REGNUM),
-    DEFINE_GPR (cp0_badvaddr, badvaddr, NULL,   gcc_dwarf_bad_mips64,    gcc_dwarf_bad_mips64,    LLDB_INVALID_REGNUM,    LLDB_INVALID_REGNUM),
-    DEFINE_GPR (cp0_status, sr, "status",   gcc_dwarf_sr_mips64,    gcc_dwarf_sr_mips64,    LLDB_REGNUM_GENERIC_FLAGS,    LLDB_INVALID_REGNUM),
-    DEFINE_GPR (cp0_cause,  cause,  NULL,   gcc_dwarf_cause_mips64,    gcc_dwarf_cause_mips64,    LLDB_INVALID_REGNUM,    LLDB_INVALID_REGNUM),
-};
+//---------------------------------------------------------------------------
+// Include RegisterInfos_mips64 to declare our g_register_infos_mips64 structure.
+//---------------------------------------------------------------------------
+#define DECLARE_REGISTER_INFOS_MIPS64_STRUCT
+#include "RegisterInfos_mips64.h"
+#undef DECLARE_REGISTER_INFOS_MIPS64_STRUCT
 
 static const RegisterInfo *
 GetRegisterInfoPtr (const ArchSpec &target_arch)
 {
     switch (target_arch.GetMachine())
     {
         case llvm::Triple::mips64:
         case llvm::Triple::mips64el:
+        case llvm::Triple::mips:
+        case llvm::Triple::mipsel:
             return g_register_infos_mips64;
         default:
             assert(false && "Unhandled target architecture.");
             return nullptr;
     }
 }
 
 static uint32_t
 GetRegisterInfoCount (const ArchSpec &target_arch)
 {
     switch (target_arch.GetMachine())
     {
         case llvm::Triple::mips64:
         case llvm::Triple::mips64el:
+        case llvm::Triple::mips:
+        case llvm::Triple::mipsel:
             return static_cast<uint32_t> (sizeof (g_register_infos_mips64) / sizeof (g_register_infos_mips64 [0]));
         default:
             assert(false && "Unhandled target architecture.");
             return 0;
     }
 }
 
 RegisterContextLinux_mips64::RegisterContextLinux_mips64(const ArchSpec &target_arch) :

source/Plugins/Process/Utility/RegisterContextPOSIX_mips64.h

 //===-- RegisterContextPOSIX_mips64.h ---------------------------*- C++ -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 
 #ifndef liblldb_RegisterContextPOSIX_mips64_H_
 #define liblldb_RegisterContextPOSIX_mips64_H_
 
 #include "lldb/Core/Log.h"
 #include "RegisterContextPOSIX.h"
 #include "RegisterContext_mips64.h"
+#include "lldb-mips64-register-enums.h"
 
-class ProcessMonitor;
-
-// ---------------------------------------------------------------------------
-// Internal codes for all mips64 registers.
-// ---------------------------------------------------------------------------
-enum
-{
-    k_first_gpr_mips64,
-    gpr_zero_mips64 = k_first_gpr_mips64,
-    gpr_r1_mips64,
-    gpr_r2_mips64,
-    gpr_r3_mips64,
-    gpr_r4_mips64,
-    gpr_r5_mips64,
-    gpr_r6_mips64,
-    gpr_r7_mips64,
-    gpr_r8_mips64,
-    gpr_r9_mips64,
-    gpr_r10_mips64,
-    gpr_r11_mips64,
-    gpr_r12_mips64,
-    gpr_r13_mips64,
-    gpr_r14_mips64,
-    gpr_r15_mips64,
-    gpr_r16_mips64,
-    gpr_r17_mips64,
-    gpr_r18_mips64,
-    gpr_r19_mips64,
-    gpr_r20_mips64,
-    gpr_r21_mips64,
-    gpr_r22_mips64,
-    gpr_r23_mips64,
-    gpr_r24_mips64,
-    gpr_r25_mips64,
-    gpr_r26_mips64,
-    gpr_r27_mips64,
-    gpr_gp_mips64,
-    gpr_sp_mips64,
-    gpr_r30_mips64,
-    gpr_ra_mips64,
-    gpr_sr_mips64,
-    gpr_mullo_mips64,
-    gpr_mulhi_mips64,
-    gpr_badvaddr_mips64,
-    gpr_cause_mips64,
-    gpr_pc_mips64,
-    gpr_ic_mips64,
-    gpr_dummy_mips64,
+using namespace lldb_private;
 
-    k_num_registers_mips64,
-    k_num_gpr_registers_mips64 = k_num_registers_mips64
-};
+class ProcessMonitor;
 
 class RegisterContextPOSIX_mips64
   : public lldb_private::RegisterContext
 {
 public:
     RegisterContextPOSIX_mips64 (lldb_private::Thread &thread,
                             uint32_t concrete_frame_idx,
                             lldb_private::RegisterInfoInterface *register_info);

source/Plugins/Process/Utility/RegisterContext_mips64.h

 //===-- RegisterContext_mips64.h --------------------------------*- C++ -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 
 #ifndef liblldb_RegisterContext_mips64_H_
 #define liblldb_RegisterContext_mips64_H_
 
 // GCC and DWARF Register numbers (eRegisterKindGCC & eRegisterKindDWARF)
 enum
 {
     // GP Registers
+    gcc_dwarf_zero_mips = 0,
+    gcc_dwarf_r1_mips,
+    gcc_dwarf_r2_mips,
+    gcc_dwarf_r3_mips,
+    gcc_dwarf_r4_mips,
+    gcc_dwarf_r5_mips,
+    gcc_dwarf_r6_mips,
+    gcc_dwarf_r7_mips,
+    gcc_dwarf_r8_mips,
+    gcc_dwarf_r9_mips,
+    gcc_dwarf_r10_mips,
+    gcc_dwarf_r11_mips,
+    gcc_dwarf_r12_mips,
+    gcc_dwarf_r13_mips,
+    gcc_dwarf_r14_mips,
+    gcc_dwarf_r15_mips,
+    gcc_dwarf_r16_mips,
+    gcc_dwarf_r17_mips,
+    gcc_dwarf_r18_mips,
+    gcc_dwarf_r19_mips,
+    gcc_dwarf_r20_mips,
+    gcc_dwarf_r21_mips,
+    gcc_dwarf_r22_mips,
+    gcc_dwarf_r23_mips,
+    gcc_dwarf_r24_mips,
+    gcc_dwarf_r25_mips,
+    gcc_dwarf_r26_mips,
+    gcc_dwarf_r27_mips,
+    gcc_dwarf_gp_mips,
+    gcc_dwarf_sp_mips,
+    gcc_dwarf_r30_mips,
+    gcc_dwarf_ra_mips,
+    gcc_dwarf_lo_mips,
+    gcc_dwarf_hi_mips,
+    gcc_dwarf_pc_mips,
+    gcc_dwarf_bad_mips,
+    gcc_dwarf_sr_mips,
+    gcc_dwarf_cause_mips,
+    gcc_dwarf_f0_mips,  
+    gcc_dwarf_f1_mips,
+    gcc_dwarf_f2_mips,
+    gcc_dwarf_f3_mips,
+    gcc_dwarf_f4_mips,
+    gcc_dwarf_f5_mips,
+    gcc_dwarf_f6_mips,
+    gcc_dwarf_f7_mips,
+    gcc_dwarf_f8_mips,
+    gcc_dwarf_f9_mips,
+    gcc_dwarf_f10_mips,
+    gcc_dwarf_f11_mips,
+    gcc_dwarf_f12_mips,
+    gcc_dwarf_f13_mips,
+    gcc_dwarf_f14_mips,
+    gcc_dwarf_f15_mips,
+    gcc_dwarf_f16_mips,
+    gcc_dwarf_f17_mips,
+    gcc_dwarf_f18_mips,
+    gcc_dwarf_f19_mips,
+    gcc_dwarf_f20_mips,
+    gcc_dwarf_f21_mips,
+    gcc_dwarf_f22_mips,
+    gcc_dwarf_f23_mips,
+    gcc_dwarf_f24_mips,
+    gcc_dwarf_f25_mips,
+    gcc_dwarf_f26_mips,
+    gcc_dwarf_f27_mips,
+    gcc_dwarf_f28_mips,
+    gcc_dwarf_f29_mips,
+    gcc_dwarf_f30_mips,
+    gcc_dwarf_f31_mips,
+    gcc_dwarf_fcsr_mips,
+    gcc_dwarf_fir_mips,
+    gcc_dwarf_ic_mips,
+    gcc_dwarf_dummy_mips
+};
+
+enum
+{
     gcc_dwarf_zero_mips64 = 0,
     gcc_dwarf_r1_mips64,
     gcc_dwarf_r2_mips64,
     gcc_dwarf_r3_mips64,
     gcc_dwarf_r4_mips64,
     gcc_dwarf_r5_mips64,
     gcc_dwarf_r6_mips64,
     gcc_dwarf_r7_mips64,
enum
     gcc_dwarf_r30_mips64,
     gcc_dwarf_ra_mips64,
     gcc_dwarf_sr_mips64,
     gcc_dwarf_lo_mips64,
     gcc_dwarf_hi_mips64,
     gcc_dwarf_bad_mips64,
     gcc_dwarf_cause_mips64,
     gcc_dwarf_pc_mips64,
+    gcc_dwarf_f0_mips64,  
+    gcc_dwarf_f1_mips64,
+    gcc_dwarf_f2_mips64,
+    gcc_dwarf_f3_mips64,
+    gcc_dwarf_f4_mips64,
+    gcc_dwarf_f5_mips64,
+    gcc_dwarf_f6_mips64,
+    gcc_dwarf_f7_mips64,
+    gcc_dwarf_f8_mips64,
+    gcc_dwarf_f9_mips64,
+    gcc_dwarf_f10_mips64,
+    gcc_dwarf_f11_mips64,
+    gcc_dwarf_f12_mips64,
+    gcc_dwarf_f13_mips64,
+    gcc_dwarf_f14_mips64,
+    gcc_dwarf_f15_mips64,
+    gcc_dwarf_f16_mips64,
+    gcc_dwarf_f17_mips64,
+    gcc_dwarf_f18_mips64,
+    gcc_dwarf_f19_mips64,
+    gcc_dwarf_f20_mips64,
+    gcc_dwarf_f21_mips64,
+    gcc_dwarf_f22_mips64,
+    gcc_dwarf_f23_mips64,
+    gcc_dwarf_f24_mips64,
+    gcc_dwarf_f25_mips64,
+    gcc_dwarf_f26_mips64,
+    gcc_dwarf_f27_mips64,
+    gcc_dwarf_f28_mips64,
+    gcc_dwarf_f29_mips64,
+    gcc_dwarf_f30_mips64,
+    gcc_dwarf_f31_mips64,
+    gcc_dwarf_fcsr_mips64,
+    gcc_dwarf_fir_mips64,
     gcc_dwarf_ic_mips64,
     gcc_dwarf_dummy_mips64
 };
 
 // GDB Register numbers (eRegisterKindGDB)
 enum
 {
+    gdb_zero_mips = 0,
+    gdb_r1_mips,
+    gdb_r2_mips,
+    gdb_r3_mips,
+    gdb_r4_mips,
+    gdb_r5_mips,
+    gdb_r6_mips,
+    gdb_r7_mips,
+    gdb_r8_mips,
+    gdb_r9_mips,
+    gdb_r10_mips,
+    gdb_r11_mips,
+    gdb_r12_mips,
+    gdb_r13_mips,
+    gdb_r14_mips,
+    gdb_r15_mips,
+    gdb_r16_mips,
+    gdb_r17_mips,
+    gdb_r18_mips,
+    gdb_r19_mips,
+    gdb_r20_mips,
+    gdb_r21_mips,
+    gdb_r22_mips,
+    gdb_r23_mips,
+    gdb_r24_mips,
+    gdb_r25_mips,
+    gdb_r26_mips,
+    gdb_r27_mips,
+    gdb_gp_mips,
+    gdb_sp_mips,
+    gdb_r30_mips,
+    gdb_ra_mips,
+    gdb_lo_mips,
+    gdb_hi_mips,
+    gdb_pc_mips,
+    gdb_bad_mips,
+    gdb_sr_mips,
+    gdb_cause_mips,
+    gdb_f0_mips,
+    gdb_f1_mips,
+    gdb_f2_mips,
+    gdb_f3_mips,
+    gdb_f4_mips,
+    gdb_f5_mips,
+    gdb_f6_mips,
+    gdb_f7_mips,
+    gdb_f8_mips,
+    gdb_f9_mips,
+    gdb_f10_mips,
+    gdb_f11_mips,
+    gdb_f12_mips,
+    gdb_f13_mips,
+    gdb_f14_mips,
+    gdb_f15_mips,
+    gdb_f16_mips,
+    gdb_f17_mips,
+    gdb_f18_mips,
+    gdb_f19_mips,
+    gdb_f20_mips,
+    gdb_f21_mips,
+    gdb_f22_mips,
+    gdb_f23_mips,
+    gdb_f24_mips,
+    gdb_f25_mips,
+    gdb_f26_mips,
+    gdb_f27_mips,
+    gdb_f28_mips,
+    gdb_f29_mips,
+    gdb_f30_mips,
+    gdb_f31_mips,
+    gdb_fcsr_mips,
+    gdb_fir_mips,
+    gdb_ic_mips,
+    gdb_dummy_mips
+};
+
+enum
+{
     gdb_zero_mips64 = 0,
     gdb_r1_mips64,
     gdb_r2_mips64,
     gdb_r3_mips64,
     gdb_r4_mips64,
     gdb_r5_mips64,
     gdb_r6_mips64,
     gdb_r7_mips64,
enum
     gdb_r30_mips64,
     gdb_ra_mips64,
     gdb_sr_mips64,
     gdb_lo_mips64,
     gdb_hi_mips64,
     gdb_bad_mips64,
     gdb_cause_mips64,
     gdb_pc_mips64,
+    gdb_f0_mips64,
+    gdb_f1_mips64,
+    gdb_f2_mips64,
+    gdb_f3_mips64,
+    gdb_f4_mips64,
+    gdb_f5_mips64,
+    gdb_f6_mips64,
+    gdb_f7_mips64,
+    gdb_f8_mips64,
+    gdb_f9_mips64,
+    gdb_f10_mips64,
+    gdb_f11_mips64,
+    gdb_f12_mips64,
+    gdb_f13_mips64,
+    gdb_f14_mips64,
+    gdb_f15_mips64,
+    gdb_f16_mips64,
+    gdb_f17_mips64,
+    gdb_f18_mips64,
+    gdb_f19_mips64,
+    gdb_f20_mips64,
+    gdb_f21_mips64,
+    gdb_f22_mips64,
+    gdb_f23_mips64,
+    gdb_f24_mips64,
+    gdb_f25_mips64,
+    gdb_f26_mips64,
+    gdb_f27_mips64,
+    gdb_f28_mips64,
+    gdb_f29_mips64,
+    gdb_f30_mips64,
+    gdb_f31_mips64,
+    gdb_fcsr_mips64,
+    gdb_fir_mips64,
     gdb_ic_mips64,
     gdb_dummy_mips64
 };
 
+// FP registers
+struct FPR_mips
+{
+    uint64_t    fp_reg[32];
+    uint32_t    fcsr;        /* FPU status register */
+    uint32_t    fir;        /* FPU control register */
+}; 
+
+
 #endif // liblldb_RegisterContext_mips64_H_

source/Plugins/Process/Utility/RegisterInfos_mips.h

+//===-- RegisterInfos_mips.h -----------------------------------*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===---------------------------------------------------------------------===//
+#include "llvm/Support/Compiler.h"
+
+#include <stddef.h>
+
+#ifdef DECLARE_REGISTER_INFOS_MIPS_STRUCT
+
+// Computes the offset of the given GPR in the user data area.
+#define GPR_OFFSET(regname) \
+    (LLVM_EXTENSION offsetof(GPR, regname))
+
+// Computes the offset of the given FPR in the extended data area.
+#define FPR_OFFSET(regname)  \
+     (LLVM_EXTENSION offsetof(FPR_mips, regname))
+
+// Note that the size and offset will be updated by platform-specific classes.
+#define DEFINE_GPR(reg, alt, kind1, kind2, kind3, kind4)            \
+    { #reg, alt, sizeof(((GPR*)NULL)->reg), GPR_OFFSET(reg), eEncodingUint,  \
+      eFormatHex, { kind1, kind2, kind3, kind4, gpr_##reg##_mips }, NULL, NULL }
+
+#define DEFINE_FPR(member, reg, alt, kind1, kind2, kind3, kind4)           \
+    { #reg, alt, sizeof(((FPR_mips*)NULL)->member), FPR_OFFSET(member), eEncodingUint,   \
+      eFormatHex, { kind1, kind2, kind3, kind4, fpr_##reg##_mips }, NULL, NULL }
+
+// RegisterKind: GCC, DWARF, Generic, GDB, LLDB
+
+static RegisterInfo
+g_register_infos_mips[] =
+{
+    DEFINE_GPR (zero,     "zero", gcc_dwarf_zero_mips,  gcc_dwarf_zero_mips,  LLDB_INVALID_REGNUM,    gdb_zero_mips),
+    DEFINE_GPR (r1,       "at",   gcc_dwarf_r1_mips,    gcc_dwarf_r1_mips,    LLDB_INVALID_REGNUM,    gdb_r1_mips),
+    DEFINE_GPR (r2,       NULL,   gcc_dwarf_r2_mips,    gcc_dwarf_r2_mips,    LLDB_INVALID_REGNUM,    gdb_r2_mips),
+    DEFINE_GPR (r3,       NULL,   gcc_dwarf_r3_mips,    gcc_dwarf_r3_mips,    LLDB_INVALID_REGNUM,    gdb_r3_mips),
+    DEFINE_GPR (r4,       NULL,   gcc_dwarf_r4_mips,    gcc_dwarf_r4_mips,    LLDB_REGNUM_GENERIC_ARG1,    gdb_r4_mips),
+    DEFINE_GPR (r5,       NULL,   gcc_dwarf_r5_mips,    gcc_dwarf_r5_mips,    LLDB_REGNUM_GENERIC_ARG2,    gdb_r5_mips),
+    DEFINE_GPR (r6,       NULL,   gcc_dwarf_r6_mips,    gcc_dwarf_r6_mips,    LLDB_REGNUM_GENERIC_ARG3,    gdb_r6_mips),
+    DEFINE_GPR (r7,       NULL,   gcc_dwarf_r7_mips,    gcc_dwarf_r7_mips,    LLDB_REGNUM_GENERIC_ARG4,    gdb_r7_mips),
+    DEFINE_GPR (r8,       NULL,   gcc_dwarf_r8_mips,    gcc_dwarf_r8_mips,    LLDB_INVALID_REGNUM,    gdb_r8_mips),
+    DEFINE_GPR (r9,       NULL,   gcc_dwarf_r9_mips,    gcc_dwarf_r9_mips,    LLDB_INVALID_REGNUM,    gdb_r9_mips),
+    DEFINE_GPR (r10,      NULL,   gcc_dwarf_r10_mips,   gcc_dwarf_r10_mips,   LLDB_INVALID_REGNUM,    gdb_r10_mips),
+    DEFINE_GPR (r11,      NULL,   gcc_dwarf_r11_mips,   gcc_dwarf_r11_mips,   LLDB_INVALID_REGNUM,    gdb_r11_mips),
+    DEFINE_GPR (r12,      NULL,   gcc_dwarf_r12_mips,   gcc_dwarf_r12_mips,   LLDB_INVALID_REGNUM,    gdb_r12_mips),
+    DEFINE_GPR (r13,      NULL,   gcc_dwarf_r13_mips,   gcc_dwarf_r13_mips,   LLDB_INVALID_REGNUM,    gdb_r13_mips),
+    DEFINE_GPR (r14,      NULL,   gcc_dwarf_r14_mips,   gcc_dwarf_r14_mips,   LLDB_INVALID_REGNUM,    gdb_r14_mips),
+    DEFINE_GPR (r15,      NULL,   gcc_dwarf_r15_mips,   gcc_dwarf_r15_mips,   LLDB_INVALID_REGNUM,    gdb_r15_mips),
+    DEFINE_GPR (r16,      NULL,   gcc_dwarf_r16_mips,   gcc_dwarf_r16_mips,   LLDB_INVALID_REGNUM,    gdb_r16_mips),
+    DEFINE_GPR (r17,      NULL,   gcc_dwarf_r17_mips,   gcc_dwarf_r17_mips,   LLDB_INVALID_REGNUM,    gdb_r17_mips),
+    DEFINE_GPR (r18,      NULL,   gcc_dwarf_r18_mips,   gcc_dwarf_r18_mips,   LLDB_INVALID_REGNUM,    gdb_r18_mips),
+    DEFINE_GPR (r19,      NULL,   gcc_dwarf_r19_mips,   gcc_dwarf_r19_mips,   LLDB_INVALID_REGNUM,    gdb_r19_mips),
+    DEFINE_GPR (r20,      NULL,   gcc_dwarf_r20_mips,   gcc_dwarf_r20_mips,   LLDB_INVALID_REGNUM,    gdb_r20_mips),
+    DEFINE_GPR (r21,      NULL,   gcc_dwarf_r21_mips,   gcc_dwarf_r21_mips,   LLDB_INVALID_REGNUM,    gdb_r21_mips),
+    DEFINE_GPR (r22,      NULL,   gcc_dwarf_r22_mips,   gcc_dwarf_r22_mips,   LLDB_INVALID_REGNUM,    gdb_r22_mips),
+    DEFINE_GPR (r23,      NULL,   gcc_dwarf_r23_mips,   gcc_dwarf_r23_mips,   LLDB_INVALID_REGNUM,    gdb_r23_mips),
+    DEFINE_GPR (r24,      NULL,   gcc_dwarf_r24_mips,   gcc_dwarf_r24_mips,   LLDB_INVALID_REGNUM,    gdb_r24_mips),
+    DEFINE_GPR (r25,      NULL,   gcc_dwarf_r25_mips,   gcc_dwarf_r25_mips,   LLDB_INVALID_REGNUM,    gdb_r25_mips),
+    DEFINE_GPR (r26,      NULL,   gcc_dwarf_r26_mips,   gcc_dwarf_r26_mips,   LLDB_INVALID_REGNUM,    gdb_r26_mips),
+    DEFINE_GPR (r27,      NULL,   gcc_dwarf_r27_mips,   gcc_dwarf_r27_mips,   LLDB_INVALID_REGNUM,    gdb_r27_mips),
+    DEFINE_GPR (gp,       "gp",   gcc_dwarf_gp_mips,    gcc_dwarf_gp_mips,    LLDB_INVALID_REGNUM,    gdb_gp_mips),
+    DEFINE_GPR (sp,       "sp",   gcc_dwarf_sp_mips,    gcc_dwarf_sp_mips,    LLDB_REGNUM_GENERIC_SP, gdb_sp_mips),
+    DEFINE_GPR (r30,      "fp",   gcc_dwarf_r30_mips,   gcc_dwarf_r30_mips,   LLDB_REGNUM_GENERIC_FP, gdb_r30_mips),
+    DEFINE_GPR (ra,       "ra",   gcc_dwarf_ra_mips,    gcc_dwarf_ra_mips,    LLDB_REGNUM_GENERIC_RA, gdb_ra_mips),
+    DEFINE_GPR (mullo,    NULL,   gcc_dwarf_lo_mips,    gcc_dwarf_lo_mips,    LLDB_INVALID_REGNUM,    LLDB_INVALID_REGNUM),
+    DEFINE_GPR (mulhi,    NULL,   gcc_dwarf_hi_mips,    gcc_dwarf_hi_mips,    LLDB_INVALID_REGNUM,    LLDB_INVALID_REGNUM),
+    DEFINE_GPR (pc,       NULL,   gcc_dwarf_pc_mips,    gcc_dwarf_pc_mips,    LLDB_REGNUM_GENERIC_PC, LLDB_INVALID_REGNUM),
+    DEFINE_GPR (badvaddr, NULL,   gcc_dwarf_bad_mips,    gcc_dwarf_bad_mips,    LLDB_INVALID_REGNUM,    LLDB_INVALID_REGNUM),
+    DEFINE_GPR (sr,   "status",   gcc_dwarf_sr_mips,    gcc_dwarf_sr_mips,    LLDB_REGNUM_GENERIC_FLAGS,    LLDB_INVALID_REGNUM),
+    DEFINE_GPR (cause,    NULL,   gcc_dwarf_cause_mips,    gcc_dwarf_cause_mips,    LLDB_INVALID_REGNUM,    LLDB_INVALID_REGNUM),
+    DEFINE_FPR (fp_reg[0],   f0,    NULL,   gcc_dwarf_f0_mips,   gcc_dwarf_f0_mips,   LLDB_INVALID_REGNUM,    gdb_f0_mips),
+    DEFINE_FPR (fp_reg[1],   f1,    NULL,   gcc_dwarf_f1_mips,   gcc_dwarf_f1_mips,   LLDB_INVALID_REGNUM,    gdb_f1_mips),
+    DEFINE_FPR (fp_reg[2],   f2,    NULL,   gcc_dwarf_f2_mips,   gcc_dwarf_f2_mips,   LLDB_INVALID_REGNUM,    gdb_f2_mips),
+    DEFINE_FPR (fp_reg[3],   f3,    NULL,   gcc_dwarf_f3_mips,   gcc_dwarf_f3_mips,   LLDB_INVALID_REGNUM,    gdb_f3_mips),
+    DEFINE_FPR (fp_reg[4],   f4,    NULL,   gcc_dwarf_f4_mips,   gcc_dwarf_f4_mips,   LLDB_INVALID_REGNUM,    gdb_f4_mips),
+    DEFINE_FPR (fp_reg[5],   f5,    NULL,   gcc_dwarf_f5_mips,   gcc_dwarf_f5_mips,   LLDB_INVALID_REGNUM,    gdb_f5_mips),
+    DEFINE_FPR (fp_reg[6],   f6,    NULL,   gcc_dwarf_f6_mips,   gcc_dwarf_f6_mips,   LLDB_INVALID_REGNUM,    gdb_f6_mips),
+    DEFINE_FPR (fp_reg[7],   f7,    NULL,   gcc_dwarf_f7_mips,   gcc_dwarf_f7_mips,   LLDB_INVALID_REGNUM,    gdb_f7_mips),
+    DEFINE_FPR (fp_reg[8],   f8,    NULL,   gcc_dwarf_f8_mips,   gcc_dwarf_f8_mips,   LLDB_INVALID_REGNUM,    gdb_f8_mips),
+    DEFINE_FPR (fp_reg[9],   f9,    NULL,   gcc_dwarf_f9_mips,   gcc_dwarf_f9_mips,   LLDB_INVALID_REGNUM,    gdb_f9_mips),
+    DEFINE_FPR (fp_reg[10],  f10,   NULL,   gcc_dwarf_f10_mips,  gcc_dwarf_f10_mips,  LLDB_INVALID_REGNUM,    gdb_f10_mips),
+    DEFINE_FPR (fp_reg[11],  f11,   NULL,   gcc_dwarf_f11_mips,  gcc_dwarf_f11_mips,  LLDB_INVALID_REGNUM,    gdb_f11_mips),
+    DEFINE_FPR (fp_reg[12],  f12,   NULL,   gcc_dwarf_f12_mips,  gcc_dwarf_f12_mips,  LLDB_INVALID_REGNUM,    gdb_f12_mips),
+    DEFINE_FPR (fp_reg[13],  f13,   NULL,   gcc_dwarf_f13_mips,  gcc_dwarf_f13_mips,  LLDB_INVALID_REGNUM,    gdb_f13_mips),
+    DEFINE_FPR (fp_reg[14],  f14,   NULL,   gcc_dwarf_f14_mips,  gcc_dwarf_f14_mips,  LLDB_INVALID_REGNUM,    gdb_f14_mips),
+    DEFINE_FPR (fp_reg[15],  f15,   NULL,   gcc_dwarf_f15_mips,  gcc_dwarf_f15_mips,  LLDB_INVALID_REGNUM,    gdb_f15_mips),
+    DEFINE_FPR (fp_reg[16],  f16,   NULL,   gcc_dwarf_f16_mips,  gcc_dwarf_f16_mips,  LLDB_INVALID_REGNUM,    gdb_f16_mips),
+    DEFINE_FPR (fp_reg[17],  f17,   NULL,   gcc_dwarf_f17_mips,  gcc_dwarf_f17_mips,  LLDB_INVALID_REGNUM,    gdb_f17_mips),
+    DEFINE_FPR (fp_reg[18],  f18,   NULL,   gcc_dwarf_f18_mips,  gcc_dwarf_f18_mips,  LLDB_INVALID_REGNUM,    gdb_f18_mips),
+    DEFINE_FPR (fp_reg[19],  f19,   NULL,   gcc_dwarf_f19_mips,  gcc_dwarf_f19_mips,  LLDB_INVALID_REGNUM,    gdb_f19_mips),
+    DEFINE_FPR (fp_reg[20],  f20,   NULL,   gcc_dwarf_f20_mips,  gcc_dwarf_f20_mips,  LLDB_INVALID_REGNUM,    gdb_f20_mips),
+    DEFINE_FPR (fp_reg[21],  f21,   NULL,   gcc_dwarf_f21_mips,  gcc_dwarf_f21_mips,  LLDB_INVALID_REGNUM,    gdb_f21_mips),
+    DEFINE_FPR (fp_reg[22],  f22,   NULL,   gcc_dwarf_f22_mips,  gcc_dwarf_f22_mips,  LLDB_INVALID_REGNUM,    gdb_f22_mips),
+    DEFINE_FPR (fp_reg[23],  f23,   NULL,   gcc_dwarf_f23_mips,  gcc_dwarf_f23_mips,  LLDB_INVALID_REGNUM,    gdb_f23_mips),
+    DEFINE_FPR (fp_reg[24],  f24,   NULL,   gcc_dwarf_f24_mips,  gcc_dwarf_f24_mips,  LLDB_INVALID_REGNUM,    gdb_f24_mips),
+    DEFINE_FPR (fp_reg[25],  f25,   NULL,   gcc_dwarf_f25_mips,  gcc_dwarf_f25_mips,  LLDB_INVALID_REGNUM,    gdb_f25_mips),
+    DEFINE_FPR (fp_reg[26],  f26,   NULL,   gcc_dwarf_f26_mips,  gcc_dwarf_f26_mips,  LLDB_INVALID_REGNUM,    gdb_f26_mips),
+    DEFINE_FPR (fp_reg[27],  f27,   NULL,   gcc_dwarf_f27_mips,  gcc_dwarf_f27_mips,  LLDB_INVALID_REGNUM,    gdb_f27_mips),
+    DEFINE_FPR (fp_reg[28],  f28,   NULL,   gcc_dwarf_f28_mips,  gcc_dwarf_f28_mips,  LLDB_INVALID_REGNUM,    gdb_f28_mips),
+    DEFINE_FPR (fp_reg[29],  f29,   NULL,   gcc_dwarf_f29_mips,  gcc_dwarf_f29_mips,  LLDB_INVALID_REGNUM,    gdb_f29_mips),
+    DEFINE_FPR (fp_reg[30],  f30,   NULL,   gcc_dwarf_f30_mips,  gcc_dwarf_f30_mips,  LLDB_INVALID_REGNUM,    gdb_f30_mips),
+    DEFINE_FPR (fp_reg[31],  f31,   NULL,   gcc_dwarf_f31_mips,  gcc_dwarf_f31_mips,  LLDB_INVALID_REGNUM,    gdb_f31_mips),
+    DEFINE_FPR (fcsr,        fcsr,  NULL,   gcc_dwarf_fcsr_mips, gcc_dwarf_fcsr_mips, LLDB_INVALID_REGNUM,    gdb_fcsr_mips),
+    DEFINE_FPR (fir,         fir,   NULL,   gcc_dwarf_fir_mips,  gcc_dwarf_fir_mips,  LLDB_INVALID_REGNUM,    gdb_fir_mips)
+};
+static_assert((sizeof(g_register_infos_mips) / sizeof(g_register_infos_mips[0])) == k_num_registers_mips,
+    "g_register_infos_mips has wrong number of register infos");
+
+#undef GPR_OFFSET
+#undef FPR_OFFSET
+#undef DEFINE_GPR
+#undef DEFINE_FPR
+
+#endif // DECLARE_REGISTER_INFOS_MIPS_STRUCT

source/Plugins/Process/Utility/RegisterInfos_mips64.h

 //===-- RegisterInfos_mips64.h ---------------------------------*- C++ -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===---------------------------------------------------------------------===//
+#include "llvm/Support/Compiler.h"
 
 #include <stddef.h>
 
+#ifdef DECLARE_REGISTER_INFOS_MIPS64_STRUCT
+
 // Computes the offset of the given GPR in the user data area.
-#define GPR_OFFSET(regname)                                                 \
-    (offsetof(GPR, regname))
+#define GPR_OFFSET(regname) \
+    (LLVM_EXTENSION offsetof(GPR, regname))
 
-#ifdef DECLARE_REGISTER_INFOS_MIPS64_STRUCT
+// Computes the offset of the given FPR in the extended data area.
+#define FPR_OFFSET(regname) \
+     LLVM_EXTENSION offsetof(FPR_mips, regname) \
+
+// RegisterKind: GCC, DWARF, Generic, GDB, LLDB
 
 // Note that the size and offset will be updated by platform-specific classes.
-#define DEFINE_GPR(reg, alt, kind1, kind2, kind3, kind4)           \
-    { #reg, alt, sizeof(((GPR*)NULL)->reg), GPR_OFFSET(reg), eEncodingUint, \
+#define DEFINE_GPR(reg, alt, kind1, kind2, kind3, kind4)    \
+    { #reg, alt, sizeof(((GPR*)0)->reg), GPR_OFFSET(reg), eEncodingUint, \
       eFormatHex, { kind1, kind2, kind3, kind4, gpr_##reg##_mips64 }, NULL, NULL }
 
+#define DEFINE_FPR(member, reg, alt, kind1, kind2, kind3, kind4)    \
+    { #reg, alt, sizeof(((FPR_mips*)0)->member), FPR_OFFSET(member), eEncodingUint,   \
+      eFormatHex, { kind1, kind2, kind3, kind4, fpr_##reg##_mips64 }, NULL, NULL }
+
 static RegisterInfo
 g_register_infos_mips64[] =
 {
     // General purpose registers.                 GCC,                  DWARF,              Generic,                GDB
     DEFINE_GPR(zero,     "r0",  gcc_dwarf_zero_mips64,  gcc_dwarf_zero_mips64,  LLDB_INVALID_REGNUM,    gdb_zero_mips64),
     DEFINE_GPR(r1,       NULL,  gcc_dwarf_r1_mips64,    gcc_dwarf_r1_mips64,    LLDB_INVALID_REGNUM,    gdb_r1_mips64),
     DEFINE_GPR(r2,       NULL,  gcc_dwarf_r2_mips64,    gcc_dwarf_r2_mips64,    LLDB_INVALID_REGNUM,    gdb_r2_mips64),
     DEFINE_GPR(r3,       NULL,  gcc_dwarf_r3_mips64,    gcc_dwarf_r3_mips64,    LLDB_INVALID_REGNUM,    gdb_r3_mips64),
g_register_infos_mips64[] =
     DEFINE_GPR(r24,      NULL,  gcc_dwarf_r24_mips64,   gcc_dwarf_r24_mips64,   LLDB_INVALID_REGNUM,    gdb_r24_mips64),
     DEFINE_GPR(r25,      NULL,  gcc_dwarf_r25_mips64,   gcc_dwarf_r25_mips64,   LLDB_INVALID_REGNUM,    gdb_r25_mips64),
     DEFINE_GPR(r26,      NULL,  gcc_dwarf_r26_mips64,   gcc_dwarf_r26_mips64,   LLDB_INVALID_REGNUM,    gdb_r26_mips64),
     DEFINE_GPR(r27,      NULL,  gcc_dwarf_r27_mips64,   gcc_dwarf_r27_mips64,   LLDB_INVALID_REGNUM,    gdb_r27_mips64),
     DEFINE_GPR(gp,       "r28", gcc_dwarf_gp_mips64,    gcc_dwarf_gp_mips64,    LLDB_INVALID_REGNUM,    gdb_gp_mips64),
     DEFINE_GPR(sp,       "r29", gcc_dwarf_sp_mips64,    gcc_dwarf_sp_mips64,    LLDB_REGNUM_GENERIC_SP, gdb_sp_mips64),
     DEFINE_GPR(r30,      NULL,  gcc_dwarf_r30_mips64,   gcc_dwarf_r30_mips64,   LLDB_INVALID_REGNUM,    gdb_r30_mips64),
     DEFINE_GPR(ra,       "r31", gcc_dwarf_ra_mips64,    gcc_dwarf_ra_mips64,    LLDB_INVALID_REGNUM,    gdb_ra_mips64),
-    DEFINE_GPR(sr,       NULL,  gcc_dwarf_sr_mips64,    gcc_dwarf_sr_mips64,    LLDB_INVALID_REGNUM,    LLDB_INVALID_REGNUM),
     DEFINE_GPR(mullo,    NULL,  gcc_dwarf_lo_mips64,    gcc_dwarf_lo_mips64,    LLDB_INVALID_REGNUM,    LLDB_INVALID_REGNUM),
     DEFINE_GPR(mulhi,    NULL,  gcc_dwarf_hi_mips64,    gcc_dwarf_hi_mips64,    LLDB_INVALID_REGNUM,    LLDB_INVALID_REGNUM),
+    DEFINE_GPR(pc,       "pc",  gcc_dwarf_pc_mips64,    gcc_dwarf_pc_mips64,    LLDB_REGNUM_GENERIC_PC, LLDB_INVALID_REGNUM),
     DEFINE_GPR(badvaddr, NULL,  gcc_dwarf_bad_mips64,   gcc_dwarf_bad_mips64,   LLDB_INVALID_REGNUM,    LLDB_INVALID_REGNUM),
+    DEFINE_GPR(sr,       NULL,  gcc_dwarf_sr_mips64,    gcc_dwarf_sr_mips64,    LLDB_INVALID_REGNUM,    LLDB_INVALID_REGNUM),
     DEFINE_GPR(cause,    NULL,  gcc_dwarf_cause_mips64, gcc_dwarf_cause_mips64, LLDB_INVALID_REGNUM,    LLDB_INVALID_REGNUM),
-    DEFINE_GPR(pc,       "pc",  gcc_dwarf_pc_mips64,    gcc_dwarf_pc_mips64,    LLDB_REGNUM_GENERIC_PC, LLDB_INVALID_REGNUM),
     DEFINE_GPR(ic,       NULL,  gcc_dwarf_ic_mips64,    gcc_dwarf_ic_mips64,    LLDB_INVALID_REGNUM,    LLDB_INVALID_REGNUM),
     DEFINE_GPR(dummy,    NULL,  gcc_dwarf_dummy_mips64, gcc_dwarf_dummy_mips64, LLDB_INVALID_REGNUM,    LLDB_INVALID_REGNUM),
+    
+    DEFINE_FPR (fp_reg[0],   f0,    NULL,   gcc_dwarf_f0_mips64,   gcc_dwarf_f0_mips64,   LLDB_INVALID_REGNUM,    gdb_f0_mips64),
+    DEFINE_FPR (fp_reg[1],   f1,    NULL,   gcc_dwarf_f1_mips64,   gcc_dwarf_f1_mips64,   LLDB_INVALID_REGNUM,    gdb_f1_mips64),
+    DEFINE_FPR (fp_reg[2],   f2,    NULL,   gcc_dwarf_f2_mips64,   gcc_dwarf_f2_mips64,   LLDB_INVALID_REGNUM,    gdb_f2_mips64),
+    DEFINE_FPR (fp_reg[3],   f3,    NULL,   gcc_dwarf_f3_mips64,   gcc_dwarf_f3_mips64,   LLDB_INVALID_REGNUM,    gdb_f3_mips64),
+    DEFINE_FPR (fp_reg[4],   f4,    NULL,   gcc_dwarf_f4_mips64,   gcc_dwarf_f4_mips64,   LLDB_INVALID_REGNUM,    gdb_f4_mips64),
+    DEFINE_FPR (fp_reg[5],   f5,    NULL,   gcc_dwarf_f5_mips64,   gcc_dwarf_f5_mips64,   LLDB_INVALID_REGNUM,    gdb_f5_mips64),
+    DEFINE_FPR (fp_reg[6],   f6,    NULL,   gcc_dwarf_f6_mips64,   gcc_dwarf_f6_mips64,   LLDB_INVALID_REGNUM,    gdb_f6_mips64),
+    DEFINE_FPR (fp_reg[7],   f7,    NULL,   gcc_dwarf_f7_mips64,   gcc_dwarf_f7_mips64,   LLDB_INVALID_REGNUM,    gdb_f7_mips64),
+    DEFINE_FPR (fp_reg[8],   f8,    NULL,   gcc_dwarf_f8_mips64,   gcc_dwarf_f8_mips64,   LLDB_INVALID_REGNUM,    gdb_f8_mips64),
+    DEFINE_FPR (fp_reg[9],   f9,    NULL,   gcc_dwarf_f9_mips64,   gcc_dwarf_f9_mips64,   LLDB_INVALID_REGNUM,    gdb_f9_mips64),
+    DEFINE_FPR (fp_reg[10],  f10,   NULL,   gcc_dwarf_f10_mips64,  gcc_dwarf_f10_mips64,  LLDB_INVALID_REGNUM,    gdb_f10_mips64),
+    DEFINE_FPR (fp_reg[11],  f11,   NULL,   gcc_dwarf_f11_mips64,  gcc_dwarf_f11_mips64,  LLDB_INVALID_REGNUM,    gdb_f11_mips64),
+    DEFINE_FPR (fp_reg[12],  f12,   NULL,   gcc_dwarf_f12_mips64,  gcc_dwarf_f12_mips64,  LLDB_INVALID_REGNUM,    gdb_f12_mips64),
+    DEFINE_FPR (fp_reg[13],  f13,   NULL,   gcc_dwarf_f13_mips64,  gcc_dwarf_f13_mips64,  LLDB_INVALID_REGNUM,    gdb_f13_mips64),
+    DEFINE_FPR (fp_reg[14],  f14,   NULL,   gcc_dwarf_f14_mips64,  gcc_dwarf_f14_mips64,  LLDB_INVALID_REGNUM,    gdb_f14_mips64),
+    DEFINE_FPR (fp_reg[15],  f15,   NULL,   gcc_dwarf_f15_mips64,  gcc_dwarf_f15_mips64,  LLDB_INVALID_REGNUM,    gdb_f15_mips64),
+    DEFINE_FPR (fp_reg[16],  f16,   NULL,   gcc_dwarf_f16_mips64,  gcc_dwarf_f16_mips64,  LLDB_INVALID_REGNUM,    gdb_f16_mips64),
+    DEFINE_FPR (fp_reg[17],  f17,   NULL,   gcc_dwarf_f17_mips64,  gcc_dwarf_f17_mips64,  LLDB_INVALID_REGNUM,    gdb_f17_mips64),
+    DEFINE_FPR (fp_reg[18],  f18,   NULL,   gcc_dwarf_f18_mips64,  gcc_dwarf_f18_mips64,  LLDB_INVALID_REGNUM,    gdb_f18_mips64),
+    DEFINE_FPR (fp_reg[19],  f19,   NULL,   gcc_dwarf_f19_mips64,  gcc_dwarf_f19_mips64,  LLDB_INVALID_REGNUM,    gdb_f19_mips64),
+    DEFINE_FPR (fp_reg[20],  f20,   NULL,   gcc_dwarf_f20_mips64,  gcc_dwarf_f20_mips64,  LLDB_INVALID_REGNUM,    gdb_f20_mips64),
+    DEFINE_FPR (fp_reg[21],  f21,   NULL,   gcc_dwarf_f21_mips64,  gcc_dwarf_f21_mips64,  LLDB_INVALID_REGNUM,    gdb_f21_mips64),
+    DEFINE_FPR (fp_reg[22],  f22,   NULL,   gcc_dwarf_f22_mips64,  gcc_dwarf_f22_mips64,  LLDB_INVALID_REGNUM,    gdb_f22_mips64),
+    DEFINE_FPR (fp_reg[23],  f23,   NULL,   gcc_dwarf_f23_mips64,  gcc_dwarf_f23_mips64,  LLDB_INVALID_REGNUM,    gdb_f23_mips64),
+    DEFINE_FPR (fp_reg[24],  f24,   NULL,   gcc_dwarf_f24_mips64,  gcc_dwarf_f24_mips64,  LLDB_INVALID_REGNUM,    gdb_f24_mips64),
+    DEFINE_FPR (fp_reg[25],  f25,   NULL,   gcc_dwarf_f25_mips64,  gcc_dwarf_f25_mips64,  LLDB_INVALID_REGNUM,    gdb_f25_mips64),
+    DEFINE_FPR (fp_reg[26],  f26,   NULL,   gcc_dwarf_f26_mips64,  gcc_dwarf_f26_mips64,  LLDB_INVALID_REGNUM,    gdb_f26_mips64),
+    DEFINE_FPR (fp_reg[27],  f27,   NULL,   gcc_dwarf_f27_mips64,  gcc_dwarf_f27_mips64,  LLDB_INVALID_REGNUM,    gdb_f27_mips64),
+    DEFINE_FPR (fp_reg[28],  f28,   NULL,   gcc_dwarf_f28_mips64,  gcc_dwarf_f28_mips64,  LLDB_INVALID_REGNUM,    gdb_f28_mips64),
+    DEFINE_FPR (fp_reg[29],  f29,   NULL,   gcc_dwarf_f29_mips64,  gcc_dwarf_f29_mips64,  LLDB_INVALID_REGNUM,    gdb_f29_mips64),
+    DEFINE_FPR (fp_reg[30],  f30,   NULL,   gcc_dwarf_f30_mips64,  gcc_dwarf_f30_mips64,  LLDB_INVALID_REGNUM,    gdb_f30_mips64),
+    DEFINE_FPR (fp_reg[31],  f31,   NULL,   gcc_dwarf_f31_mips64,  gcc_dwarf_f31_mips64,  LLDB_INVALID_REGNUM,    gdb_f31_mips64),
+    DEFINE_FPR (fcsr,        fcsr,  NULL,   gcc_dwarf_fcsr_mips64, gcc_dwarf_fcsr_mips64, LLDB_INVALID_REGNUM,    gdb_fcsr_mips64),
+    DEFINE_FPR (fir,         fir,   NULL,   gcc_dwarf_fir_mips64,  gcc_dwarf_fir_mips64,  LLDB_INVALID_REGNUM,    gdb_fir_mips64)
 };
 static_assert((sizeof(g_register_infos_mips64) / sizeof(g_register_infos_mips64[0])) == k_num_registers_mips64,
     "g_register_infos_mips64 has wrong number of register infos");
 
 #undef DEFINE_GPR
-
-#endif // DECLARE_REGISTER_INFOS_MIPS64_STRUCT
-
+#undef DEFINE_FPR
 #undef GPR_OFFSET
+#undef FPR_OFFSET
 
+#endif // DECLARE_REGISTER_INFOS_MIPS64_STRUCT

source/Plugins/Process/Utility/lldb-mips64-register-enums.h

+//===-- lldb-mips64-register-enums.h -------------------------------*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef lldb_mips64_register_enums_h
+#define lldb_mips64_register_enums_h
+
+namespace lldb_private
+{
+    // LLDB register codes (e.g. RegisterKind == eRegisterKindLLDB)
+
+    //---------------------------------------------------------------------------
+    // Internal codes for all mips registers.
+    //---------------------------------------------------------------------------
+    enum
+    {
+        k_first_gpr_mips,
+        gpr_zero_mips = k_first_gpr_mips,
+        gpr_r1_mips,
+        gpr_r2_mips,
+        gpr_r3_mips,
+        gpr_r4_mips,
+        gpr_r5_mips,
+        gpr_r6_mips,
+        gpr_r7_mips,
+        gpr_r8_mips,
+        gpr_r9_mips,
+        gpr_r10_mips,
+        gpr_r11_mips,
+        gpr_r12_mips,
+        gpr_r13_mips,
+        gpr_r14_mips,
+        gpr_r15_mips,
+        gpr_r16_mips,
+        gpr_r17_mips,
+        gpr_r18_mips,
+        gpr_r19_mips,
+        gpr_r20_mips,
+        gpr_r21_mips,
+        gpr_r22_mips,
+        gpr_r23_mips,
+        gpr_r24_mips,
+        gpr_r25_mips,
+        gpr_r26_mips,
+        gpr_r27_mips,
+        gpr_gp_mips,
+        gpr_sp_mips,
+        gpr_r30_mips,
+        gpr_ra_mips,
+        gpr_mullo_mips,
+        gpr_mulhi_mips,
+        gpr_pc_mips,
+        gpr_badvaddr_mips,
+        gpr_sr_mips,
+        gpr_cause_mips,
+
+        k_last_gpr_mips = gpr_cause_mips,
+
+        k_first_fpr_mips,
+        fpr_f0_mips = k_first_fpr_mips,
+        fpr_f1_mips,
+        fpr_f2_mips,
+        fpr_f3_mips,
+        fpr_f4_mips,
+        fpr_f5_mips,
+        fpr_f6_mips,
+        fpr_f7_mips,
+        fpr_f8_mips,
+        fpr_f9_mips,
+        fpr_f10_mips,
+        fpr_f11_mips,
+        fpr_f12_mips,
+        fpr_f13_mips,
+        fpr_f14_mips,
+        fpr_f15_mips,
+        fpr_f16_mips,
+        fpr_f17_mips,
+        fpr_f18_mips,
+        fpr_f19_mips,
+        fpr_f20_mips,
+        fpr_f21_mips,
+        fpr_f22_mips,
+        fpr_f23_mips,
+        fpr_f24_mips,
+        fpr_f25_mips,
+        fpr_f26_mips,
+        fpr_f27_mips,
+        fpr_f28_mips,
+        fpr_f29_mips,
+        fpr_f30_mips,
+        fpr_f31_mips,
+        fpr_fcsr_mips,
+        fpr_fir_mips,
+        k_last_fpr_mips = fpr_fir_mips,
+
+        k_num_registers_mips,
+        k_num_gpr_registers_mips = k_last_gpr_mips - k_first_gpr_mips + 1,
+        k_num_fpr_registers_mips = k_last_fpr_mips - k_first_fpr_mips + 1,
+        k_num_user_registers_mips = k_num_gpr_registers_mips + k_num_fpr_registers_mips,
+    };
+
+    //---------------------------------------------------------------------------
+    // Internal codes for all mips64 registers.
+    //---------------------------------------------------------------------------
+    enum
+    {
+        k_first_gpr_mips64,
+        gpr_zero_mips64 = k_first_gpr_mips64,
+        gpr_r1_mips64,
+        gpr_r2_mips64,
+        gpr_r3_mips64,
+        gpr_r4_mips64,
+        gpr_r5_mips64,
+        gpr_r6_mips64,
+        gpr_r7_mips64,
+        gpr_r8_mips64,
+        gpr_r9_mips64,
+        gpr_r10_mips64,
+        gpr_r11_mips64,
+        gpr_r12_mips64,
+        gpr_r13_mips64,
+        gpr_r14_mips64,
+        gpr_r15_mips64,
+        gpr_r16_mips64,
+        gpr_r17_mips64,
+        gpr_r18_mips64,
+        gpr_r19_mips64,
+        gpr_r20_mips64,
+        gpr_r21_mips64,
+        gpr_r22_mips64,
+        gpr_r23_mips64,
+        gpr_r24_mips64,
+        gpr_r25_mips64,
+        gpr_r26_mips64,
+        gpr_r27_mips64,
+        gpr_gp_mips64,
+        gpr_sp_mips64,
+        gpr_r30_mips64,
+        gpr_ra_mips64,
+        gpr_mullo_mips64,
+        gpr_mulhi_mips64,
+        gpr_pc_mips64,
+        gpr_badvaddr_mips64,
+        gpr_sr_mips64,
+        gpr_cause_mips64,
+        gpr_ic_mips64,
+        gpr_dummy_mips64,
+
+        k_last_gpr_mips64 = gpr_dummy_mips64,
+
+        k_first_fpr_mips64,
+        fpr_f0_mips64 = k_first_fpr_mips64,
+        fpr_f1_mips64,
+        fpr_f2_mips64,
+        fpr_f3_mips64,
+        fpr_f4_mips64,
+        fpr_f5_mips64,
+        fpr_f6_mips64,
+        fpr_f7_mips64,
+        fpr_f8_mips64,
+        fpr_f9_mips64,
+        fpr_f10_mips64,
+        fpr_f11_mips64,
+        fpr_f12_mips64,
+        fpr_f13_mips64,
+        fpr_f14_mips64,
+        fpr_f15_mips64,
+        fpr_f16_mips64,
+        fpr_f17_mips64,
+        fpr_f18_mips64,
+        fpr_f19_mips64,
+        fpr_f20_mips64,
+        fpr_f21_mips64,
+        fpr_f22_mips64,
+        fpr_f23_mips64,
+        fpr_f24_mips64,
+        fpr_f25_mips64,
+        fpr_f26_mips64,
+        fpr_f27_mips64,
+        fpr_f28_mips64,
+        fpr_f29_mips64,
+        fpr_f30_mips64,
+        fpr_f31_mips64,
+        fpr_fcsr_mips64,
+        fpr_fir_mips64,
+        k_last_fpr_mips64 = fpr_fir_mips64,
+
+        k_num_registers_mips64,
+        k_num_gpr_registers_mips64 = k_last_gpr_mips64 - k_first_gpr_mips64 + 1,
+        k_num_fpr_registers_mips64 = k_last_fpr_mips64 - k_first_fpr_mips64 + 1,
+    };
+}
+
+#endif // #ifndef fpr_mips64_register_enums_h