[MIPS][lldb-server] Add 32-bit register context and read/write FP registers on mips64

[slthakur]

Summary

• Added support for read/write FP registers in FR1 mode.
• Added 32 bit register context for mips32.

[tberghammer]

NativeRegisterContextLinux_mips.cpp and NativeRegisterContextLinux_mips64.cpp are both enabled at the same time (when mips is defined) what will cause a conflict because both implements NativeRegisterContextLinux::CreateHostNativeRegisterContextLinux for creating the appropriate register context. I don't know what is the relationship between mips and mips64 (if they should exist next to each outher as i386 and x86_64 or they are completely different ones as arm and aarch64) but you have to do something to always create the right context and have exactly one CreateHostNativeRegisterContextLinux implementation when mips is defined.

Please upload a revision with full context and where the base revision already contains D9935 to make it easier to review.

source/Core/RegisterValue.cpp

88–111

We shouldn't have architecture specific code in RegisterValue.

If I understand it correctly your problem is that both single and double precision floats can be stored in the same register and you want to display them correctly. I suggest to use alias registers for this issue (eg.: f1 -> hex, flt1 -> float, dbl1 -> double) in the register context so it will work in an architecture independent way. A similar solution is used on i386 and on x86_64 for handling the integer registers with the only difference that in that case you can address both part of the bigger register.

source/Plugins/Process/Utility/RegisterContextLinux_mips.cpp

111–112

These registers should have uint encoding and hex format

[clayborg]

source/Core/RegisterValue.cpp

88–111

RegisterValue.cpp shouldn't have arch specific stuff. Like tberghammer said, just make registers that have different names if needed. But you really shouldn't have to do this as you can view registers using a different format:

(lldb) register read s31
s31 = 2.125
(lldb) register read --format hex s31
S31 = 0x40080000

This would display a float or double register as hex. If you need to show parts of a register you do make different registers. Registers through the GDB remote protocol with qRegisterInfo or the target.xml, can claim they are part of another register (RegisterInfo.value_regs). So if you have a 'f0' register for mips that is a double you can define a register that is "f0" whose size is 64 bits, and then make a "f0_low" (or some other better name) whose values_regs specifies the register number of "f0". When this register is read, it will then read the "f0" register and then take part of that value based off of the offset and size in the RegisterInfo structure.

[slthakur]

Hi @clayborg, @tberghammer,

NativeRegisterContextLinux_mips.cpp and NativeRegisterContextLinux_mips64.cpp are both enabled at the same time (when mips is defined) what will cause a conflict because both implements NativeRegisterContextLinux::CreateHostNativeRegisterContextLinux for creating the appropriate register context.

I will remove the NativeRegisterContextLinux_mips.cpp. NativeRegisterContextLinux_mips64.cpp will work for both mips and mips64.

We shouldn't have architecture specific code in RegisterValue

As @clayborg suggested, we can let the user use the --format option for printing float or double or hex values for floating point registers for now.

I will updated this patch with full context and address all review comments.

Thanks.

[slthakur]

• Shifted code for defining g_register_infos_mips* to RegisterInfos_mips* classes.
• Shifted lldb internals codes for registers to lldb-mips64-register-enums.h.
• Addressed review comments by @tberghammer and @clayborg.

[tberghammer]

The general concept looks good.
For the mips specific part I don't have enough knowledge to verify, but I noticed one serious issue (see inline comment).

source/Plugins/Process/Linux/NativeRegisterContextLinux_mips64.cpp

478–498

• The error message says "failed to read floating point register" after a WriteFPR() call what seems to be wrong.
• You do a write before setting the value of the register from the argument.

Based on the two observation I am not sure if the general concept in the function is correct and those are just 2 typos or if the content of the function is accidentally swapped with the content of a ReadRegister function

[slthakur]

Corrected WriteFPR function.

[slthakur]

Corrected another typo in file name discription in RegisterInfo_mips* files.

[tberghammer]

Looks good, but see 2 minor comments inline

source/Core/ArchSpec.cpp

1161

You are missing a break here (or if it is intentional then please add a comment)

1175

You are missing a break here (or if it is intentional then please add a comment)

[slthakur]

Addressed review comments

[clayborg]

Looks good.

include/lldb/Core/ArchSpec.h

         kCore_hexagon_last   = eCore_hexagon_hexagonv5,
 
         kCore_kalimba_first = eCore_kalimba3,
-        kCore_kalimba_last = eCore_kalimba5
+        kCore_kalimba_last = eCore_kalimba5,
+
+        kCore_mips32_first  = eCore_mips32,
+        kCore_mips32_last   = eCore_mips32r6,
+
+        kCore_mips32el_first  = eCore_mips32el,
+        kCore_mips32el_last   = eCore_mips32r6el,
+
+        kCore_mips64_first  = eCore_mips64,
+        kCore_mips64_last   = eCore_mips64r6,
+
+        kCore_mips64el_first  = eCore_mips64el,
+        kCore_mips64el_last   = eCore_mips64r6el
     };
 
     typedef void (* StopInfoOverrideCallbackType)(lldb_private::Thread &thread);

include/lldb/Core/RegisterValue.h

 // Project includes
 #include "lldb/lldb-public.h"
 #include "lldb/lldb-private.h"
+#include "lldb/Core/ArchSpec.h"
 #include "lldb/Host/Endian.h"
 
 //#define ENABLE_128_BIT_SUPPORT 1

         void
         Clear();
 
+        llvm::Triple m_target_triple;
+
     protected:
 
         RegisterValue::Type m_type;

source/Commands/CommandObjectRegister.cpp

 
                 bool prefix_with_altname = (bool)m_command_options.alternate_name;
                 bool prefix_with_name = !prefix_with_altname;
+                Target *target = exe_ctx.GetTargetPtr ();
+                reg_value.m_target_triple = target->GetArchitecture().GetTriple();
                 reg_value.Dump(&strm, reg_info, prefix_with_name, prefix_with_altname, m_format_options.GetFormat(), 8);
                 if ((reg_info->encoding == eEncodingUint) || (reg_info->encoding == eEncodingSint))
                 {

source/Core/ArchSpec.cpp

     { eByteOrderLittle, 8, 4, 4, llvm::Triple::aarch64, ArchSpec::eCore_arm_aarch64     , "aarch64"   },
 
     // mips32, mips32r2, mips32r3, mips32r5, mips32r6
-    { eByteOrderBig   , 4, 4, 4, llvm::Triple::mips  , ArchSpec::eCore_mips32         , "mips32"      },
-    { eByteOrderBig   , 4, 4, 4, llvm::Triple::mips  , ArchSpec::eCore_mips32r2       , "mips32r2"    },
-    { eByteOrderBig   , 4, 4, 4, llvm::Triple::mips  , ArchSpec::eCore_mips32r3       , "mips32r3"    },
-    { eByteOrderBig   , 4, 4, 4, llvm::Triple::mips  , ArchSpec::eCore_mips32r5       , "mips32r5"    },
-    { eByteOrderBig   , 4, 4, 4, llvm::Triple::mips  , ArchSpec::eCore_mips32r6       , "mips32r6"    },
-    { eByteOrderLittle, 4, 4, 4, llvm::Triple::mipsel, ArchSpec::eCore_mips32el       , "mips32el"    },
-    { eByteOrderLittle, 4, 4, 4, llvm::Triple::mipsel, ArchSpec::eCore_mips32r2el     , "mips32r2el"  },
-    { eByteOrderLittle, 4, 4, 4, llvm::Triple::mipsel, ArchSpec::eCore_mips32r3el     , "mips32r3el"  },
-    { eByteOrderLittle, 4, 4, 4, llvm::Triple::mipsel, ArchSpec::eCore_mips32r5el     , "mips32r5el"  },
-    { eByteOrderLittle, 4, 4, 4, llvm::Triple::mipsel, ArchSpec::eCore_mips32r6el     , "mips32r6el"  },
+    { eByteOrderBig   , 4, 4, 4, llvm::Triple::mips  , ArchSpec::eCore_mips32         , "mips"      },
+    { eByteOrderBig   , 4, 4, 4, llvm::Triple::mips  , ArchSpec::eCore_mips32r2       , "mipsr2"    },
+    { eByteOrderBig   , 4, 4, 4, llvm::Triple::mips  , ArchSpec::eCore_mips32r3       , "mipsr3"    },
+    { eByteOrderBig   , 4, 4, 4, llvm::Triple::mips  , ArchSpec::eCore_mips32r5       , "mipsr5"    },
+    { eByteOrderBig   , 4, 4, 4, llvm::Triple::mips  , ArchSpec::eCore_mips32r6       , "mipsr6"    },
+    { eByteOrderLittle, 4, 4, 4, llvm::Triple::mipsel, ArchSpec::eCore_mips32el       , "mipsel"    },
+    { eByteOrderLittle, 4, 4, 4, llvm::Triple::mipsel, ArchSpec::eCore_mips32r2el     , "mipsr2el"  },
+    { eByteOrderLittle, 4, 4, 4, llvm::Triple::mipsel, ArchSpec::eCore_mips32r3el     , "mipsr3el"  },
+    { eByteOrderLittle, 4, 4, 4, llvm::Triple::mipsel, ArchSpec::eCore_mips32r5el     , "mipsr5el"  },
+    { eByteOrderLittle, 4, 4, 4, llvm::Triple::mipsel, ArchSpec::eCore_mips32r6el     , "mipsr6el"  },
     
     // mips64, mips64r2, mips64r3, mips64r5, mips64r6
     { eByteOrderBig   , 8, 4, 4, llvm::Triple::mips64  , ArchSpec::eCore_mips64         , "mips64"      },

         }
         break;
 
+    case ArchSpec::eCore_mips64:
+    case ArchSpec::eCore_mips64r2:
+    case ArchSpec::eCore_mips64r3:
+    case ArchSpec::eCore_mips64r5:
+    case ArchSpec::eCore_mips64r6:
+        if (!enforce_exact_match)
+        {
+            if (core2 >= ArchSpec::kCore_mips32_first && core2 <= (core1 - 10))
+                return true;
+            if (core2 >= ArchSpec::kCore_mips64_first && core2 <= (core1 - 1))
+                return true;
+            try_inverse = false;
+        }
+    
+    case ArchSpec::eCore_mips64el:
+    case ArchSpec::eCore_mips64r2el:
+    case ArchSpec::eCore_mips64r3el:
+    case ArchSpec::eCore_mips64r5el:
+    case ArchSpec::eCore_mips64r6el:
+        if (!enforce_exact_match)
+        {
+            if (core2 >= ArchSpec::kCore_mips32el_first && core2 <= (core1 - 10))
+                return true;
+            if (core2 >= ArchSpec::kCore_mips64el_first && core2 <= (core1 - 1))
+                return true;
+            try_inverse = false;
+        }
+
     default:
         break;
     }

source/Core/RegisterValue.cpp

 // C++ Includes
 // Other libraries and framework includes
 // Project includes
+#include "llvm/ADT/Triple.h"
 #include "lldb/Core/DataExtractor.h"
 #include "lldb/Core/Error.h"
 #include "lldb/Core/Scalar.h"

         if (format == eFormatDefault)
             format = reg_info->format;
 
+        if (m_target_triple.getArch() == llvm::Triple::mips64 || m_target_triple.getArch() == llvm::Triple::mips64el)
+        {
+                if (reg_info->name[0] == 'f') // Floating point register
+                {
+                    if (reg_info->byte_offset >= 256 && reg_info->byte_offset < 272) // fscr and fir
+                    {
+                        data.Dump (s, 0, eFormatHex, reg_info->byte_size, 1, UINT32_MAX, LLDB_INVALID_ADDRESS, 0, 0);
+                    }
+                    else
+                    {
+                        data.Dump (s, 0, eFormatHex, reg_info->byte_size, 1, UINT32_MAX, LLDB_INVALID_ADDRESS, 0, 0);
+                        s->PutCString ("  flt:\t");
+                        data.Dump (s, 0, eFormatFloat, 4, 1, UINT32_MAX, LLDB_INVALID_ADDRESS, 0, 0);
+                        s->PutCString ("  dbl:  ");
+                        data.Dump (s, 0, eFormatFloat, 8, 1, UINT32_MAX, LLDB_INVALID_ADDRESS, 0, 0);
+                    }
+                }
+                else // General purpose register
+                {
+                    data.Dump (s, 0, format, reg_info->byte_size, 1, UINT32_MAX, LLDB_INVALID_ADDRESS, 0, 0);
+                }
+        }
+        else
+        {
         data.Dump (s, 
                    0,                       // Offset in "data"
                    format,                  // Format to use when dumping

                    LLDB_INVALID_ADDRESS,    // base_addr
                    0,                       // item_bit_size
                    0);                      // item_bit_offset
+        }
         return true;
     }
     return false;

     }
     return false;
 }
-

source/Plugins/Platform/Linux/PlatformLinux.cpp

             case 4: triple.setArchName("mips64"); break;
             case 5: triple.setArchName("hexagon"); break;
             case 6: triple.setArchName("mips"); break;
+            case 7: triple.setArchName("mips64el"); break;
+            case 8: triple.setArchName("mipsel"); break;
             default: return false;
         }
         // Leave the vendor as "llvm::Triple:UnknownVendor" and don't specify the vendor by

source/Plugins/Process/Linux/CMakeLists.txt

   NativeRegisterContextLinux_arm64.cpp
   NativeRegisterContextLinux_x86_64.cpp
   NativeRegisterContextLinux_mips64.cpp
+  NativeRegisterContextLinux_mips.cpp
   NativeThreadLinux.cpp
   ProcessLinux.cpp
   ProcessMonitor.cpp

source/Plugins/Process/Linux/NativeRegisterContextLinux_mips.h

+//===-- NativeRegisterContextLinux_mips.h ---------------------*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+
+#if defined(__mips__)
+
+#ifndef lldb_NativeRegisterContextLinux_mips_h
+#define lldb_NativeRegisterContextLinux_mips_h
+
+#include "Plugins/Process/Linux/NativeRegisterContextLinux.h"
+#include "Plugins/Process/Utility/RegisterContext_mips.h"
+#include "Plugins/Process/Utility/RegisterContextLinux_mips.h"
+
+namespace lldb_private {
+namespace process_linux {
+
+    class NativeProcessLinux;
+
+    // ---------------------------------------------------------------------------
+    // Internal codes for mips GP and FP registers.
+    // ---------------------------------------------------------------------------
+    enum
+    {
+        k_first_gp_reg_mips,
+        gp_reg_r0_mips = k_first_gp_reg_mips,
+        gp_reg_r1_mips,
+        gp_reg_r2_mips,
+        gp_reg_r3_mips,
+        gp_reg_r4_mips,
+        gp_reg_r5_mips,
+        gp_reg_r6_mips,
+        gp_reg_r7_mips,
+        gp_reg_r8_mips,
+        gp_reg_r9_mips,
+        gp_reg_r10_mips,
+        gp_reg_r11_mips,
+        gp_reg_r12_mips,
+        gp_reg_r13_mips,
+        gp_reg_r14_mips,
+        gp_reg_r15_mips,
+        gp_reg_r16_mips,
+        gp_reg_r17_mips,
+        gp_reg_r18_mips,
+        gp_reg_r19_mips,
+        gp_reg_r20_mips,
+        gp_reg_r21_mips,
+        gp_reg_r22_mips,
+        gp_reg_r23_mips,
+        gp_reg_r24_mips,
+        gp_reg_r25_mips,
+        gp_reg_r26_mips,
+        gp_reg_r27_mips,
+        gp_reg_r28_mips,
+        gp_reg_r29_mips,
+        gp_reg_r30_mips,
+        gp_reg_r31_mips,
+        gp_reg_mullo_mips,
+        gp_reg_mulhi_mips,
+        gp_reg_pc_mips,
+        gp_reg_badvaddr_mips,
+        gp_reg_sr_mips,
+        gp_reg_cause_mips,
+        k_last_gp_reg_mips = gp_reg_cause_mips,
+
+        k_first_fp_reg_mips,
+        fp_reg_f0_mips = k_first_fp_reg_mips,
+        fp_reg_f1_mips,
+        fp_reg_f2_mips,
+        fp_reg_f3_mips,
+        fp_reg_f4_mips,
+        fp_reg_f5_mips,
+        fp_reg_f6_mips,
+        fp_reg_f7_mips,
+        fp_reg_f8_mips,
+        fp_reg_f9_mips,
+        fp_reg_f10_mips,
+        fp_reg_f11_mips,
+        fp_reg_f12_mips,
+        fp_reg_f13_mips,
+        fp_reg_f14_mips,
+        fp_reg_f15_mips,
+        fp_reg_f16_mips,
+        fp_reg_f17_mips,
+        fp_reg_f18_mips,
+        fp_reg_f19_mips,
+        fp_reg_f20_mips,
+        fp_reg_f21_mips,
+        fp_reg_f22_mips,
+        fp_reg_f23_mips,
+        fp_reg_f24_mips,
+        fp_reg_f25_mips,
+        fp_reg_f26_mips,
+        fp_reg_f27_mips,
+        fp_reg_f28_mips,
+        fp_reg_f29_mips,
+        fp_reg_f30_mips,
+        fp_reg_f31_mips,
+        fp_reg_fcsr_mips,
+        fp_reg_fir_mips,
+        k_last_fp_reg_mips = fp_reg_fir_mips,
+
+        k_num_gp_reg_mips = k_last_gp_reg_mips - k_first_gp_reg_mips + 1,
+        k_num_fp_reg_mips = k_last_fp_reg_mips - k_first_fp_reg_mips + 1
+    };
+
+    class NativeRegisterContextLinux_mips : public NativeRegisterContextLinux
+    {
+    public:
+        NativeRegisterContextLinux_mips (const ArchSpec& target_arch,
+                                           NativeThreadProtocol &native_thread,
+                                           uint32_t concrete_frame_idx);
+
+        uint32_t
+        GetRegisterSetCount () const override;
+
+        const RegisterSet *
+        GetRegisterSet (uint32_t set_index) const override;
+
+        Error
+        ReadRegister (const RegisterInfo *reg_info, RegisterValue &reg_value) override;
+
+        Error
+        WriteRegister (const RegisterInfo *reg_info, const RegisterValue &reg_value) override;
+
+        Error
+        ReadAllRegisterValues (lldb::DataBufferSP &data_sp) override;
+
+        Error
+        WriteAllRegisterValues (const lldb::DataBufferSP &data_sp) override;
+
+        Error
+        IsWatchpointHit (uint8_t wp_index);
+
+        Error
+        IsWatchpointVacant (uint32_t wp_index);
+
+        bool
+        ClearHardwareWatchpoint (uint32_t wp_index) override;
+
+        Error
+        ClearAllHardwareWatchpoints ();
+
+        Error
+        SetHardwareWatchpointWithIndex (lldb::addr_t addr, size_t size,
+                uint32_t watch_flags, uint32_t wp_index);
+
+        uint32_t
+        SetHardwareWatchpoint (lldb::addr_t addr, size_t size,
+                uint32_t watch_flags) override;
+
+        lldb::addr_t
+        GetWatchpointAddress (uint32_t wp_index);
+
+        uint32_t
+        NumSupportedHardwareWatchpoints () override;
+
+    protected:
+        NativeProcessLinux::OperationUP
+        GetReadRegisterValueOperation(uint32_t offset,
+                                      const char* reg_name,
+                                      uint32_t size,
+                                      RegisterValue &value) override;
+
+        NativeProcessLinux::OperationUP
+        GetWriteRegisterValueOperation(uint32_t offset,
+                                       const char* reg_name,
+                                       const RegisterValue &value) override;
+    };
+
+} // namespace process_linux
+} // namespace lldb_private
+
+#endif // #ifndef lldb_NativeRegisterContextLinux_mips_h
+
+#endif

source/Plugins/Process/Linux/NativeRegisterContextLinux_mips.cpp

+//===-- NativeRegisterContextLinux_mips.cpp ---------------*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+
+#if defined(__mips__)
+
+#include "NativeRegisterContextLinux_mips.h"
+
+// C Includes
+// C++ Includes
+
+// Other libraries and framework includes
+#include "lldb/Core/Error.h"
+#include "lldb/Core/RegisterValue.h"
+
+#include "Plugins/Process/Linux/NativeProcessLinux.h"
+#include "Plugins/Process/Linux/Procfs.h"
+#include "Plugins/Process/Utility/RegisterContextLinux_mips.h"
+
+using namespace lldb_private;
+using namespace lldb_private::process_linux;
+
+// ----------------------------------------------------------------------------
+// Private namespace.
+// ----------------------------------------------------------------------------
+
+namespace
+{
+    // mips general purpose registers.
+    const uint32_t
+    g_gp_regnums_mips[] =
+    {
+        gp_reg_r0_mips,
+        gp_reg_r1_mips,
+        gp_reg_r2_mips,
+        gp_reg_r3_mips,
+        gp_reg_r4_mips,
+        gp_reg_r5_mips,
+        gp_reg_r6_mips,
+        gp_reg_r7_mips,
+        gp_reg_r8_mips,
+        gp_reg_r9_mips,
+        gp_reg_r10_mips,
+        gp_reg_r11_mips,
+        gp_reg_r12_mips,
+        gp_reg_r13_mips,
+        gp_reg_r14_mips,
+        gp_reg_r15_mips,
+        gp_reg_r16_mips,
+        gp_reg_r17_mips,
+        gp_reg_r18_mips,
+        gp_reg_r19_mips,
+        gp_reg_r20_mips,
+        gp_reg_r21_mips,
+        gp_reg_r22_mips,
+        gp_reg_r23_mips,
+        gp_reg_r24_mips,
+        gp_reg_r25_mips,
+        gp_reg_r26_mips,
+        gp_reg_r27_mips,
+        gp_reg_r28_mips,
+        gp_reg_r29_mips,
+        gp_reg_r30_mips,
+        gp_reg_r31_mips,
+        gp_reg_mullo_mips,
+        gp_reg_mulhi_mips,
+        gp_reg_pc_mips,
+        gp_reg_badvaddr_mips,
+        gp_reg_sr_mips,
+        gp_reg_cause_mips,
+        LLDB_INVALID_REGNUM     // register sets need to end with this flag
+    };
+
+    static_assert((sizeof(g_gp_regnums_mips) / sizeof(g_gp_regnums_mips[0])) - 1 == k_num_gp_reg_mips,
+                  "g_gp_regnums_mips has wrong number of register infos");
+
+    // mips floating point registers.
+    const uint32_t
+    g_fp_regnums_mips[] =
+    {
+        fp_reg_f0_mips,
+        fp_reg_f1_mips,
+        fp_reg_f2_mips,
+        fp_reg_f3_mips,
+        fp_reg_f4_mips,
+        fp_reg_f5_mips,
+        fp_reg_f6_mips,
+        fp_reg_f7_mips,
+        fp_reg_f8_mips,
+        fp_reg_f9_mips,
+        fp_reg_f10_mips,
+        fp_reg_f11_mips,
+        fp_reg_f12_mips,
+        fp_reg_f13_mips,
+        fp_reg_f14_mips,
+        fp_reg_f15_mips,
+        fp_reg_f16_mips,
+        fp_reg_f17_mips,
+        fp_reg_f18_mips,
+        fp_reg_f19_mips,
+        fp_reg_f20_mips,
+        fp_reg_f21_mips,
+        fp_reg_f22_mips,
+        fp_reg_f23_mips,
+        fp_reg_f24_mips,
+        fp_reg_f25_mips,
+        fp_reg_f26_mips,
+        fp_reg_f27_mips,
+        fp_reg_f28_mips,
+        fp_reg_f29_mips,
+        fp_reg_f30_mips,
+        fp_reg_f31_mips,
+        fp_reg_fcsr_mips,
+        fp_reg_fir_mips,
+        LLDB_INVALID_REGNUM     // register sets need to end with this flag
+    };
+
+    static_assert((sizeof(g_fp_regnums_mips) / sizeof(g_fp_regnums_mips[0])) - 1 == k_num_fp_reg_mips,
+                  "g_fp_regnums_mips has wrong number of register infos");
+
+    // Number of register sets provided by this context.
+    enum
+    {
+        k_num_register_sets = 2
+    };
+
+    // Register sets for mips.
+    static const RegisterSet
+    g_reg_sets_mips[k_num_register_sets] =
+    {
+        { "General Purpose Registers",  "gpr", k_num_gp_reg_mips, g_gp_regnums_mips },
+        { "Floating Point Registers",   "fpu", k_num_fp_reg_mips, g_fp_regnums_mips }
+    };
+
+    class ReadRegOperation : public NativeProcessLinux::Operation
+    {
+    public:
+        ReadRegOperation(lldb::tid_t tid, uint32_t offset, RegisterValue &value) :
+            m_tid(tid),
+            m_offset(static_cast<uintptr_t>(offset)),
+            m_value(value)
+        { }
+
+        void
+        Execute(NativeProcessLinux *monitor) override;
+
+    private:
+        lldb::tid_t m_tid;
+        uintptr_t m_offset;
+        RegisterValue &m_value;
+    };
+
+    class WriteRegOperation : public NativeProcessLinux::Operation
+    {
+    public:
+        WriteRegOperation(lldb::tid_t tid, unsigned offset, const char *reg_name, const RegisterValue &value) :
+            m_tid(tid),
+            m_offset(offset),
+            m_reg_name(reg_name),
+            m_value(value)
+        { }
+
+        void
+        Execute(NativeProcessLinux *monitor) override;
+
+    private:
+        lldb::tid_t m_tid;
+        uintptr_t m_offset;
+        const char *m_reg_name;
+        const RegisterValue &m_value;
+    };
+
+} // end of anonymous namespace
+
+void
+ReadRegOperation::Execute(NativeProcessLinux *monitor)
+{
+    elf_gregset_t regs;
+    NativeProcessLinux::PtraceWrapper(PTRACE_GETREGS, m_tid, NULL, &regs, sizeof regs, m_error);
+    if (m_error.Success())
+    {
+        lldb_private::ArchSpec arch;
+        if (monitor->GetArchitecture(arch))
+            m_value.SetBytes((void *)(((unsigned char *)(regs)) + m_offset), 8, arch.GetByteOrder());
+        else
+            m_error.SetErrorString("failed to get architecture");
+    }
+}
+
+void
+WriteRegOperation::Execute(NativeProcessLinux *monitor)
+{
+    elf_gregset_t regs;
+    NativeProcessLinux::PtraceWrapper(PTRACE_GETREGS, m_tid, NULL, &regs, sizeof regs, m_error);
+    if (m_error.Success())
+    {
+        ::memcpy((void *)(((unsigned char *)(&regs)) + m_offset), m_value.GetBytes(), 8);
+        NativeProcessLinux::PtraceWrapper(PTRACE_SETREGS, m_tid, NULL, &regs, sizeof regs, m_error);
+    }
+}
+
+NativeRegisterContextLinux*
+NativeRegisterContextLinux::CreateHostNativeRegisterContextLinux(const ArchSpec& target_arch,
+                                                                 NativeThreadProtocol &native_thread,
+                                                                 uint32_t concrete_frame_idx)
+{
+    return new NativeRegisterContextLinux_mips(target_arch, native_thread, concrete_frame_idx);
+}
+
+// ----------------------------------------------------------------------------
+// NativeRegisterContextLinux_mips members.
+// ----------------------------------------------------------------------------
+
+NativeRegisterContextLinux_mips::NativeRegisterContextLinux_mips (const ArchSpec& target_arch,
+                                                                      NativeThreadProtocol &native_thread, 
+                                                                      uint32_t concrete_frame_idx) :
+    NativeRegisterContextLinux (native_thread, concrete_frame_idx, new RegisterContextLinux_mips (target_arch))
+{
+}
+
+uint32_t
+NativeRegisterContextLinux_mips::GetRegisterSetCount () const
+{
+    return k_num_register_sets;
+}
+
+const lldb_private::RegisterSet *
+NativeRegisterContextLinux_mips::GetRegisterSet (uint32_t set_index) const
+{
+    if (set_index >= k_num_register_sets)
+        return nullptr;
+
+    switch (GetRegisterInfoInterface ().GetTargetArchitecture ().GetMachine ())
+    {
+        case llvm::Triple::mips:
+        case llvm::Triple::mipsel:
+            return &g_reg_sets_mips[set_index];
+        default:
+            assert (false && "Unhandled target architecture.");
+            return nullptr;
+    }
+
+    return nullptr;
+}
+
+lldb_private::Error
+NativeRegisterContextLinux_mips::ReadRegister (const RegisterInfo *reg_info, RegisterValue &reg_value)
+{
+    Error error;
+    error.SetErrorString ("MIPS TODO: NativeRegisterContextLinux_mips::ReadRegister not implemented");
+    return error;
+}
+
+lldb_private::Error
+NativeRegisterContextLinux_mips::WriteRegister (const RegisterInfo *reg_info, const RegisterValue &reg_value)
+{
+    Error error;
+    error.SetErrorString ("MIPS TODO: NativeRegisterContextLinux_mips::WriteRegister not implemented");
+    return error;
+}
+
+lldb_private::Error
+NativeRegisterContextLinux_mips::ReadAllRegisterValues (lldb::DataBufferSP &data_sp)
+{
+    Error error;
+    error.SetErrorString ("MIPS TODO: NativeRegisterContextLinux_mips::ReadAllRegisterValues not implemented");
+    return error;
+}
+
+lldb_private::Error
+NativeRegisterContextLinux_mips::WriteAllRegisterValues (const lldb::DataBufferSP &data_sp)
+{
+    Error error;
+    error.SetErrorString ("MIPS TODO: NativeRegisterContextLinux_mips::WriteAllRegisterValues not implemented");
+    return error;
+}
+
+Error
+NativeRegisterContextLinux_mips::IsWatchpointHit (uint8_t wp_index)
+{
+    Error error;
+    error.SetErrorString ("MIPS TODO: NativeRegisterContextLinux_mips::IsWatchpointHit not implemented");
+    return error;
+}
+
+Error
+NativeRegisterContextLinux_mips::IsWatchpointVacant (uint32_t wp_index)
+{
+    Error error;
+    error.SetErrorString ("MIPS TODO: NativeRegisterContextLinux_mips::IsWatchpointVacant not implemented");
+    return error;
+}
+
+bool
+NativeRegisterContextLinux_mips::ClearHardwareWatchpoint (uint32_t wp_index)
+{
+    return false;
+}
+
+Error
+NativeRegisterContextLinux_mips::ClearAllHardwareWatchpoints ()
+{
+    Error error;
+    error.SetErrorString ("MIPS TODO: NativeRegisterContextLinux_mips::ClearAllHardwareWatchpoints not implemented");
+    return error;
+}
+
+Error
+NativeRegisterContextLinux_mips::SetHardwareWatchpointWithIndex (
+        lldb::addr_t addr, size_t size, uint32_t watch_flags, uint32_t wp_index) 
+{
+    Error error;
+    error.SetErrorString ("MIPS TODO: NativeRegisterContextLinux_mips::SetHardwareWatchpointWithIndex not implemented");
+    return error;
+}
+
+uint32_t
+NativeRegisterContextLinux_mips::SetHardwareWatchpoint (
+        lldb::addr_t addr, size_t size, uint32_t watch_flags)
+{
+    return LLDB_INVALID_INDEX32;
+}
+
+lldb::addr_t
+NativeRegisterContextLinux_mips::GetWatchpointAddress (uint32_t wp_index)
+{
+    return LLDB_INVALID_ADDRESS;
+}
+
+uint32_t
+NativeRegisterContextLinux_mips::NumSupportedHardwareWatchpoints ()
+{
+    return 0;
+}
+
+NativeProcessLinux::OperationUP
+NativeRegisterContextLinux_mips::GetReadRegisterValueOperation(uint32_t offset,
+                                                                 const char* reg_name,
+                                                                 uint32_t size,
+                                                                 RegisterValue &value)
+{
+    return NativeProcessLinux::OperationUP(new ReadRegOperation(m_thread.GetID(), offset, value));
+}
+
+NativeProcessLinux::OperationUP
+NativeRegisterContextLinux_mips::GetWriteRegisterValueOperation(uint32_t offset,
+                                                                  const char* reg_name,
+                                                                  const RegisterValue &value)
+{
+    return NativeProcessLinux::OperationUP(new WriteRegOperation(m_thread.GetID(), offset, reg_name, value));
+}
+
+#endif

source/Plugins/Process/Linux/NativeRegisterContextLinux_mips64.h

     class NativeProcessLinux;
 
     // ---------------------------------------------------------------------------
-    // Internal codes for mips64 GP registers.
+    // Internal codes for mips64 GP and FP registers.
     // ---------------------------------------------------------------------------
     enum
     {

         gp_reg_badvaddr_mips64,
         gp_reg_sr_mips64,
         gp_reg_cause_mips64,
-        k_num_gp_reg_mips64,
+        k_last_gp_reg_mips64 = gp_reg_cause_mips64,
+
+        k_first_fp_reg_mips64,
+        fp_reg_f0_mips64 = k_first_fp_reg_mips64,
+        fp_reg_f1_mips64,
+        fp_reg_f2_mips64,
+        fp_reg_f3_mips64,
+        fp_reg_f4_mips64,
+        fp_reg_f5_mips64,
+        fp_reg_f6_mips64,
+        fp_reg_f7_mips64,
+        fp_reg_f8_mips64,
+        fp_reg_f9_mips64,
+        fp_reg_f10_mips64,
+        fp_reg_f11_mips64,
+        fp_reg_f12_mips64,
+        fp_reg_f13_mips64,
+        fp_reg_f14_mips64,
+        fp_reg_f15_mips64,
+        fp_reg_f16_mips64,
+        fp_reg_f17_mips64,
+        fp_reg_f18_mips64,
+        fp_reg_f19_mips64,
+        fp_reg_f20_mips64,
+        fp_reg_f21_mips64,
+        fp_reg_f22_mips64,
+        fp_reg_f23_mips64,
+        fp_reg_f24_mips64,
+        fp_reg_f25_mips64,
+        fp_reg_f26_mips64,
+        fp_reg_f27_mips64,
+        fp_reg_f28_mips64,
+        fp_reg_f29_mips64,
+        fp_reg_f30_mips64,
+        fp_reg_f31_mips64,
+        fp_reg_fcsr_mips64,
+        fp_reg_fir_mips64,
+        k_last_fp_reg_mips64 = fp_reg_fir_mips64,
+
+        k_num_gp_reg_mips64 = k_last_gp_reg_mips64 - k_first_gp_reg_mips64 + 1,
+        k_num_fp_reg_mips64 = k_last_fp_reg_mips64 - k_first_fp_reg_mips64 + 1
     };
 
     class NativeRegisterContextLinux_mips64 : public NativeRegisterContextRegisterInfo

 
     private:
 
+        ldb_private::Error 
+        ReadGPR();
+
+        lldb_private::Error
+        WriteGPR();
+
         lldb_private::Error
-        WriteRegister(const uint32_t reg, const RegisterValue &value);
+        ReadFPR();
 
         lldb_private::Error
-        ReadRegisterRaw (uint32_t reg_index, RegisterValue &reg_value);
+        WriteFPR();
+
+        bool
+        IsFPR(uint32_t reg_index) const;
+
+        void*
+        GetGPRBuffer() override { return &m_gpr_mips64; }
+
+        void*
+        GetFPRBuffer() override { return &m_fpr_mips64; }
+
+        size_t
+        GetFPRSize() override { return sizeof(m_fpr_mips64); }
+
+    private:
+        uint64_t m_gpr_mips64[k_num_gp_reg_mips64];
+
+        FPR_mips64 m_fpr_mips64;
     };
 
 } // namespace process_linux

source/Plugins/Process/Linux/NativeRegisterContextLinux_mips64.cpp

 #include "lldb/Core/DataBufferHeap.h"
 #include "lldb/Core/Error.h"
 #include "lldb/Core/RegisterValue.h"
-#include "lldb/Host/common/NativeProcessProtocol.h"
-#include "lldb/Host/common/NativeThreadProtocol.h"
+#include "lldb/Core/Log.h"
+#include "lldb/Core/DataBufferHeap.h"
+#include "lldb/Host/HostInfo.h"
+
 #include "Plugins/Process/Linux/NativeProcessLinux.h"
 
 using namespace lldb_private;

     static_assert((sizeof(g_gp_regnums_mips64) / sizeof(g_gp_regnums_mips64[0])) - 1 == k_num_gp_reg_mips64,
                   "g_gp_regnums_mips64 has wrong number of register infos");
 
+    // mips64 floating point registers.
+    const uint32_t
+    g_fp_regnums_mips64[] =
+    {
+        fp_reg_f0_mips64,
+        fp_reg_f1_mips64,
+        fp_reg_f2_mips64,
+        fp_reg_f3_mips64,
+        fp_reg_f4_mips64,
+        fp_reg_f5_mips64,
+        fp_reg_f6_mips64,
+        fp_reg_f7_mips64,
+        fp_reg_f8_mips64,
+        fp_reg_f9_mips64,
+        fp_reg_f10_mips64,
+        fp_reg_f11_mips64,
+        fp_reg_f12_mips64,
+        fp_reg_f13_mips64,
+        fp_reg_f14_mips64,
+        fp_reg_f15_mips64,
+        fp_reg_f16_mips64,
+        fp_reg_f17_mips64,
+        fp_reg_f18_mips64,
+        fp_reg_f19_mips64,
+        fp_reg_f20_mips64,
+        fp_reg_f21_mips64,
+        fp_reg_f22_mips64,
+        fp_reg_f23_mips64,
+        fp_reg_f24_mips64,
+        fp_reg_f25_mips64,
+        fp_reg_f26_mips64,
+        fp_reg_f27_mips64,
+        fp_reg_f28_mips64,
+        fp_reg_f29_mips64,
+        fp_reg_f30_mips64,
+        fp_reg_f31_mips64,
+        fp_reg_fcsr_mips64,
+        fp_reg_fir_mips64,
+        LLDB_INVALID_REGNUM     // register sets need to end with this flag
+    };
+
+    static_assert((sizeof(g_fp_regnums_mips64) / sizeof(g_fp_regnums_mips64[0])) - 1 == k_num_fp_reg_mips64,
+                  "g_fp_regnums_mips64 has wrong number of register infos");
+
+
     // Number of register sets provided by this context.
     enum
     {
-        k_num_register_sets = 1
+        k_num_register_sets = 2
     };
 
     // Register sets for mips64.
     static const RegisterSet
     g_reg_sets_mips64[k_num_register_sets] =
     {
-        { "General Purpose Registers",  "gpr", k_num_gp_reg_mips64, g_gp_regnums_mips64 }
+        { "General Purpose Registers",  "gpr", k_num_gp_reg_mips64, g_gp_regnums_mips64 },
+        { "Floating Point Registers",   "fpu", k_num_fp_reg_mips64, g_fp_regnums_mips64 }
     };
 }
 
+#define REG_CONTEXT_SIZE (GetRegisterInfoInterface ().GetGPRSize () + sizeof(FPR_mips64))
+
 // ----------------------------------------------------------------------------
 // NativeRegisterContextLinux_mips64 members.
 // ----------------------------------------------------------------------------

         uint32_t concrete_frame_idx, RegisterInfoInterface *reg_info_interface_p) :
     NativeRegisterContextRegisterInfo (native_thread, concrete_frame_idx, reg_info_interface_p)
 {
+    // Clear out the FPR state.
+    ::memset(&m_fpr_mips64, 0, sizeof(FPR_mips64));
 }
 
 uint32_t

     {
         case llvm::Triple::mips64:
         case llvm::Triple::mips64el:
+        case llvm::Triple::mips:
+        case llvm::Triple::mipsel:
             return &g_reg_sets_mips64[set_index];
         default:
             assert (false && "Unhandled target architecture.");

 }
 
 lldb_private::Error
-NativeRegisterContextLinux_mips64::ReadRegisterRaw (uint32_t reg_index, RegisterValue &reg_value)
+NativeRegisterContextLinux_mips64::ReadRegister (const RegisterInfo *reg_info, RegisterValue &reg_value)
 {
     Error error;
 
-    const RegisterInfo *const reg_info = GetRegisterInfoAtIndex (reg_index);
     if (!reg_info)
     {
-        error.SetErrorStringWithFormat ("register %" PRIu32 " not found", reg_index);
+        error.SetErrorString ("reg_info NULL");
         return error;
     }
 
-    NativeProcessProtocolSP process_sp (m_thread.GetProcess ());
-    if (!process_sp)
+    const uint32_t reg = reg_info->kinds[lldb::eRegisterKindLLDB];
+    if (reg == LLDB_INVALID_REGNUM)
     {
-        error.SetErrorString ("NativeProcessProtocol is NULL");
+        // This is likely an internal register for lldb use only and should not be directly queried.
+        error.SetErrorStringWithFormat ("register \"%s\" is an internal-only lldb register, cannot read directly", reg_info->name);
         return error;
     }
 
-    NativeProcessLinux *const process_p = reinterpret_cast<NativeProcessLinux*> (process_sp.get ());
-    return process_p->ReadRegisterValue(m_thread.GetID(),
-                                        reg_info->byte_offset,
-                                        reg_info->name,
-                                        reg_info->byte_size,
-                                        reg_value);
+    if (IsFPR(reg))
+    {
+        error = ReadFPR();
+        if (!error.Success())
+        {
+            error.SetErrorString ("failed to read floating point register");
+            return error;
+        }
+        assert (reg_info->byte_offset < sizeof(FPR_mips64));
+        uint8_t *src = (uint8_t *)&m_fpr_mips64 + reg_info->byte_offset;
+        switch (reg_info->byte_size)
+        {
+            case 4:
+                reg_value.SetUInt32(*(uint32_t *)src);
+                break;
+            case 8:
+                reg_value.SetUInt64(*(uint64_t *)src);
+                break;
+            default:
+                assert(false && "Unhandled data size.");
+                error.SetErrorStringWithFormat ("unhandled byte size: %" PRIu32, reg_info->byte_size);
+                break;
+        }
+    }
+    else
+    {
+        error = ReadRegisterRaw(reg, reg_value);
+        if (error.Success())
+        {
+            // If our return byte size was greater than the return value reg size, then
+            // use the type specified by reg_info rather than the uint64_t default
+            if (reg_value.GetByteSize() > reg_info->byte_size)
+                reg_value.SetType(reg_info);
+        }
+    }
+
+    return error;
 }
 
 lldb_private::Error
-NativeRegisterContextLinux_mips64::ReadRegister (const RegisterInfo *reg_info, RegisterValue &reg_value)
+NativeRegisterContextLinux_mips64::WriteRegister (const RegisterInfo *reg_info, const RegisterValue &reg_value)
 {
     Error error;
 
-    if (!reg_info)
+    assert (reg_info && "reg_info is null");
+
+    const uint32_t reg_index = reg_info->kinds[lldb::eRegisterKindLLDB];
+
+    if (reg_index == LLDB_INVALID_REGNUM)
+        return Error ("no lldb regnum for %s", reg_info && reg_info->name ? reg_info->name : "<unknown register>");
+
+    if (IsFPR(reg_index))
     {
-        error.SetErrorString ("reg_info NULL");
+        error = ReadFPR();            
+        if (!error.Success())
+        {
+            error.SetErrorString ("failed to read floating point register");
+            return error;
+        }
+        assert (reg_info->byte_offset < sizeof(FPR_mips64));
+        uint8_t *dst = (uint8_t *)&m_fpr_mips64 + reg_info->byte_offset;
+        switch (reg_info->byte_size)
+        {
+            case 4:
+                *(uint32_t *)dst = reg_value.GetAsUInt32();
+                break;
+            case 8:
+                *(uint64_t *)dst = reg_value.GetAsUInt64();
+                break;
+            default:
+                assert(false && "Unhandled data size.");
+                error.SetErrorStringWithFormat ("unhandled byte size: %" PRIu32, reg_info->byte_size);
+                break;
+        }
+    }
+    else
+    {
+        error = WriteRegisterRaw(reg_index, reg_value);
+    }
+
+    return error;
+}
+
+Error
+NativeRegisterContextLinux_mips64::ReadAllRegisterValues (lldb::DataBufferSP &data_sp)
+{
+    Error error;
+
+    data_sp.reset (new DataBufferHeap (REG_CONTEXT_SIZE, 0));
+    if (!data_sp)
+    {
+        error.SetErrorStringWithFormat ("failed to allocate DataBufferHeap instance of size %" PRIu64, REG_CONTEXT_SIZE);
         return error;
     }
 
-    const uint32_t reg = reg_info->kinds[lldb::eRegisterKindLLDB];
-    if (reg == LLDB_INVALID_REGNUM)
+    error = ReadGPR();
+    if (!error.Success())
     {
-        // This is likely an internal register for lldb use only and should not be directly queried.
-        error.SetErrorStringWithFormat ("register \"%s\" is an internal-only lldb register, cannot read directly", reg_info->name);
+        error.SetErrorString ("ReadGPR() failed");
         return error;
     }
 
-    error = ReadRegisterRaw(reg, reg_value);
+    error = ReadFPR();
+    if (!error.Success())
+    {
+        error.SetErrorString ("ReadFPR() failed");
+        return error;
+    }
 
-    if (error.Success ())
+    uint8_t *dst = data_sp->GetBytes ();
+    if (dst == nullptr)
     {
-        // If our return byte size was greater than the return value reg size, then
-        // use the type specified by reg_info rather than the uint64_t default
-        if (reg_value.GetByteSize() > reg_info->byte_size)
-            reg_value.SetType(reg_info);
+        error.SetErrorStringWithFormat ("DataBufferHeap instance of size %" PRIu64 " returned a null pointer", REG_CONTEXT_SIZE);
+        return error;
     }
 
+    ::memcpy (dst, &m_gpr_mips64, GetRegisterInfoInterface ().GetGPRSize ());
+    dst += GetRegisterInfoInterface ().GetGPRSize ();
+
+    ::memcpy (dst, &m_fpr_mips64, sizeof(FPR_mips64));
+
     return error;
 }
 
-lldb_private::Error
-NativeRegisterContextLinux_mips64::WriteRegister(const uint32_t reg,
-                                                 const RegisterValue &value)
+Error
+NativeRegisterContextLinux_mips64::WriteAllRegisterValues (const lldb::DataBufferSP &data_sp)
 {
     Error error;
 
-    uint32_t reg_to_write = reg;
-    RegisterValue value_to_write = value;
-
-    NativeProcessProtocolSP process_sp (m_thread.GetProcess ());
-    if (!process_sp)
+    if (!data_sp)
     {
-        error.SetErrorString ("NativeProcessProtocol is NULL");
+        error.SetErrorStringWithFormat ("NativeRegisterContextLinux_mips64::%s invalid data_sp provided", __FUNCTION__);
         return error;
     }
 
-    const RegisterInfo *const register_to_write_info_p = GetRegisterInfoAtIndex (reg_to_write);
-    assert (register_to_write_info_p && "register to write does not have valid RegisterInfo");
-    if (!register_to_write_info_p)
+    if (data_sp->GetByteSize () != REG_CONTEXT_SIZE)
     {
-        error.SetErrorStringWithFormat ("NativeRegisterContextLinux_mips64::%s failed to get RegisterInfo for write register index %" PRIu32, __FUNCTION__, reg_to_write);
+        error.SetErrorStringWithFormat ("NativeRegisterContextLinux_mips64::%s data_sp contained mismatched data size, expected %" PRIu64 ", actual %" PRIu64, __FUNCTION__, REG_CONTEXT_SIZE, data_sp->GetByteSize ());
         return error;
     }
 
-    NativeProcessLinux *const process_p = reinterpret_cast<NativeProcessLinux*> (process_sp.get ());
-    return process_p->WriteRegisterValue(m_thread.GetID(),
-                                         register_to_write_info_p->byte_offset,
-                                         register_to_write_info_p->name,
-                                         value_to_write);
-}
 
+    uint8_t *src = data_sp->GetBytes ();
+    if (src == nullptr)
+    {
+        error.SetErrorStringWithFormat ("NativeRegisterContextLinux_mips64::%s DataBuffer::GetBytes() returned a null pointer", __FUNCTION__);
+        return error;
+    }
+    ::memcpy (&m_gpr_mips64, src, GetRegisterInfoInterface ().GetGPRSize ());
+    src += GetRegisterInfoInterface ().GetGPRSize ();
 
+    ::memcpy (&m_fpr_mips64, src, sizeof(FPR_mips64));
 
-lldb_private::Error
-NativeRegisterContextLinux_mips64::WriteRegister (const RegisterInfo *reg_info, const RegisterValue &reg_value)
+    error = WriteGPR();
+    if (!error.Success())
     {
-    assert (reg_info && "reg_info is null");
+        error.SetErrorStringWithFormat ("NativeRegisterContextLinux_mips64::%s WriteGPR() failed", __FUNCTION__);
+        return error;
+    }
 
-    const uint32_t reg_index = reg_info->kinds[lldb::eRegisterKindLLDB];
+    error = WriteGPR();
+    if (!error.Success())
+    {
+        error.SetErrorStringWithFormat ("NativeRegisterContextLinux_mips64::%s WriteFPR() failed", __FUNCTION__);
+        return error;
+    }
 
-    if (reg_index == LLDB_INVALID_REGNUM)
-        return Error ("no lldb regnum for %s", reg_info && reg_info->name ? reg_info->name : "<unknown register>");
+    return error;
+}
 
-    return WriteRegister(reg_index, reg_value);
+lldb_private::Error
+NativeRegisterContextLinux_mips64::ReadGPR()
+{
+    return NativeRegisterContextLinux::ReadGPR();
 }
 
-Error
-NativeRegisterContextLinux_mips64::ReadAllRegisterValues (lldb::DataBufferSP &data_sp)
+lldb_private::Error
+NativeRegisterContextLinux_mips64::WriteGPR()
 {
-    Error error;
-    error.SetErrorString ("MIPS TODO: NativeRegisterContextLinux_mips64::ReadAllRegisterValues not implemented");
-    return error;
+    return NativeRegisterContextLinux::WriteGPR();
 }
 
-Error
-NativeRegisterContextLinux_mips64::WriteAllRegisterValues (const lldb::DataBufferSP &data_sp)
+lldb_private::Error
+NativeRegisterContextLinux_mips64::ReadFPR ()
 {
-    Error error;
-    error.SetErrorString ("MIPS TODO: NativeRegisterContextLinux_mips64::WriteAllRegisterValues not implemented");
-    return error;
+    return NativeRegisterContextLinux::ReadFPR();
+}       
+    
+lldb_private::Error
+NativeRegisterContextLinux_mips64::WriteFPR()
+{
+    return NativeRegisterContextLinux::WriteFPR();
+}       
+    
+bool
+NativeRegisterContextLinux_mips64::IsFPR(uint32_t reg_index) const
+{
+    return (k_first_fp_reg_mips64 <= reg_index && reg_index <= k_last_fp_reg_mips64);
 }
 
 Error

source/Plugins/Process/Linux/NativeThreadLinux.cpp

 #include "NativeRegisterContextLinux_arm64.h"
 #include "NativeRegisterContextLinux_x86_64.h"
 #include "NativeRegisterContextLinux_mips64.h"
+#include "NativeRegisterContextLinux_mips.h"
 
 #include "lldb/Core/Log.h"
 #include "lldb/Core/State.h"

source/Plugins/Process/Utility/CMakeLists.txt

   RegisterContextLinux_i386.cpp
   RegisterContextLinux_x86_64.cpp
   RegisterContextLinux_mips64.cpp
+  RegisterContextLinux_mips.cpp
   RegisterContextLLDB.cpp
   RegisterContextMacOSXFrameBackchain.cpp
   RegisterContextMach_arm.cpp

source/Plugins/Process/Utility/RegisterContextLinux_mips.h

+//===-- RegisterContextLinux_mips.h ---------------------------*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+
+#if defined(__mips__)
+
+#ifndef liblldb_RegisterContextLinux_mips_H_
+#define liblldb_RegisterContextLinux_mips_H_
+
+#include "lldb/lldb-private.h"
+#include "RegisterInfoInterface.h"
+
+// GP registers
+struct GPR_mips
+{
+    uint32_t    gp_reg[32];
+    uint32_t    mul_lo;
+    uint32_t    mul_hi;
+    uint32_t    cp0_epc;
+    uint32_t    cp0_badvaddr;
+    uint32_t    cp0_status;
+    uint32_t    cp0_cause;
+};
+
+// FP registers
+struct FPR_mips
+{
+    uint32_t    fp_reg[32];
+    uint32_t    fcsr;        /* FPU status register */
+    uint32_t    fir;        /* FPU control register */
+};
+
+class RegisterContextLinux_mips
+    : public lldb_private::RegisterInfoInterface
+{
+public:
+    RegisterContextLinux_mips(const lldb_private::ArchSpec &target_arch);
+
+    size_t
+    GetGPRSize() const override;
+
+    const lldb_private::RegisterInfo *
+    GetRegisterInfo() const override;
+
+    uint32_t
+    GetRegisterCount () const override;
+
+private:
+    const lldb_private::RegisterInfo *m_register_info_p;
+    uint32_t m_register_info_count;
+};
+
+#endif
+
+#endif

source/Plugins/Process/Utility/RegisterContextLinux_mips.cpp

+//===-- RegisterContextLinux_mips.cpp ------------------------*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===---------------------------------------------------------------------===//
+
+#if defined(__mips__)
+
+#include <vector>
+#include <stddef.h>
+
+// For GDB, GCC and DWARF Register numbers
+#include "RegisterContextLinux_mips.h"
+
+// Internal codes for all mips registers
+#include "Plugins/Process/Linux/NativeRegisterContextLinux_mips.h"
+#include "RegisterContext_mips.h"
+
+using namespace lldb_private;
+using namespace lldb;
+
+// Computes the offset of the given GPR/FPR in the user data area.
+#define GPR_OFFSET(regname) (offsetof(GPR_mips, regname))
+#define FPR_OFFSET(regname) (offsetof(FPR_mips, regname))
+
+// Note that the size and offset will be updated by platform-specific classes.
+#define DEFINE_GPR(member, reg, alt, kind1, kind2, kind3, kind4)                    \
+    { #reg, alt, sizeof(((GPR_mips*)0)->member), GPR_OFFSET(member), eEncodingUint,      \
+      eFormatHex, { kind1, kind2, kind3, kind4, lldb_private::process_linux::gp_reg_##reg##_mips }, NULL, NULL }
+
+#define DEFINE_FPR(member, reg, alt, kind1, kind2, kind3, kind4)                    \
+    { #reg, alt, sizeof(((FPR_mips*)0)->member), FPR_OFFSET(member), eEncodingIEEE754,   \
+      eFormatFloat, { kind1, kind2, kind3, kind4, lldb_private::process_linux::fp_reg_##reg##_mips }, NULL, NULL }
+
+static RegisterInfo
+g_register_infos_mips[] =
+{
+    DEFINE_GPR (gp_reg[0],  r0,   "zero",   gcc_dwarf_zero_mips,  gcc_dwarf_zero_mips,  LLDB_INVALID_REGNUM,    gdb_zero_mips),
+    DEFINE_GPR (gp_reg[1],  r1,     "at",   gcc_dwarf_r1_mips,    gcc_dwarf_r1_mips,    LLDB_INVALID_REGNUM,    gdb_r1_mips),
+    DEFINE_GPR (gp_reg[2],  r2,     NULL,   gcc_dwarf_r2_mips,    gcc_dwarf_r2_mips,    LLDB_INVALID_REGNUM,    gdb_r2_mips),
+    DEFINE_GPR (gp_reg[3],  r3,     NULL,   gcc_dwarf_r3_mips,    gcc_dwarf_r3_mips,    LLDB_INVALID_REGNUM,    gdb_r3_mips),
+    DEFINE_GPR (gp_reg[4],  r4,     NULL,   gcc_dwarf_r4_mips,    gcc_dwarf_r4_mips,    LLDB_REGNUM_GENERIC_ARG1,    gdb_r4_mips),
+    DEFINE_GPR (gp_reg[5],  r5,     NULL,   gcc_dwarf_r5_mips,    gcc_dwarf_r5_mips,    LLDB_REGNUM_GENERIC_ARG2,    gdb_r5_mips),
+    DEFINE_GPR (gp_reg[6],  r6,     NULL,   gcc_dwarf_r6_mips,    gcc_dwarf_r6_mips,    LLDB_REGNUM_GENERIC_ARG3,    gdb_r6_mips),
+    DEFINE_GPR (gp_reg[7],  r7,     NULL,   gcc_dwarf_r7_mips,    gcc_dwarf_r7_mips,    LLDB_REGNUM_GENERIC_ARG4,    gdb_r7_mips),
+    DEFINE_GPR (gp_reg[8],  r8,     NULL,   gcc_dwarf_r8_mips,    gcc_dwarf_r8_mips,    LLDB_INVALID_REGNUM,    gdb_r8_mips),
+    DEFINE_GPR (gp_reg[9],  r9,     NULL,   gcc_dwarf_r9_mips,    gcc_dwarf_r9_mips,    LLDB_INVALID_REGNUM,    gdb_r9_mips),
+    DEFINE_GPR (gp_reg[10], r10,    NULL,   gcc_dwarf_r10_mips,   gcc_dwarf_r10_mips,   LLDB_INVALID_REGNUM,    gdb_r10_mips),
+    DEFINE_GPR (gp_reg[11], r11,    NULL,   gcc_dwarf_r11_mips,   gcc_dwarf_r11_mips,   LLDB_INVALID_REGNUM,    gdb_r11_mips),
+    DEFINE_GPR (gp_reg[12], r12,    NULL,   gcc_dwarf_r12_mips,   gcc_dwarf_r12_mips,   LLDB_INVALID_REGNUM,    gdb_r12_mips),
+    DEFINE_GPR (gp_reg[13], r13,    NULL,   gcc_dwarf_r13_mips,   gcc_dwarf_r13_mips,   LLDB_INVALID_REGNUM,    gdb_r13_mips),
+    DEFINE_GPR (gp_reg[14], r14,    NULL,   gcc_dwarf_r14_mips,   gcc_dwarf_r14_mips,   LLDB_INVALID_REGNUM,    gdb_r14_mips),
+    DEFINE_GPR (gp_reg[15], r15,    NULL,   gcc_dwarf_r15_mips,   gcc_dwarf_r15_mips,   LLDB_INVALID_REGNUM,    gdb_r15_mips),
+    DEFINE_GPR (gp_reg[16], r16,    NULL,   gcc_dwarf_r16_mips,   gcc_dwarf_r16_mips,   LLDB_INVALID_REGNUM,    gdb_r16_mips),
+    DEFINE_GPR (gp_reg[17], r17,    NULL,   gcc_dwarf_r17_mips,   gcc_dwarf_r17_mips,   LLDB_INVALID_REGNUM,    gdb_r17_mips),
+    DEFINE_GPR (gp_reg[18], r18,    NULL,   gcc_dwarf_r18_mips,   gcc_dwarf_r18_mips,   LLDB_INVALID_REGNUM,    gdb_r18_mips),
+    DEFINE_GPR (gp_reg[19], r19,    NULL,   gcc_dwarf_r19_mips,   gcc_dwarf_r19_mips,   LLDB_INVALID_REGNUM,    gdb_r19_mips),
+    DEFINE_GPR (gp_reg[20], r20,    NULL,   gcc_dwarf_r20_mips,   gcc_dwarf_r20_mips,   LLDB_INVALID_REGNUM,    gdb_r20_mips),
+    DEFINE_GPR (gp_reg[21], r21,    NULL,   gcc_dwarf_r21_mips,   gcc_dwarf_r21_mips,   LLDB_INVALID_REGNUM,    gdb_r21_mips),
+    DEFINE_GPR (gp_reg[22], r22,    NULL,   gcc_dwarf_r22_mips,   gcc_dwarf_r22_mips,   LLDB_INVALID_REGNUM,    gdb_r22_mips),
+    DEFINE_GPR (gp_reg[23], r23,    NULL,   gcc_dwarf_r23_mips,   gcc_dwarf_r23_mips,   LLDB_INVALID_REGNUM,    gdb_r23_mips),
+    DEFINE_GPR (gp_reg[24], r24,    NULL,   gcc_dwarf_r24_mips,   gcc_dwarf_r24_mips,   LLDB_INVALID_REGNUM,    gdb_r24_mips),
+    DEFINE_GPR (gp_reg[25], r25,    NULL,   gcc_dwarf_r25_mips,   gcc_dwarf_r25_mips,   LLDB_INVALID_REGNUM,    gdb_r25_mips),
+    DEFINE_GPR (gp_reg[26], r26,    NULL,   gcc_dwarf_r26_mips,   gcc_dwarf_r26_mips,   LLDB_INVALID_REGNUM,    gdb_r26_mips),
+    DEFINE_GPR (gp_reg[27], r27,    NULL,   gcc_dwarf_r27_mips,   gcc_dwarf_r27_mips,   LLDB_INVALID_REGNUM,    gdb_r27_mips),
+    DEFINE_GPR (gp_reg[28], r28,    "gp",   gcc_dwarf_gp_mips,    gcc_dwarf_gp_mips,    LLDB_INVALID_REGNUM,    gdb_gp_mips),
+    DEFINE_GPR (gp_reg[29], r29,    "sp",   gcc_dwarf_sp_mips,    gcc_dwarf_sp_mips,    LLDB_REGNUM_GENERIC_SP, gdb_sp_mips),
+    DEFINE_GPR (gp_reg[30], r30,    "fp",   gcc_dwarf_r30_mips,   gcc_dwarf_r30_mips,   LLDB_REGNUM_GENERIC_FP, gdb_r30_mips),
+    DEFINE_GPR (gp_reg[31], r31,    "ra",   gcc_dwarf_ra_mips,    gcc_dwarf_ra_mips,    LLDB_REGNUM_GENERIC_RA, gdb_ra_mips),
+    DEFINE_GPR (mul_lo,     mullo,  NULL,   gcc_dwarf_lo_mips,    gcc_dwarf_lo_mips,    LLDB_INVALID_REGNUM,    LLDB_INVALID_REGNUM),
+    DEFINE_GPR (mul_hi,     mulhi,  NULL,   gcc_dwarf_hi_mips,    gcc_dwarf_hi_mips,    LLDB_INVALID_REGNUM,    LLDB_INVALID_REGNUM),
+    DEFINE_GPR (cp0_epc,    pc,     NULL,   gcc_dwarf_pc_mips,    gcc_dwarf_pc_mips,    LLDB_REGNUM_GENERIC_PC, LLDB_INVALID_REGNUM),
+    DEFINE_GPR (cp0_badvaddr, badvaddr, NULL,   gcc_dwarf_bad_mips,    gcc_dwarf_bad_mips,    LLDB_INVALID_REGNUM,    LLDB_INVALID_REGNUM),
+    DEFINE_GPR (cp0_status, sr, "status",   gcc_dwarf_sr_mips,    gcc_dwarf_sr_mips,    LLDB_REGNUM_GENERIC_FLAGS,    LLDB_INVALID_REGNUM),
+    DEFINE_GPR (cp0_cause,  cause,  NULL,   gcc_dwarf_cause_mips,    gcc_dwarf_cause_mips,    LLDB_INVALID_REGNUM,    LLDB_INVALID_REGNUM),
+    DEFINE_FPR (fp_reg[0],   f0,    NULL,   gcc_dwarf_f0_mips,   gcc_dwarf_f0_mips,   LLDB_INVALID_REGNUM,    gdb_f0_mips),
+    DEFINE_FPR (fp_reg[1],   f1,    NULL,   gcc_dwarf_f1_mips,   gcc_dwarf_f1_mips,   LLDB_INVALID_REGNUM,    gdb_f1_mips),
+    DEFINE_FPR (fp_reg[2],   f2,    NULL,   gcc_dwarf_f2_mips,   gcc_dwarf_f2_mips,   LLDB_INVALID_REGNUM,    gdb_f2_mips),
+    DEFINE_FPR (fp_reg[3],   f3,    NULL,   gcc_dwarf_f3_mips,   gcc_dwarf_f3_mips,   LLDB_INVALID_REGNUM,    gdb_f3_mips),
+    DEFINE_FPR (fp_reg[4],   f4,    NULL,   gcc_dwarf_f4_mips,   gcc_dwarf_f4_mips,   LLDB_INVALID_REGNUM,    gdb_f4_mips),
+    DEFINE_FPR (fp_reg[5],   f5,    NULL,   gcc_dwarf_f5_mips,   gcc_dwarf_f5_mips,   LLDB_INVALID_REGNUM,    gdb_f5_mips),
+    DEFINE_FPR (fp_reg[6],   f6,    NULL,   gcc_dwarf_f6_mips,   gcc_dwarf_f6_mips,   LLDB_INVALID_REGNUM,    gdb_f6_mips),
+    DEFINE_FPR (fp_reg[7],   f7,    NULL,   gcc_dwarf_f7_mips,   gcc_dwarf_f7_mips,   LLDB_INVALID_REGNUM,    gdb_f7_mips),
+    DEFINE_FPR (fp_reg[8],   f8,    NULL,   gcc_dwarf_f8_mips,   gcc_dwarf_f8_mips,   LLDB_INVALID_REGNUM,    gdb_f8_mips),
+    DEFINE_FPR (fp_reg[9],   f9,    NULL,   gcc_dwarf_f9_mips,   gcc_dwarf_f9_mips,   LLDB_INVALID_REGNUM,    gdb_f9_mips),
+    DEFINE_FPR (fp_reg[10],  f10,   NULL,   gcc_dwarf_f10_mips,  gcc_dwarf_f10_mips,  LLDB_INVALID_REGNUM,    gdb_f10_mips),
+    DEFINE_FPR (fp_reg[11],  f11,   NULL,   gcc_dwarf_f11_mips,  gcc_dwarf_f11_mips,  LLDB_INVALID_REGNUM,    gdb_f11_mips),
+    DEFINE_FPR (fp_reg[12],  f12,   NULL,   gcc_dwarf_f12_mips,  gcc_dwarf_f12_mips,  LLDB_INVALID_REGNUM,    gdb_f12_mips),
+    DEFINE_FPR (fp_reg[13],  f13,   NULL,   gcc_dwarf_f13_mips,  gcc_dwarf_f13_mips,  LLDB_INVALID_REGNUM,    gdb_f13_mips),
+    DEFINE_FPR (fp_reg[14],  f14,   NULL,   gcc_dwarf_f14_mips,  gcc_dwarf_f14_mips,  LLDB_INVALID_REGNUM,    gdb_f14_mips),
+    DEFINE_FPR (fp_reg[15],  f15,   NULL,   gcc_dwarf_f15_mips,  gcc_dwarf_f15_mips,  LLDB_INVALID_REGNUM,    gdb_f15_mips),
+    DEFINE_FPR (fp_reg[16],  f16,   NULL,   gcc_dwarf_f16_mips,  gcc_dwarf_f16_mips,  LLDB_INVALID_REGNUM,    gdb_f16_mips),
+    DEFINE_FPR (fp_reg[17],  f17,   NULL,   gcc_dwarf_f17_mips,  gcc_dwarf_f17_mips,  LLDB_INVALID_REGNUM,    gdb_f17_mips),
+    DEFINE_FPR (fp_reg[18],  f18,   NULL,   gcc_dwarf_f18_mips,  gcc_dwarf_f18_mips,  LLDB_INVALID_REGNUM,    gdb_f18_mips),
+    DEFINE_FPR (fp_reg[19],  f19,   NULL,   gcc_dwarf_f19_mips,  gcc_dwarf_f19_mips,  LLDB_INVALID_REGNUM,    gdb_f19_mips),
+    DEFINE_FPR (fp_reg[20],  f20,   NULL,   gcc_dwarf_f20_mips,  gcc_dwarf_f20_mips,  LLDB_INVALID_REGNUM,    gdb_f20_mips),
+    DEFINE_FPR (fp_reg[21],  f21,   NULL,   gcc_dwarf_f21_mips,  gcc_dwarf_f21_mips,  LLDB_INVALID_REGNUM,    gdb_f21_mips),
+    DEFINE_FPR (fp_reg[22],  f22,   NULL,   gcc_dwarf_f22_mips,  gcc_dwarf_f22_mips,  LLDB_INVALID_REGNUM,    gdb_f22_mips),
+    DEFINE_FPR (fp_reg[23],  f23,   NULL,   gcc_dwarf_f23_mips,  gcc_dwarf_f23_mips,  LLDB_INVALID_REGNUM,    gdb_f23_mips),
+    DEFINE_FPR (fp_reg[24],  f24,   NULL,   gcc_dwarf_f24_mips,  gcc_dwarf_f24_mips,  LLDB_INVALID_REGNUM,    gdb_f24_mips),
+    DEFINE_FPR (fp_reg[25],  f25,   NULL,   gcc_dwarf_f25_mips,  gcc_dwarf_f25_mips,  LLDB_INVALID_REGNUM,    gdb_f25_mips),
+    DEFINE_FPR (fp_reg[26],  f26,   NULL,   gcc_dwarf_f26_mips,  gcc_dwarf_f26_mips,  LLDB_INVALID_REGNUM,    gdb_f26_mips),
+    DEFINE_FPR (fp_reg[27],  f27,   NULL,   gcc_dwarf_f27_mips,  gcc_dwarf_f27_mips,  LLDB_INVALID_REGNUM,    gdb_f27_mips),
+    DEFINE_FPR (fp_reg[28],  f28,   NULL,   gcc_dwarf_f28_mips,  gcc_dwarf_f28_mips,  LLDB_INVALID_REGNUM,    gdb_f28_mips),
+    DEFINE_FPR (fp_reg[29],  f29,   NULL,   gcc_dwarf_f29_mips,  gcc_dwarf_f29_mips,  LLDB_INVALID_REGNUM,    gdb_f29_mips),
+    DEFINE_FPR (fp_reg[30],  f30,   NULL,   gcc_dwarf_f30_mips,  gcc_dwarf_f30_mips,  LLDB_INVALID_REGNUM,    gdb_f30_mips),
+    DEFINE_FPR (fp_reg[31],  f31,   NULL,   gcc_dwarf_f31_mips,  gcc_dwarf_f31_mips,  LLDB_INVALID_REGNUM,    gdb_f31_mips),
+    DEFINE_FPR (fcsr,        fcsr,  NULL,   gcc_dwarf_fcsr_mips, gcc_dwarf_fcsr_mips, LLDB_INVALID_REGNUM,    gdb_fcsr_mips),
+    DEFINE_FPR (fir,         fir,   NULL,   gcc_dwarf_fir_mips,  gcc_dwarf_fir_mips,  LLDB_INVALID_REGNUM,    gdb_fir_mips)
+};
+
+static const RegisterInfo *
+GetRegisterInfoPtr (const ArchSpec &target_arch)
+{
+    switch (target_arch.GetMachine())
+    {
+        case llvm::Triple::mips:
+        case llvm::Triple::mipsel:
+            return g_register_infos_mips;
+        default:
+            assert(false && "Unhandled target architecture.");
+            return nullptr;
+    }
+}
+
+static uint32_t
+GetRegisterInfoCount (const ArchSpec &target_arch)
+{
+    switch (target_arch.GetMachine())
+    {
+        case llvm::Triple::mips:
+        case llvm::Triple::mipsel:
+            return static_cast<uint32_t> (sizeof (g_register_infos_mips) / sizeof (g_register_infos_mips [0]));
+        default:
+            assert(false && "Unhandled target architecture.");
+            return 0;
+    }
+}
+
+RegisterContextLinux_mips::RegisterContextLinux_mips(const ArchSpec &target_arch) :
+    lldb_private::RegisterInfoInterface(target_arch),
+    m_register_info_p (GetRegisterInfoPtr (target_arch)),
+    m_register_info_count (GetRegisterInfoCount (target_arch))
+{
+}
+
+size_t
+RegisterContextLinux_mips::GetGPRSize() const
+{
+    return sizeof(GPR_mips);
+}
+
+const RegisterInfo *
+RegisterContextLinux_mips::GetRegisterInfo() const
+{
+    return m_register_info_p;
+}
+
+uint32_t
+RegisterContextLinux_mips::GetRegisterCount () const
+{
+    return m_register_info_count;
+}
+
+#endif

source/Plugins/Process/Utility/RegisterContextLinux_mips64.h

 //
 //===----------------------------------------------------------------------===//
 
+#if defined(__mips__)
 #ifndef liblldb_RegisterContextLinux_mips64_H_
 #define liblldb_RegisterContextLinux_mips64_H_
 
 #include "lldb/lldb-private.h"
 #include "RegisterInfoInterface.h"
 
+// GP registers
+struct GPR_mips64
+{
+    uint64_t    gp_reg[32];
+    uint64_t    mul_lo;
+    uint64_t    mul_hi;
+    uint64_t    cp0_epc;
+    uint64_t    cp0_badvaddr;
+    uint64_t    cp0_status;
+    uint64_t    cp0_cause;
+};
+
+// FP registers
+struct FPR_mips64
+{
+    uint64_t    fp_reg[32];
+    uint32_t    fcsr;        /* FPU status register */
+    uint32_t    fir;        /* FPU control register */
+};
+
 class RegisterContextLinux_mips64
     : public lldb_private::RegisterInfoInterface
 {

 };
 
 #endif
+
+#endif

source/Plugins/Process/Utility/RegisterContextLinux_mips64.cpp

 //
 //===---------------------------------------------------------------------===//
 
+#if defined(__mips__)
+
 #include <vector>
 #include <stddef.h>
 

 using namespace lldb_private;
 using namespace lldb_private::process_linux;
 
-// GP registers
-typedef struct _GPR
-{
-    uint64_t    gp_reg[32];
-    uint64_t    mul_lo;
-    uint64_t    mul_hi;
-    uint64_t    cp0_epc;
-    uint64_t    cp0_badvaddr;
-    uint64_t    cp0_status;
-    uint64_t    cp0_cause;
-} GPR;
-
-// FP registers
-typedef struct _FPR
-{
-    uint64_t    fp_reg[32];
-    uint64_t    fsr;        /* FPU status register */
-    uint64_t    fcr;        /* FPU control register */
-} FPR;
-
 // Computes the offset of the given GPR/FPR in the user data area.
-#define GPR_OFFSET(regname) (LLVM_EXTENSION offsetof(GPR, regname))
-#define FPR_OFFSET(regname) (LLVM_EXTENSION offsetof(FPR, regname))
+#define GPR_OFFSET(regname) (LLVM_EXTENSION offsetof(GPR_mips64, regname))
+#define FPR_OFFSET(regname) (LLVM_EXTENSION offsetof(FPR_mips64, regname))
 
 // Note that the size and offset will be updated by platform-specific classes.
 #define DEFINE_GPR(member, reg, alt, kind1, kind2, kind3, kind4)                    \
-    { #reg, alt, sizeof(((GPR*)0)->member), GPR_OFFSET(member), eEncodingUint,      \
+    { #reg, alt, sizeof(((GPR_mips64*)0)->member), GPR_OFFSET(member), eEncodingUint,      \
       eFormatHex, { kind1, kind2, kind3, kind4, gp_reg_##reg##_mips64 }, NULL, NULL }
 
 #define DEFINE_FPR(member, reg, alt, kind1, kind2, kind3, kind4)                    \
-    { #reg, alt, sizeof(((FPR*)0)->member), FPR_OFFSET(member), eEncodingIEEE754,   \
+    { #reg, alt, sizeof(((FPR_mips64*)0)->member), FPR_OFFSET(member), eEncodingIEEE754,   \
       eFormatFloat, { kind1, kind2, kind3, kind4, fp_reg_##reg##_mips64 }, NULL, NULL }
 
 static RegisterInfo

     DEFINE_GPR (cp0_badvaddr, badvaddr, NULL,   gcc_dwarf_bad_mips64,    gcc_dwarf_bad_mips64,    LLDB_INVALID_REGNUM,    LLDB_INVALID_REGNUM),
     DEFINE_GPR (cp0_status, sr, "status",   gcc_dwarf_sr_mips64,    gcc_dwarf_sr_mips64,    LLDB_REGNUM_GENERIC_FLAGS,    LLDB_INVALID_REGNUM),
     DEFINE_GPR (cp0_cause,  cause,  NULL,   gcc_dwarf_cause_mips64,    gcc_dwarf_cause_mips64,    LLDB_INVALID_REGNUM,    LLDB_INVALID_REGNUM),
+    DEFINE_FPR (fp_reg[0],   f0,    NULL,   gcc_dwarf_f0_mips64,   gcc_dwarf_f0_mips64,   LLDB_INVALID_REGNUM,    gdb_f0_mips64),
+    DEFINE_FPR (fp_reg[1],   f1,    NULL,   gcc_dwarf_f1_mips64,   gcc_dwarf_f1_mips64,   LLDB_INVALID_REGNUM,    gdb_f1_mips64),
+    DEFINE_FPR (fp_reg[2],   f2,    NULL,   gcc_dwarf_f2_mips64,   gcc_dwarf_f2_mips64,   LLDB_INVALID_REGNUM,    gdb_f2_mips64),
+    DEFINE_FPR (fp_reg[3],   f3,    NULL,   gcc_dwarf_f3_mips64,   gcc_dwarf_f3_mips64,   LLDB_INVALID_REGNUM,    gdb_f3_mips64),
+    DEFINE_FPR (fp_reg[4],   f4,    NULL,   gcc_dwarf_f4_mips64,   gcc_dwarf_f4_mips64,   LLDB_INVALID_REGNUM,    gdb_f4_mips64),
+    DEFINE_FPR (fp_reg[5],   f5,    NULL,   gcc_dwarf_f5_mips64,   gcc_dwarf_f5_mips64,   LLDB_INVALID_REGNUM,    gdb_f5_mips64),
+    DEFINE_FPR (fp_reg[6],   f6,    NULL,   gcc_dwarf_f6_mips64,   gcc_dwarf_f6_mips64,   LLDB_INVALID_REGNUM,    gdb_f6_mips64),
+    DEFINE_FPR (fp_reg[7],   f7,    NULL,   gcc_dwarf_f7_mips64,   gcc_dwarf_f7_mips64,   LLDB_INVALID_REGNUM,    gdb_f7_mips64),
+    DEFINE_FPR (fp_reg[8],   f8,    NULL,   gcc_dwarf_f8_mips64,   gcc_dwarf_f8_mips64,   LLDB_INVALID_REGNUM,    gdb_f8_mips64),
+    DEFINE_FPR (fp_reg[9],   f9,    NULL,   gcc_dwarf_f9_mips64,   gcc_dwarf_f9_mips64,   LLDB_INVALID_REGNUM,    gdb_f9_mips64),
+    DEFINE_FPR (fp_reg[10],  f10,   NULL,   gcc_dwarf_f10_mips64,  gcc_dwarf_f10_mips64,  LLDB_INVALID_REGNUM,    gdb_f10_mips64),
+    DEFINE_FPR (fp_reg[11],  f11,   NULL,   gcc_dwarf_f11_mips64,  gcc_dwarf_f11_mips64,  LLDB_INVALID_REGNUM,    gdb_f11_mips64),
+    DEFINE_FPR (fp_reg[12],  f12,   NULL,   gcc_dwarf_f12_mips64,  gcc_dwarf_f12_mips64,  LLDB_INVALID_REGNUM,    gdb_f12_mips64),
+    DEFINE_FPR (fp_reg[13],  f13,   NULL,   gcc_dwarf_f13_mips64,  gcc_dwarf_f13_mips64,  LLDB_INVALID_REGNUM,    gdb_f13_mips64),
+    DEFINE_FPR (fp_reg[14],  f14,   NULL,   gcc_dwarf_f14_mips64,  gcc_dwarf_f14_mips64,  LLDB_INVALID_REGNUM,    gdb_f14_mips64),
+    DEFINE_FPR (fp_reg[15],  f15,   NULL,   gcc_dwarf_f15_mips64,  gcc_dwarf_f15_mips64,  LLDB_INVALID_REGNUM,    gdb_f15_mips64),
+    DEFINE_FPR (fp_reg[16],  f16,   NULL,   gcc_dwarf_f16_mips64,  gcc_dwarf_f16_mips64,  LLDB_INVALID_REGNUM,    gdb_f16_mips64),
+    DEFINE_FPR (fp_reg[17],  f17,   NULL,   gcc_dwarf_f17_mips64,  gcc_dwarf_f17_mips64,  LLDB_INVALID_REGNUM,    gdb_f17_mips64),
+    DEFINE_FPR (fp_reg[18],  f18,   NULL,   gcc_dwarf_f18_mips64,  gcc_dwarf_f18_mips64,  LLDB_INVALID_REGNUM,    gdb_f18_mips64),
+    DEFINE_FPR (fp_reg[19],  f19,   NULL,   gcc_dwarf_f19_mips64,  gcc_dwarf_f19_mips64,  LLDB_INVALID_REGNUM,    gdb_f19_mips64),
+    DEFINE_FPR (fp_reg[20],  f20,   NULL,   gcc_dwarf_f20_mips64,  gcc_dwarf_f20_mips64,  LLDB_INVALID_REGNUM,    gdb_f20_mips64),
+    DEFINE_FPR (fp_reg[21],  f21,   NULL,   gcc_dwarf_f21_mips64,  gcc_dwarf_f21_mips64,  LLDB_INVALID_REGNUM,    gdb_f21_mips64),
+    DEFINE_FPR (fp_reg[22],  f22,   NULL,   gcc_dwarf_f22_mips64,  gcc_dwarf_f22_mips64,  LLDB_INVALID_REGNUM,    gdb_f22_mips64),
+    DEFINE_FPR (fp_reg[23],  f23,   NULL,   gcc_dwarf_f23_mips64,  gcc_dwarf_f23_mips64,  LLDB_INVALID_REGNUM,    gdb_f23_mips64),
+    DEFINE_FPR (fp_reg[24],  f24,   NULL,   gcc_dwarf_f24_mips64,  gcc_dwarf_f24_mips64,  LLDB_INVALID_REGNUM,    gdb_f24_mips64),
+    DEFINE_FPR (fp_reg[25],  f25,   NULL,   gcc_dwarf_f25_mips64,  gcc_dwarf_f25_mips64,  LLDB_INVALID_REGNUM,    gdb_f25_mips64),
+    DEFINE_FPR (fp_reg[26],  f26,   NULL,   gcc_dwarf_f26_mips64,  gcc_dwarf_f26_mips64,  LLDB_INVALID_REGNUM,    gdb_f26_mips64),
+    DEFINE_FPR (fp_reg[27],  f27,   NULL,   gcc_dwarf_f27_mips64,  gcc_dwarf_f27_mips64,  LLDB_INVALID_REGNUM,    gdb_f27_mips64),
+    DEFINE_FPR (fp_reg[28],  f28,   NULL,   gcc_dwarf_f28_mips64,  gcc_dwarf_f28_mips64,  LLDB_INVALID_REGNUM,    gdb_f28_mips64),
+    DEFINE_FPR (fp_reg[29],  f29,   NULL,   gcc_dwarf_f29_mips64,  gcc_dwarf_f29_mips64,  LLDB_INVALID_REGNUM,    gdb_f29_mips64),
+    DEFINE_FPR (fp_reg[30],  f30,   NULL,   gcc_dwarf_f30_mips64,  gcc_dwarf_f30_mips64,  LLDB_INVALID_REGNUM,    gdb_f30_mips64),
+    DEFINE_FPR (fp_reg[31],  f31,   NULL,   gcc_dwarf_f31_mips64,  gcc_dwarf_f31_mips64,  LLDB_INVALID_REGNUM,    gdb_f31_mips64),
+    DEFINE_FPR (fcsr,        fcsr,  NULL,   gcc_dwarf_fcsr_mips64, gcc_dwarf_fcsr_mips64, LLDB_INVALID_REGNUM,    gdb_fcsr_mips64),
+    DEFINE_FPR (fir,         fir,   NULL,   gcc_dwarf_fir_mips64,  gcc_dwarf_fir_mips64,  LLDB_INVALID_REGNUM,    gdb_fir_mips64)
 };
 
 static const RegisterInfo *

     {
         case llvm::Triple::mips64:
         case llvm::Triple::mips64el:
+        case llvm::Triple::mips:
+        case llvm::Triple::mipsel:
             return g_register_infos_mips64;
         default:
             assert(false && "Unhandled target architecture.");

     {
         case llvm::Triple::mips64:
         case llvm::Triple::mips64el:
+        case llvm::Triple::mips:
+        case llvm::Triple::mipsel:
             return static_cast<uint32_t> (sizeof (g_register_infos_mips64) / sizeof (g_register_infos_mips64 [0]));
         default:
             assert(false && "Unhandled target architecture.");

 size_t
 RegisterContextLinux_mips64::GetGPRSize() const
 {
-    return sizeof(GPR);
+    return sizeof(GPR_mips64);
 }
 
 const RegisterInfo *

     return m_register_info_count;
 }
 
+#endif

source/Plugins/Process/Utility/RegisterContext_mips.h

+//===-- RegisterContext_mips.h --------------------------------*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef liblldb_RegisterContext_mips_H_
+#define liblldb_RegisterContext_mips_H_
+
+// GCC and DWARF Register numbers (eRegisterKindGCC & eRegisterKindDWARF)
+enum
+{
+    // GP Registers
+    gcc_dwarf_zero_mips = 0,
+    gcc_dwarf_r1_mips,
+    gcc_dwarf_r2_mips,
+    gcc_dwarf_r3_mips,
+    gcc_dwarf_r4_mips,
+    gcc_dwarf_r5_mips,
+    gcc_dwarf_r6_mips,
+    gcc_dwarf_r7_mips,
+    gcc_dwarf_r8_mips,
+    gcc_dwarf_r9_mips,
+    gcc_dwarf_r10_mips,
+    gcc_dwarf_r11_mips,
+    gcc_dwarf_r12_mips,
+    gcc_dwarf_r13_mips,
+    gcc_dwarf_r14_mips,
+    gcc_dwarf_r15_mips,
+    gcc_dwarf_r16_mips,
+    gcc_dwarf_r17_mips,
+    gcc_dwarf_r18_mips,
+    gcc_dwarf_r19_mips,
+    gcc_dwarf_r20_mips,
+    gcc_dwarf_r21_mips,
+    gcc_dwarf_r22_mips,
+    gcc_dwarf_r23_mips,
+    gcc_dwarf_r24_mips,
+    gcc_dwarf_r25_mips,
+    gcc_dwarf_r26_mips,
+    gcc_dwarf_r27_mips,
+    gcc_dwarf_gp_mips,
+    gcc_dwarf_sp_mips,
+    gcc_dwarf_r30_mips,
+    gcc_dwarf_ra_mips,
+    gcc_dwarf_sr_mips,
+    gcc_dwarf_lo_mips,
+    gcc_dwarf_hi_mips,
+    gcc_dwarf_bad_mips,
+    gcc_dwarf_cause_mips,
+    gcc_dwarf_pc_mips,
+    gcc_dwarf_f0_mips,  
+    gcc_dwarf_f1_mips,
+    gcc_dwarf_f2_mips,
+    gcc_dwarf_f3_mips,
+    gcc_dwarf_f4_mips,
+    gcc_dwarf_f5_mips,
+    gcc_dwarf_f6_mips,
+    gcc_dwarf_f7_mips,
+    gcc_dwarf_f8_mips,
+    gcc_dwarf_f9_mips,
+    gcc_dwarf_f10_mips,
+    gcc_dwarf_f11_mips,
+    gcc_dwarf_f12_mips,
+    gcc_dwarf_f13_mips,
+    gcc_dwarf_f14_mips,
+    gcc_dwarf_f15_mips,
+    gcc_dwarf_f16_mips,
+    gcc_dwarf_f17_mips,
+    gcc_dwarf_f18_mips,
+    gcc_dwarf_f19_mips,
+    gcc_dwarf_f20_mips,
+    gcc_dwarf_f21_mips,
+    gcc_dwarf_f22_mips,
+    gcc_dwarf_f23_mips,
+    gcc_dwarf_f24_mips,
+    gcc_dwarf_f25_mips,
+    gcc_dwarf_f26_mips,
+    gcc_dwarf_f27_mips,
+    gcc_dwarf_f28_mips,
+    gcc_dwarf_f29_mips,
+    gcc_dwarf_f30_mips,
+    gcc_dwarf_f31_mips,
+    gcc_dwarf_fcsr_mips,
+    gcc_dwarf_fir_mips,
+    gcc_dwarf_ic_mips,
+    gcc_dwarf_dummy_mips
+};
+
+// GDB Register numbers (eRegisterKindGDB)
+enum
+{
+    gdb_zero_mips = 0,
+    gdb_r1_mips,
+    gdb_r2_mips,
+    gdb_r3_mips,
+    gdb_r4_mips,
+    gdb_r5_mips,
+    gdb_r6_mips,
+    gdb_r7_mips,
+    gdb_r8_mips,
+    gdb_r9_mips,
+    gdb_r10_mips,
+    gdb_r11_mips,
+    gdb_r12_mips,
+    gdb_r13_mips,
+    gdb_r14_mips,
+    gdb_r15_mips,
+    gdb_r16_mips,
+    gdb_r17_mips,
+    gdb_r18_mips,
+    gdb_r19_mips,
+    gdb_r20_mips,
+    gdb_r21_mips,
+    gdb_r22_mips,
+    gdb_r23_mips,
+    gdb_r24_mips,
+    gdb_r25_mips,
+    gdb_r26_mips,
+    gdb_r27_mips,
+    gdb_gp_mips,
+    gdb_sp_mips,
+    gdb_r30_mips,
+    gdb_ra_mips,
+    gdb_sr_mips,
+    gdb_lo_mips,
+    gdb_hi_mips,
+    gdb_bad_mips,
+    gdb_cause_mips,
+    gdb_pc_mips,
+    gdb_f0_mips,
+    gdb_f1_mips,
+    gdb_f2_mips,
+    gdb_f3_mips,
+    gdb_f4_mips,
+    gdb_f5_mips,
+    gdb_f6_mips,
+    gdb_f7_mips,
+    gdb_f8_mips,
+    gdb_f9_mips,
+    gdb_f10_mips,
+    gdb_f11_mips,
+    gdb_f12_mips,
+    gdb_f13_mips,
+    gdb_f14_mips,
+    gdb_f15_mips,
+    gdb_f16_mips,
+    gdb_f17_mips,
+    gdb_f18_mips,
+    gdb_f19_mips,
+    gdb_f20_mips,
+    gdb_f21_mips,
+    gdb_f22_mips,
+    gdb_f23_mips,
+    gdb_f24_mips,
+    gdb_f25_mips,
+    gdb_f26_mips,
+    gdb_f27_mips,
+    gdb_f28_mips,
+    gdb_f29_mips,
+    gdb_f30_mips,
+    gdb_f31_mips,
+    gdb_fcsr_mips,
+    gdb_fir_mips,
+    gdb_ic_mips,
+    gdb_dummy_mips
+};
+
+#endif // liblldb_RegisterContext_mips_H_

source/Plugins/Process/Utility/RegisterContext_mips64.h

 //
 //===----------------------------------------------------------------------===//
 
+#if defined(__mips__)
+
 #ifndef liblldb_RegisterContext_mips64_H_
 #define liblldb_RegisterContext_mips64_H_
 

     gcc_dwarf_bad_mips64,
     gcc_dwarf_cause_mips64,
     gcc_dwarf_pc_mips64,
+    gcc_dwarf_f0_mips64,  
+    gcc_dwarf_f1_mips64,
+    gcc_dwarf_f2_mips64,
+    gcc_dwarf_f3_mips64,
+    gcc_dwarf_f4_mips64,
+    gcc_dwarf_f5_mips64,
+    gcc_dwarf_f6_mips64,
+    gcc_dwarf_f7_mips64,
+    gcc_dwarf_f8_mips64,
+    gcc_dwarf_f9_mips64,
+    gcc_dwarf_f10_mips64,
+    gcc_dwarf_f11_mips64,
+    gcc_dwarf_f12_mips64,
+    gcc_dwarf_f13_mips64,
+    gcc_dwarf_f14_mips64,
+    gcc_dwarf_f15_mips64,
+    gcc_dwarf_f16_mips64,
+    gcc_dwarf_f17_mips64,
+    gcc_dwarf_f18_mips64,
+    gcc_dwarf_f19_mips64,
+    gcc_dwarf_f20_mips64,
+    gcc_dwarf_f21_mips64,
+    gcc_dwarf_f22_mips64,
+    gcc_dwarf_f23_mips64,
+    gcc_dwarf_f24_mips64,
+    gcc_dwarf_f25_mips64,
+    gcc_dwarf_f26_mips64,
+    gcc_dwarf_f27_mips64,
+    gcc_dwarf_f28_mips64,
+    gcc_dwarf_f29_mips64,
+    gcc_dwarf_f30_mips64,
+    gcc_dwarf_f31_mips64,
+    gcc_dwarf_fcsr_mips64,
+    gcc_dwarf_fir_mips64,
     gcc_dwarf_ic_mips64,
     gcc_dwarf_dummy_mips64
 };

     gdb_bad_mips64,
     gdb_cause_mips64,
     gdb_pc_mips64,
+    gdb_f0_mips64,
+    gdb_f1_mips64,
+    gdb_f2_mips64,
+    gdb_f3_mips64,
+    gdb_f4_mips64,
+    gdb_f5_mips64,
+    gdb_f6_mips64,
+    gdb_f7_mips64,
+    gdb_f8_mips64,
+    gdb_f9_mips64,
+    gdb_f10_mips64,
+    gdb_f11_mips64,
+    gdb_f12_mips64,
+    gdb_f13_mips64,
+    gdb_f14_mips64,
+    gdb_f15_mips64,
+    gdb_f16_mips64,
+    gdb_f17_mips64,
+    gdb_f18_mips64,
+    gdb_f19_mips64,
+    gdb_f20_mips64,
+    gdb_f21_mips64,
+    gdb_f22_mips64,
+    gdb_f23_mips64,
+    gdb_f24_mips64,
+    gdb_f25_mips64,
+    gdb_f26_mips64,
+    gdb_f27_mips64,
+    gdb_f28_mips64,
+    gdb_f29_mips64,
+    gdb_f30_mips64,
+    gdb_f31_mips64,
+    gdb_fcsr_mips64,
+    gdb_fir_mips64,
     gdb_ic_mips64,
     gdb_dummy_mips64
 };
 
 #endif // liblldb_RegisterContext_mips64_H_
+
+#endif