[WebAssembly] Update v128.any_true

[tlively]

Summary

In the final SIMD spec, there is only a single v128.any_true instruction, rather
than one for each lane interpretation because the semantics do not depend on the
lane interpretation.

[aheejin]

Not related to this CL, but why isn't all_true also a single instruction? Does that depend on the lane size?

[tlively]

all_true returns true if all lanes are non-zero, not just if all lanes are -1. So if there are just a few bits set throughout the vector, whether all lanes are non-zero might depend on the lane interpretation.

llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td

 
 multiclass SIMDUnaryInt<SDPatternOperator node, string name, bits<32> baseInst> {
   defm "" : SIMDUnary<I8x16, node, name, baseInst>;
   defm "" : SIMDUnary<I16x8, node, name, !add(baseInst, 32)>;
   defm "" : SIMDUnary<I32x4, node, name, !add(baseInst, 64)>;
   defm "" : SIMDUnary<I64x2, node, name, !add(baseInst, 96)>;
 }
 
-multiclass SIMDReduceVec<Vec vec, SDPatternOperator op, string name, bits<32> simdop> {
-  defm _#vec : SIMD_I<(outs I32:$dst), (ins V128:$vec), (outs), (ins),
-                      [(set I32:$dst, (i32 (op (vec.vt V128:$vec))))],
-                      vec.prefix#"."#name#"\t$dst, $vec", vec.prefix#"."#name,
-                      simdop>;
-}
-
-multiclass SIMDReduce<SDPatternOperator op, string name, bits<32> baseInst> {
-  defm "" : SIMDReduceVec<I8x16, op, name, baseInst>;
-  defm "" : SIMDReduceVec<I16x8, op, name, !add(baseInst, 32)>;
-  defm "" : SIMDReduceVec<I32x4, op, name, !add(baseInst, 64)>;
-  defm "" : SIMDReduceVec<I64x2, op, name, !add(baseInst, 96)>;
-}
-
 // Integer vector negation
 def ivneg : PatFrag<(ops node:$in), (sub immAllZerosV, $in)>;
 
 // Integer absolute value: abs
 defm ABS : SIMDUnaryInt<abs, "abs", 96>;
 
 // Integer negation: neg
 defm NEG : SIMDUnaryInt<ivneg, "neg", 97>;
 
+// Population count: popcnt
+defm POPCNT : SIMDUnary<I8x16, int_wasm_popcnt, "popcnt", 0x62>;
+
 // Any lane true: any_true
-defm ANYTRUE : SIMDReduce<int_wasm_anytrue, "any_true", 98>;
+defm ANYTRUE : SIMD_I<(outs I32:$dst), (ins V128:$vec), (outs), (ins), [],
+                      "v128.any_true\t$dst, $vec", "v128.any_true", 0x53>;
+
+foreach vec = IntVecs in
+def : Pat<(int_wasm_anytrue (vec.vt V128:$vec)), (ANYTRUE V128:$vec)>;
 
 // All lanes true: all_true
-defm ALLTRUE : SIMDReduce<int_wasm_alltrue, "all_true", 99>;
+multiclass SIMDAllTrue<Vec vec, bits<32> simdop> {
+  defm ALLTRUE_#vec : SIMD_I<(outs I32:$dst), (ins V128:$vec), (outs), (ins),
+                             [(set I32:$dst,
+                               (i32 (int_wasm_alltrue (vec.vt V128:$vec))))],
+                             vec.prefix#".all_true\t$dst, $vec",
+                             vec.prefix#".all_true", simdop>;
+}
 
-// Population count: popcnt
-defm POPCNT : SIMDUnary<I8x16, int_wasm_popcnt, "popcnt", 0x62>;
+defm "" : SIMDAllTrue<I8x16, 0x63>;
+defm "" : SIMDAllTrue<I16x8, 0x83>;
+defm "" : SIMDAllTrue<I32x4, 0xa3>;
+defm "" : SIMDAllTrue<I64x2, 0xc3>;
 
 // Reductions already return 0 or 1, so and 1, setne 0, and seteq 1
 // can be folded out
 foreach reduction =
-  [["int_wasm_anytrue", "ANYTRUE"], ["int_wasm_alltrue", "ALLTRUE"]] in
-foreach vec = IntVecs in {
+  [["int_wasm_anytrue", "ANYTRUE", "I8x16"],
+   ["int_wasm_anytrue", "ANYTRUE", "I16x8"],
+   ["int_wasm_anytrue", "ANYTRUE", "I32x4"],
+   ["int_wasm_anytrue", "ANYTRUE", "I64x2"],
+   ["int_wasm_alltrue", "ALLTRUE_I8x16", "I8x16"],
+   ["int_wasm_alltrue", "ALLTRUE_I16x8", "I16x8"],
+   ["int_wasm_alltrue", "ALLTRUE_I32x4", "I32x4"],
+   ["int_wasm_alltrue", "ALLTRUE_I64x2", "I64x2"]] in {
 defvar intrinsic = !cast<Intrinsic>(reduction[0]);
-defvar inst = !cast<NI>(reduction[1]#"_"#vec);
+defvar inst = !cast<NI>(reduction[1]);
+defvar vec = !cast<Vec>(reduction[2]);
 def : Pat<(i32 (and (i32 (intrinsic (vec.vt V128:$x))), (i32 1))), (inst $x)>;
 def : Pat<(i32 (setne (i32 (intrinsic (vec.vt V128:$x))), (i32 0))), (inst $x)>;
 def : Pat<(i32 (seteq (i32 (intrinsic (vec.vt V128:$x))), (i32 1))), (inst $x)>;
 }
 
 multiclass SIMDBitmask<Vec vec, bits<32> simdop> {
   defm _#vec : SIMD_I<(outs I32:$dst), (ins V128:$vec), (outs), (ins),
                       [(set I32:$dst,

llvm/test/CodeGen/WebAssembly/simd-intrinsics.ll

 declare <16 x i8> @llvm.wasm.popcnt(<16 x i8>)
 define <16 x i8> @popcnt_v16i8(<16 x i8> %x) {
  %a = call <16 x i8> @llvm.wasm.popcnt(<16 x i8> %x)
  ret <16 x i8> %a
 }
 
 ; CHECK-LABEL: any_v16i8:
 ; CHECK-NEXT: .functype any_v16i8 (v128) -> (i32){{$}}
-; CHECK-NEXT: i8x16.any_true $push[[R:[0-9]+]]=, $0{{$}}
+; CHECK-NEXT: v128.any_true $push[[R:[0-9]+]]=, $0{{$}}
 ; CHECK-NEXT: return $pop[[R]]{{$}}
 declare i32 @llvm.wasm.anytrue.v16i8(<16 x i8>)
 define i32 @any_v16i8(<16 x i8> %x) {
   %a = call i32 @llvm.wasm.anytrue.v16i8(<16 x i8> %x)
   ret i32 %a
 }
 
 ; CHECK-LABEL: all_v16i8:

 declare <8 x i16> @llvm.wasm.extadd.pairwise.unsigned.v8i16(<16 x i8>)
 define <8 x i16> @extadd_pairwise_u_v8i16(<16 x i8> %x) {
   %a = call <8 x i16> @llvm.wasm.extadd.pairwise.unsigned.v8i16(<16 x i8> %x)
   ret <8 x i16> %a
 }
 
 ; CHECK-LABEL: any_v8i16:
 ; CHECK-NEXT: .functype any_v8i16 (v128) -> (i32){{$}}
-; CHECK-NEXT: i16x8.any_true $push[[R:[0-9]+]]=, $0{{$}}
+; CHECK-NEXT: v128.any_true $push[[R:[0-9]+]]=, $0{{$}}
 ; CHECK-NEXT: return $pop[[R]]{{$}}
 declare i32 @llvm.wasm.anytrue.v8i16(<8 x i16>)
 define i32 @any_v8i16(<8 x i16> %x) {
   %a = call i32 @llvm.wasm.anytrue.v8i16(<8 x i16> %x)
   ret i32 %a
 }
 
 ; CHECK-LABEL: all_v8i16:

 define <4 x i32> @extadd_pairwise_u_v4i32(<8 x i16> %x) {
   %a = call <4 x i32> @llvm.wasm.extadd.pairwise.unsigned.v4i32(<8 x i16> %x)
   ret <4 x i32> %a
 }
 
 
 ; CHECK-LABEL: any_v4i32:
 ; CHECK-NEXT: .functype any_v4i32 (v128) -> (i32){{$}}
-; CHECK-NEXT: i32x4.any_true $push[[R:[0-9]+]]=, $0{{$}}
+; CHECK-NEXT: v128.any_true $push[[R:[0-9]+]]=, $0{{$}}
 ; CHECK-NEXT: return $pop[[R]]{{$}}
 declare i32 @llvm.wasm.anytrue.v4i32(<4 x i32>)
 define i32 @any_v4i32(<4 x i32> %x) {
   %a = call i32 @llvm.wasm.anytrue.v4i32(<4 x i32> %x)
   ret i32 %a
 }
 
 ; CHECK-LABEL: all_v4i32:
define <2 x i64> @extmul_high_u_v2i64(<4 x i32> %x, <4 x i32> %y) {
   %a = call <2 x i64> @llvm.wasm.extmul.high.unsigned.v2i64(
     <4 x i32> %x, <4 x i32> %y
   )
   ret <2 x i64> %a
 }
 
 ; CHECK-LABEL: any_v2i64:
 ; CHECK-NEXT: .functype any_v2i64 (v128) -> (i32){{$}}
-; CHECK-NEXT: i64x2.any_true $push[[R:[0-9]+]]=, $0{{$}}
+; CHECK-NEXT: v128.any_true $push[[R:[0-9]+]]=, $0{{$}}
 ; CHECK-NEXT: return $pop[[R]]{{$}}
 declare i32 @llvm.wasm.anytrue.v2i64(<2 x i64>)
 define i32 @any_v2i64(<2 x i64> %x) {
   %a = call i32 @llvm.wasm.anytrue.v2i64(<2 x i64> %x)
   ret i32 %a
 }
 
 ; CHECK-LABEL: all_v2i64:

llvm/test/CodeGen/WebAssembly/simd-reductions.ll

 ; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+simd128 | FileCheck %s
 
 ; Tests that redundant masking and conversions are folded out
 ; following SIMD reduction instructions.
 
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
 ; ==============================================================================
 ; 16 x i8
 ; ==============================================================================
 declare i32 @llvm.wasm.anytrue.v16i8(<16 x i8>)
 declare i32 @llvm.wasm.alltrue.v16i8(<16 x i8>)
 
 ; CHECK-LABEL: any_v16i8_trunc:
 ; CHECK-NEXT: .functype any_v16i8_trunc (v128) -> (i32){{$}}
-; CHECK-NEXT: i8x16.any_true $push[[R:[0-9]+]]=, $0{{$}}
+; CHECK-NEXT: v128.any_true $push[[R:[0-9]+]]=, $0{{$}}
 ; CHECK-NEXT: return $pop[[R]]{{$}}
 define i32 @any_v16i8_trunc(<16 x i8> %x) {
   %a = call i32 @llvm.wasm.anytrue.v16i8(<16 x i8> %x)
   %b = trunc i32 %a to i1
   %c = zext i1 %b to i32
   ret i32 %c
 }
 
 ; CHECK-LABEL: any_v16i8_ne:
 ; CHECK-NEXT: .functype any_v16i8_ne (v128) -> (i32){{$}}
-; CHECK-NEXT: i8x16.any_true $push[[R:[0-9]+]]=, $0{{$}}
+; CHECK-NEXT: v128.any_true $push[[R:[0-9]+]]=, $0{{$}}
 ; CHECK-NEXT: return $pop[[R]]{{$}}
 define i32 @any_v16i8_ne(<16 x i8> %x) {
   %a = call i32 @llvm.wasm.anytrue.v16i8(<16 x i8> %x)
   %b = icmp ne i32 %a, 0
   %c = zext i1 %b to i32
   ret i32 %c
 }
 
 ; CHECK-LABEL: any_v16i8_eq:
 ; CHECK-NEXT: .functype any_v16i8_eq (v128) -> (i32){{$}}
-; CHECK-NEXT: i8x16.any_true $push[[R:[0-9]+]]=, $0{{$}}
+; CHECK-NEXT: v128.any_true $push[[R:[0-9]+]]=, $0{{$}}
 ; CHECK-NEXT: return $pop[[R]]{{$}}
 define i32 @any_v16i8_eq(<16 x i8> %x) {
   %a = call i32 @llvm.wasm.anytrue.v16i8(<16 x i8> %x)
   %b = icmp eq i32 %a, 1
   %c = zext i1 %b to i32
   ret i32 %c
 }
 

 ; ==============================================================================
 ; 8 x i16
 ; ==============================================================================
 declare i32 @llvm.wasm.anytrue.v8i16(<8 x i16>)
 declare i32 @llvm.wasm.alltrue.v8i16(<8 x i16>)
 
 ; CHECK-LABEL: any_v8i16_trunc:
 ; CHECK-NEXT: .functype any_v8i16_trunc (v128) -> (i32){{$}}
-; CHECK-NEXT: i16x8.any_true $push[[R:[0-9]+]]=, $0{{$}}
+; CHECK-NEXT: v128.any_true $push[[R:[0-9]+]]=, $0{{$}}
 ; CHECK-NEXT: return $pop[[R]]{{$}}
 define i32 @any_v8i16_trunc(<8 x i16> %x) {
   %a = call i32 @llvm.wasm.anytrue.v8i16(<8 x i16> %x)
   %b = trunc i32 %a to i1
   %c = zext i1 %b to i32
   ret i32 %c
 }
 
 ; CHECK-LABEL: any_v8i16_ne:
 ; CHECK-NEXT: .functype any_v8i16_ne (v128) -> (i32){{$}}
-; CHECK-NEXT: i16x8.any_true $push[[R:[0-9]+]]=, $0{{$}}
+; CHECK-NEXT: v128.any_true $push[[R:[0-9]+]]=, $0{{$}}
 ; CHECK-NEXT: return $pop[[R]]{{$}}
 define i32 @any_v8i16_ne(<8 x i16> %x) {
   %a = call i32 @llvm.wasm.anytrue.v8i16(<8 x i16> %x)
   %b = icmp ne i32 %a, 0
   %c = zext i1 %b to i32
   ret i32 %c
 }
 
 ; CHECK-LABEL: any_v8i16_eq:
 ; CHECK-NEXT: .functype any_v8i16_eq (v128) -> (i32){{$}}
-; CHECK-NEXT: i16x8.any_true $push[[R:[0-9]+]]=, $0{{$}}
+; CHECK-NEXT: v128.any_true $push[[R:[0-9]+]]=, $0{{$}}
 ; CHECK-NEXT: return $pop[[R]]{{$}}
 define i32 @any_v8i16_eq(<8 x i16> %x) {
   %a = call i32 @llvm.wasm.anytrue.v8i16(<8 x i16> %x)
   %b = icmp eq i32 %a, 1
   %c = zext i1 %b to i32
   ret i32 %c
 }
 

 ; ==============================================================================
 ; 4 x i32
 ; ==============================================================================
 declare i32 @llvm.wasm.anytrue.v4i32(<4 x i32>)
 declare i32 @llvm.wasm.alltrue.v4i32(<4 x i32>)
 
 ; CHECK-LABEL: any_v4i32_trunc:
 ; CHECK-NEXT: .functype any_v4i32_trunc (v128) -> (i32){{$}}
-; CHECK-NEXT: i32x4.any_true $push[[R:[0-9]+]]=, $0{{$}}
+; CHECK-NEXT: v128.any_true $push[[R:[0-9]+]]=, $0{{$}}
 ; CHECK-NEXT: return $pop[[R]]{{$}}
 define i32 @any_v4i32_trunc(<4 x i32> %x) {
   %a = call i32 @llvm.wasm.anytrue.v4i32(<4 x i32> %x)
   %b = trunc i32 %a to i1
   %c = zext i1 %b to i32
   ret i32 %c
 }
 
 ; CHECK-LABEL: any_v4i32_ne:
 ; CHECK-NEXT: .functype any_v4i32_ne (v128) -> (i32){{$}}
-; CHECK-NEXT: i32x4.any_true $push[[R:[0-9]+]]=, $0{{$}}
+; CHECK-NEXT: v128.any_true $push[[R:[0-9]+]]=, $0{{$}}
 ; CHECK-NEXT: return $pop[[R]]{{$}}
 define i32 @any_v4i32_ne(<4 x i32> %x) {
   %a = call i32 @llvm.wasm.anytrue.v4i32(<4 x i32> %x)
   %b = icmp ne i32 %a, 0
   %c = zext i1 %b to i32
   ret i32 %c
 }
 
 ; CHECK-LABEL: any_v4i32_eq:
 ; CHECK-NEXT: .functype any_v4i32_eq (v128) -> (i32){{$}}
-; CHECK-NEXT: i32x4.any_true $push[[R:[0-9]+]]=, $0{{$}}
+; CHECK-NEXT: v128.any_true $push[[R:[0-9]+]]=, $0{{$}}
 ; CHECK-NEXT: return $pop[[R]]{{$}}
 define i32 @any_v4i32_eq(<4 x i32> %x) {
   %a = call i32 @llvm.wasm.anytrue.v4i32(<4 x i32> %x)
   %b = icmp eq i32 %a, 1
   %c = zext i1 %b to i32
   ret i32 %c
 }
 

 ; ==============================================================================
 ; 2 x i64
 ; ==============================================================================
 declare i32 @llvm.wasm.anytrue.v2i64(<2 x i64>)
 declare i32 @llvm.wasm.alltrue.v2i64(<2 x i64>)
 
 ; CHECK-LABEL: any_v2i64_trunc:
 ; CHECK-NEXT: .functype any_v2i64_trunc (v128) -> (i32){{$}}
-; CHECK-NEXT: i64x2.any_true $push[[R:[0-9]+]]=, $0{{$}}
+; CHECK-NEXT: v128.any_true $push[[R:[0-9]+]]=, $0{{$}}
 ; CHECK-NEXT: return $pop[[R]]{{$}}
 define i32 @any_v2i64_trunc(<2 x i64> %x) {
   %a = call i32 @llvm.wasm.anytrue.v2i64(<2 x i64> %x)
   %b = trunc i32 %a to i1
   %c = zext i1 %b to i32
   ret i32 %c
 }
 
 ; CHECK-LABEL: any_v2i64_ne:
 ; CHECK-NEXT: .functype any_v2i64_ne (v128) -> (i32){{$}}
-; CHECK-NEXT: i64x2.any_true $push[[R:[0-9]+]]=, $0{{$}}
+; CHECK-NEXT: v128.any_true $push[[R:[0-9]+]]=, $0{{$}}
 ; CHECK-NEXT: return $pop[[R]]{{$}}
 define i32 @any_v2i64_ne(<2 x i64> %x) {
   %a = call i32 @llvm.wasm.anytrue.v2i64(<2 x i64> %x)
   %b = icmp ne i32 %a, 0
   %c = zext i1 %b to i32
   ret i32 %c
 }
 
 ; CHECK-LABEL: any_v2i64_eq:
 ; CHECK-NEXT: .functype any_v2i64_eq (v128) -> (i32){{$}}
-; CHECK-NEXT: i64x2.any_true $push[[R:[0-9]+]]=, $0{{$}}
+; CHECK-NEXT: v128.any_true $push[[R:[0-9]+]]=, $0{{$}}
 ; CHECK-NEXT: return $pop[[R]]{{$}}
 define i32 @any_v2i64_eq(<2 x i64> %x) {
   %a = call i32 @llvm.wasm.anytrue.v2i64(<2 x i64> %x)
   %b = icmp eq i32 %a, 1
   %c = zext i1 %b to i32
   ret i32 %c
 }
 

llvm/test/MC/Disassembler/WebAssembly/wasm.txt

 # CHECK: i8x16.shuffle 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
 0xFD 0x0D 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F
 
 # Check LEB128 encoding of SIMD instructions
 # CHECK: i16x8.all_true
 0xFD 0x83 0x01
 
 # Including non-canonical LEB128 encodings
-# CHECK: i16x8.any_true
-# CHECK-NOT: i16x8.neg
+# CHECK: i16x8.q15mulr_sat_s
 0xFD 0x82 0x81 0x80 0x80 0x80 0x80 0x00
 
 # Check br_table, which has its own operand type.
 # CHECK: br_table {0, 1, 2}
 0x0E 0x02 0x00 0x01 0x02
 
 # This can mean end_block/end_loop/end_if/end_function/end_try..
 # CHECK: end
 0x0B

llvm/test/MC/WebAssembly/simd-encodings.s

main:
     v128.or
 
     # CHECK: v128.xor # encoding: [0xfd,0x51]
     v128.xor
 
     # CHECK: v128.bitselect # encoding: [0xfd,0x52]
     v128.bitselect
 
-    # TODO: v128.any_true # encoding: [0xfd,0x53]
+    # CHECK: v128.any_true # encoding: [0xfd,0x53]
+    v128.any_true
 
     # CHECK: v128.load8_lane 32, 1 # encoding: [0xfd,0x54,0x00,0x20,0x01]
     v128.load8_lane 32, 1
 
     # CHECK: v128.load16_lane 32, 1 # encoding: [0xfd,0x55,0x01,0x20,0x01]
     v128.load16_lane 32, 1
 
     # CHECK: v128.load32_lane 32, 1 # encoding: [0xfd,0x56,0x02,0x20,0x01]