[PowerPC] stop reverse mem op generation when the feeder has more than one users

[shchenz]

Summary

We should consider the feeder user number when we do reverse memory operation transformation. Otherwise, we may get negative impact.

[nemanjai]

LGTM.

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

14421

It is not clear why the fact that there is no D-Form makes this unprofitable.
Perhaps:

// If there are other uses of the shuffle, the swap cannot be avoided.
// Forcing the use of an X-Form (since swapped stores only have 
// X-Forms) without removing the swap is unprofitable.

[shchenz]

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

14421

Thanks. It was updated in the commit.

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

SDValue PPCTargetLowering::combineVReverseMemOP(ShuffleVectorSDNode *SVN,
   // It is conflict with PPCVSXSwapRemoval opt. So we don't do it.
   if (!Subtarget.hasP9Vector())
     return SDValue();
 
   if(!IsElementReverse(SVN))
     return SDValue();
 
   if (LSBase->getOpcode() == ISD::LOAD) {
+    // If the load has more than one user except the shufflevector instruction,
+    // it is not profitable to replace the shufflevector with a reverse load.
+    if (!LSBase->hasOneUse())
+      return SDValue();
+
     SDLoc dl(SVN);
     SDValue LoadOps[] = {LSBase->getChain(), LSBase->getBasePtr()};
     return DAG.getMemIntrinsicNode(
         PPCISD::LOAD_VEC_BE, dl, DAG.getVTList(VT, MVT::Other), LoadOps,
         LSBase->getMemoryVT(), LSBase->getMemOperand());
   }
 
   if (LSBase->getOpcode() == ISD::STORE) {
+    // If there are other uses of the shuffle, the swap cannot be avoided.
+    // Forcing the use of an X-Form (since swapped stores only have
+    // X-Forms) without removing the swap is unprofitable.
+    if (!SVN->hasOneUse())
+      return SDValue();
+
     SDLoc dl(LSBase);
     SDValue StoreOps[] = {LSBase->getChain(), SVN->getOperand(0),
                           LSBase->getBasePtr()};
     return DAG.getMemIntrinsicNode(
         PPCISD::STORE_VEC_BE, dl, DAG.getVTList(MVT::Other), StoreOps,
         LSBase->getMemoryVT(), LSBase->getMemOperand());
   }
 

llvm/test/CodeGen/PowerPC/vsx-shuffle-le-multiple-uses.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 
 ; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mattr=+vsx \
 ; RUN:   -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s
 
 define <2 x double> @loadHasMultipleUses(<2 x double>* %p1, <2 x double>* %p2) {
 ; CHECK-LABEL: loadHasMultipleUses:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lxv 0, 0(3)
+; CHECK-NEXT:    xxswapd 34, 0
 ; CHECK-NEXT:    stxv 0, 0(4)
-; CHECK-NEXT:    lxvd2x 34, 0, 3
 ; CHECK-NEXT:    blr
   %v1 = load <2 x double>, <2 x double>* %p1
   store <2 x double> %v1, <2 x double>* %p2, align 16
   %v2 = shufflevector <2 x double> %v1, <2 x double> %v1, <2 x i32> < i32 1, i32 0>
   ret <2 x double> %v2
 }
 
 define <2 x double> @storeHasMultipleUses(<2 x double> %v, <2 x double>* %p) {
 ; CHECK-LABEL: storeHasMultipleUses:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    xxswapd 0, 34
-; CHECK-NEXT:    addi 3, 5, 256
-; CHECK-NEXT:    stxvd2x 34, 0, 3
-; CHECK-NEXT:    xxlor 34, 0, 0
+; CHECK-NEXT:    xxswapd 34, 34
+; CHECK-NEXT:    stxv 34, 256(5)
 ; CHECK-NEXT:    blr
   %v1 = shufflevector <2 x double> %v, <2 x double> %v, <2 x i32> < i32 1, i32 0>
   %addr = getelementptr inbounds <2 x double>, <2 x double>* %p, i64 16
   store <2 x double> %v1, <2 x double>* %addr, align 16
   %v2 = shufflevector <2 x double> %v, <2 x double> %v, <2 x i32> < i32 1, i32 2>
   ret <2 x double> %v2
 }