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Differential D100031

[AMDGPU] SIFoldOperands: clean up tryConstantFoldOp
ClosedPublic

Authored by foad on Apr 7 2021, 5:57 AM.

Details

Reviewers
arsenm
rampitec
Commits
rG7c706af03b86: [AMDGPU] SIFoldOperands: clean up tryConstantFoldOp
Summary

First clean up the strange API of tryConstantFoldOp where it took an
immediate operand value, but no indication of which operand it was the
value for.

Second clean up the loop that calls tryConstantFoldOp so that it does
not have to restart from the beginning every time it folds an
instruction.

This is NFCI but there are some minor changes caused by the order in
which things are folded.

Diff Detail

Event Timeline

foad created this revision.Apr 7 2021, 5:57 AM
Herald added subscribers: kerbowa, hiraditya, t-tye and 6 others. · View Herald TranscriptApr 7 2021, 5:57 AM
foad requested review of this revision.Apr 7 2021, 5:57 AM
Herald added a project: Restricted Project. · View Herald TranscriptApr 7 2021, 5:57 AM
Herald added subscribers: llvm-commits, wdng. · View Herald Transcript
arsenm accepted this revision.Apr 7 2021, 5:58 AM
arsenm added inline comments.
llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
1212

The '\n' is redundant since MI print includes it already

This revision is now accepted and ready to land.Apr 7 2021, 5:58 AM
foad updated this revision to Diff 335793.Apr 7 2021, 6:16 AM

The '\n' is redundant since MI print includes it already

Fixed upstream and rebased.

Harbormaster completed remote builds in B97497: Diff 335788.Apr 7 2021, 6:30 AM
Harbormaster completed remote builds in B97499: Diff 335793.Apr 7 2021, 6:50 AM
This revision was landed with ongoing or failed builds.May 6 2021, 2:29 AM
Closed by commit rG7c706af03b86: [AMDGPU] SIFoldOperands: clean up tryConstantFoldOp (authored by foad). · Explain Why
This revision was automatically updated to reflect the committed changes.
foad added a commit: rG7c706af03b86: [AMDGPU] SIFoldOperands: clean up tryConstantFoldOp.

Revision Contents

PathSize
llvm/
lib/
Target/
AMDGPU/
119 lines
test/
CodeGen/
AMDGPU/
GlobalISel/
64 lines

Diff 343332

llvm/lib/Target/AMDGPU/SIFoldOperands.cpp

Show First 20 Lines • Show All 1,040 Lines • ▼ Show 20 Linesstatic MachineOperand *getImmOrMaterializedImm(MachineRegisterInfo &MRI,
} }
return &Op; return &Op;
} }
// Try to simplify operations with a constant that may appear after instruction // Try to simplify operations with a constant that may appear after instruction
// selection. // selection.
// TODO: See if a frame index with a fixed offset can fold. // TODO: See if a frame index with a fixed offset can fold.
static bool tryConstantFoldOp(MachineRegisterInfo &MRI, static bool tryConstantFoldOp(MachineRegisterInfo &MRI, const SIInstrInfo *TII,
const SIInstrInfo *TII, MachineInstr *MI) {
MachineInstr *MI,
MachineOperand *ImmOp) {
unsigned Opc = MI->getOpcode(); unsigned Opc = MI->getOpcode();
if (Opc == AMDGPU::V_NOT_B32_e64 || Opc == AMDGPU::V_NOT_B32_e32 ||
Opc == AMDGPU::S_NOT_B32) { int Src0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0);
MI->getOperand(1).ChangeToImmediate(~ImmOp->getImm()); if (Src0Idx == -1)
return false;
MachineOperand *Src0 = getImmOrMaterializedImm(MRI, MI->getOperand(Src0Idx));
if ((Opc == AMDGPU::V_NOT_B32_e64 || Opc == AMDGPU::V_NOT_B32_e32 ||
Opc == AMDGPU::S_NOT_B32) &&
Src0->isImm()) {
MI->getOperand(1).ChangeToImmediate(~Src0->getImm());
mutateCopyOp(*MI, TII->get(getMovOpc(Opc == AMDGPU::S_NOT_B32))); mutateCopyOp(*MI, TII->get(getMovOpc(Opc == AMDGPU::S_NOT_B32)));
return true; return true;
} }
int Src1Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1); int Src1Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1);
if (Src1Idx == -1) if (Src1Idx == -1)
return false; return false;
int Src0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0);
MachineOperand *Src0 = getImmOrMaterializedImm(MRI, MI->getOperand(Src0Idx));
MachineOperand *Src1 = getImmOrMaterializedImm(MRI, MI->getOperand(Src1Idx)); MachineOperand *Src1 = getImmOrMaterializedImm(MRI, MI->getOperand(Src1Idx));
if (!Src0->isImm() && !Src1->isImm()) if (!Src0->isImm() && !Src1->isImm())
return false; return false;
// and k0, k1 -> v_mov_b32 (k0 & k1) // and k0, k1 -> v_mov_b32 (k0 & k1)
// or k0, k1 -> v_mov_b32 (k0 | k1) // or k0, k1 -> v_mov_b32 (k0 | k1)
// xor k0, k1 -> v_mov_b32 (k0 ^ k1) // xor k0, k1 -> v_mov_b32 (k0 ^ k1)
▲ Show 20 Lines • Show All 115 Lines • ▼ Show 20 Linesvoid SIFoldOperands::foldInstOperand(MachineInstr &MI,
MachineOperand &OpToFold) const { MachineOperand &OpToFold) const {
// We need mutate the operands of new mov instructions to add implicit // We need mutate the operands of new mov instructions to add implicit
// uses of EXEC, but adding them invalidates the use_iterator, so defer // uses of EXEC, but adding them invalidates the use_iterator, so defer
// this. // this.
SmallVector<MachineInstr *, 4> CopiesToReplace; SmallVector<MachineInstr *, 4> CopiesToReplace;
SmallVector<FoldCandidate, 4> FoldList; SmallVector<FoldCandidate, 4> FoldList;
MachineOperand &Dst = MI.getOperand(0); MachineOperand &Dst = MI.getOperand(0);
bool FoldingImm = OpToFold.isImm() || OpToFold.isFI() || OpToFold.isGlobal(); if (OpToFold.isImm()) {
if (FoldingImm) { for (auto &UseMI :
unsigned NumLiteralUses = 0; make_early_inc_range(MRI->use_nodbg_instructions(Dst.getReg()))) {
MachineOperand *NonInlineUse = nullptr;
int NonInlineUseOpNo = -1;
bool Again;
do {
Again = false;
for (auto &Use : make_early_inc_range(MRI->use_nodbg_operands(Dst.getReg()))) {
MachineInstr *UseMI = Use.getParent();
unsigned OpNo = UseMI->getOperandNo(&Use);
// Folding the immediate may reveal operations that can be constant // Folding the immediate may reveal operations that can be constant
// folded or replaced with a copy. This can happen for example after // folded or replaced with a copy. This can happen for example after
// frame indices are lowered to constants or from splitting 64-bit // frame indices are lowered to constants or from splitting 64-bit
// constants. // constants.
// //
// We may also encounter cases where one or both operands are // We may also encounter cases where one or both operands are
// immediates materialized into a register, which would ordinarily not // immediates materialized into a register, which would ordinarily not
// be folded due to multiple uses or operand constraints. // be folded due to multiple uses or operand constraints.
if (tryConstantFoldOp(*MRI, TII, &UseMI))
LLVM_DEBUG(dbgs() << "Constant folded " << UseMI);
arsenmUnsubmitted
Not Done
ReplyInline Actions

The '\n' is redundant since MI print includes it already

arsenm: The '\n' is redundant since MI print includes it already
}
}
if (OpToFold.isImm() && tryConstantFoldOp(*MRI, TII, UseMI, &OpToFold)) { bool FoldingImm = OpToFold.isImm() || OpToFold.isFI() || OpToFold.isGlobal();
LLVM_DEBUG(dbgs() << "Constant folded " << *UseMI); if (FoldingImm) {
unsigned NumLiteralUses = 0;
MachineOperand *NonInlineUse = nullptr;
int NonInlineUseOpNo = -1;
// Some constant folding cases change the same immediate's use to a new for (auto &Use :
// instruction, e.g. and x, 0 -> 0. Make sure we re-visit the user make_early_inc_range(MRI->use_nodbg_operands(Dst.getReg()))) {
// again. The same constant folded instruction could also have a second MachineInstr *UseMI = Use.getParent();
// use operand. unsigned OpNo = UseMI->getOperandNo(&Use);
FoldList.clear();
Again = true;
break;
}
// Try to fold any inline immediate uses, and then only fold other // Try to fold any inline immediate uses, and then only fold other
// constants if they have one use. // constants if they have one use.
// //
// The legality of the inline immediate must be checked based on the use // The legality of the inline immediate must be checked based on the use
// operand, not the defining instruction, because 32-bit instructions // operand, not the defining instruction, because 32-bit instructions
// with 32-bit inline immediate sources may be used to materialize // with 32-bit inline immediate sources may be used to materialize
// constants used in 16-bit operands. // constants used in 16-bit operands.
// //
// e.g. it is unsafe to fold: // e.g. it is unsafe to fold:
// s_mov_b32 s0, 1.0 // materializes 0x3f800000 // s_mov_b32 s0, 1.0 // materializes 0x3f800000
// v_add_f16 v0, v1, s0 // 1.0 f16 inline immediate sees 0x00003c00 // v_add_f16 v0, v1, s0 // 1.0 f16 inline immediate sees 0x00003c00
// Folding immediates with more than one use will increase program size. // Folding immediates with more than one use will increase program size.
// FIXME: This will also reduce register usage, which may be better // FIXME: This will also reduce register usage, which may be better
// in some cases. A better heuristic is needed. // in some cases. A better heuristic is needed.
if (isInlineConstantIfFolded(TII, *UseMI, OpNo, OpToFold)) { if (isInlineConstantIfFolded(TII, *UseMI, OpNo, OpToFold)) {
foldOperand(OpToFold, UseMI, OpNo, FoldList, CopiesToReplace); foldOperand(OpToFold, UseMI, OpNo, FoldList, CopiesToReplace);
} else if (frameIndexMayFold(TII, *UseMI, OpNo, OpToFold)) { } else if (frameIndexMayFold(TII, *UseMI, OpNo, OpToFold)) {
foldOperand(OpToFold, UseMI, OpNo, FoldList, foldOperand(OpToFold, UseMI, OpNo, FoldList, CopiesToReplace);
CopiesToReplace);
} else { } else {
if (++NumLiteralUses == 1) { if (++NumLiteralUses == 1) {
NonInlineUse = &Use; NonInlineUse = &Use;
NonInlineUseOpNo = OpNo; NonInlineUseOpNo = OpNo;
} }
} }
} }
} while (Again);
if (NumLiteralUses == 1) { if (NumLiteralUses == 1) {
MachineInstr *UseMI = NonInlineUse->getParent(); MachineInstr *UseMI = NonInlineUse->getParent();
foldOperand(OpToFold, UseMI, NonInlineUseOpNo, FoldList, CopiesToReplace); foldOperand(OpToFold, UseMI, NonInlineUseOpNo, FoldList, CopiesToReplace);
} }
} else { } else {
// Folding register. // Folding register.
SmallVector <MachineOperand *, 4> UsesToProcess; SmallVector <MachineOperand *, 4> UsesToProcess;
▲ Show 20 Lines • Show All 547 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 3,205 Lines • ▼ Show 20 Lines; GFX10-NEXT: ; return to shader part epilog
%cast = bitcast <2 x i16> %result to i32 %cast = bitcast <2 x i16> %result to i32
ret i32 %cast ret i32 %cast
} }
define <2 x i16> @v_fshr_v2i16(<2 x i16> %lhs, <2 x i16> %rhs, <2 x i16> %amt) { define <2 x i16> @v_fshr_v2i16(<2 x i16> %lhs, <2 x i16> %rhs, <2 x i16> %amt) {
; GFX6-LABEL: v_fshr_v2i16: ; GFX6-LABEL: v_fshr_v2i16:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_mov_b32_e32 v6, 0xffff
; GFX6-NEXT: v_lshlrev_b32_e32 v5, 16, v5 ; GFX6-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; GFX6-NEXT: v_and_b32_e32 v4, 0xffff, v4 ; GFX6-NEXT: v_and_b32_e32 v4, v4, v6
; GFX6-NEXT: s_mov_b32 s5, 0xffff ; GFX6-NEXT: s_mov_b32 s5, 0xffff
; GFX6-NEXT: v_or_b32_e32 v4, v5, v4 ; GFX6-NEXT: v_or_b32_e32 v4, v5, v4
; GFX6-NEXT: v_and_b32_e32 v5, s5, v2 ; GFX6-NEXT: v_and_b32_e32 v5, s5, v2
; GFX6-NEXT: s_bfe_u32 s4, 1, 0x100000 ; GFX6-NEXT: s_bfe_u32 s4, 1, 0x100000
; GFX6-NEXT: v_lshrrev_b32_e32 v5, 1, v5 ; GFX6-NEXT: v_lshrrev_b32_e32 v5, 1, v5
; GFX6-NEXT: s_bfe_u32 s6, 14, 0x100000 ; GFX6-NEXT: s_bfe_u32 s6, 14, 0x100000
; GFX6-NEXT: v_lshlrev_b32_e32 v0, s4, v0 ; GFX6-NEXT: v_lshlrev_b32_e32 v0, s4, v0
; GFX6-NEXT: v_lshrrev_b32_e32 v5, s6, v5 ; GFX6-NEXT: v_lshrrev_b32_e32 v5, s6, v5
; GFX6-NEXT: v_or_b32_e32 v0, v0, v5 ; GFX6-NEXT: v_or_b32_e32 v0, v0, v5
; GFX6-NEXT: v_and_b32_e32 v5, s5, v3 ; GFX6-NEXT: v_and_b32_e32 v5, s5, v3
; GFX6-NEXT: v_lshrrev_b32_e32 v5, 1, v5 ; GFX6-NEXT: v_lshrrev_b32_e32 v5, 1, v5
; GFX6-NEXT: v_xor_b32_e32 v4, -1, v4 ; GFX6-NEXT: v_xor_b32_e32 v4, -1, v4
; GFX6-NEXT: v_lshlrev_b32_e32 v1, s4, v1 ; GFX6-NEXT: v_lshlrev_b32_e32 v1, s4, v1
; GFX6-NEXT: v_lshrrev_b32_e32 v5, s6, v5 ; GFX6-NEXT: v_lshrrev_b32_e32 v5, s6, v5
; GFX6-NEXT: v_lshlrev_b32_e32 v2, 1, v2 ; GFX6-NEXT: v_lshlrev_b32_e32 v2, 1, v2
; GFX6-NEXT: v_and_b32_e32 v6, 15, v4 ; GFX6-NEXT: v_and_b32_e32 v7, 15, v4
; GFX6-NEXT: v_or_b32_e32 v1, v1, v5 ; GFX6-NEXT: v_or_b32_e32 v1, v1, v5
; GFX6-NEXT: v_lshrrev_b32_e32 v5, 16, v4 ; GFX6-NEXT: v_lshrrev_b32_e32 v5, 16, v4
; GFX6-NEXT: v_xor_b32_e32 v4, -1, v4 ; GFX6-NEXT: v_xor_b32_e32 v4, -1, v4
; GFX6-NEXT: v_and_b32_e32 v4, 15, v4 ; GFX6-NEXT: v_and_b32_e32 v4, 15, v4
; GFX6-NEXT: v_and_b32_e32 v2, s5, v2 ; GFX6-NEXT: v_and_b32_e32 v2, v2, v6
; GFX6-NEXT: v_bfe_u32 v6, v6, 0, 16 ; GFX6-NEXT: v_bfe_u32 v7, v7, 0, 16
; GFX6-NEXT: v_lshrrev_b32_e32 v2, 1, v2 ; GFX6-NEXT: v_lshrrev_b32_e32 v2, 1, v2
; GFX6-NEXT: v_bfe_u32 v4, v4, 0, 16 ; GFX6-NEXT: v_bfe_u32 v4, v4, 0, 16
; GFX6-NEXT: v_lshrrev_b32_e32 v2, v4, v2 ; GFX6-NEXT: v_lshrrev_b32_e32 v2, v4, v2
; GFX6-NEXT: v_lshlrev_b32_e32 v0, v6, v0 ; GFX6-NEXT: v_lshlrev_b32_e32 v0, v7, v0
; GFX6-NEXT: v_or_b32_e32 v0, v0, v2 ; GFX6-NEXT: v_or_b32_e32 v0, v0, v2
; GFX6-NEXT: v_and_b32_e32 v2, 15, v5 ; GFX6-NEXT: v_and_b32_e32 v2, 15, v5
; GFX6-NEXT: v_xor_b32_e32 v4, -1, v5 ; GFX6-NEXT: v_xor_b32_e32 v4, -1, v5
; GFX6-NEXT: v_bfe_u32 v2, v2, 0, 16 ; GFX6-NEXT: v_bfe_u32 v2, v2, 0, 16
; GFX6-NEXT: v_lshlrev_b32_e32 v3, 1, v3 ; GFX6-NEXT: v_lshlrev_b32_e32 v3, 1, v3
; GFX6-NEXT: v_lshlrev_b32_e32 v1, v2, v1 ; GFX6-NEXT: v_lshlrev_b32_e32 v1, v2, v1
; GFX6-NEXT: v_and_b32_e32 v2, s5, v3 ; GFX6-NEXT: v_and_b32_e32 v2, v3, v6
; GFX6-NEXT: v_and_b32_e32 v4, 15, v4 ; GFX6-NEXT: v_and_b32_e32 v4, 15, v4
; GFX6-NEXT: v_lshrrev_b32_e32 v2, 1, v2 ; GFX6-NEXT: v_lshrrev_b32_e32 v2, 1, v2
; GFX6-NEXT: v_bfe_u32 v3, v4, 0, 16 ; GFX6-NEXT: v_bfe_u32 v3, v4, 0, 16
; GFX6-NEXT: v_lshrrev_b32_e32 v2, v3, v2 ; GFX6-NEXT: v_lshrrev_b32_e32 v2, v3, v2
; GFX6-NEXT: v_or_b32_e32 v1, v1, v2 ; GFX6-NEXT: v_or_b32_e32 v1, v1, v2
; GFX6-NEXT: s_setpc_b64 s[30:31] ; GFX6-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX8-LABEL: v_fshr_v2i16: ; GFX8-LABEL: v_fshr_v2i16:
▲ Show 20 Lines • Show All 875 Lines • ▼ Show 20 Lines
; GFX6-NEXT: v_lshlrev_b32_e32 v1, s4, v1 ; GFX6-NEXT: v_lshlrev_b32_e32 v1, s4, v1
; GFX6-NEXT: v_lshrrev_b32_e32 v10, s6, v10 ; GFX6-NEXT: v_lshrrev_b32_e32 v10, s6, v10
; GFX6-NEXT: v_lshlrev_b32_e32 v4, 1, v4 ; GFX6-NEXT: v_lshlrev_b32_e32 v4, 1, v4
; GFX6-NEXT: v_and_b32_e32 v11, 15, v8 ; GFX6-NEXT: v_and_b32_e32 v11, 15, v8
; GFX6-NEXT: v_or_b32_e32 v1, v1, v10 ; GFX6-NEXT: v_or_b32_e32 v1, v1, v10
; GFX6-NEXT: v_lshrrev_b32_e32 v10, 16, v8 ; GFX6-NEXT: v_lshrrev_b32_e32 v10, 16, v8
; GFX6-NEXT: v_xor_b32_e32 v8, -1, v8 ; GFX6-NEXT: v_xor_b32_e32 v8, -1, v8
; GFX6-NEXT: v_and_b32_e32 v8, 15, v8 ; GFX6-NEXT: v_and_b32_e32 v8, 15, v8
; GFX6-NEXT: v_and_b32_e32 v4, s5, v4 ; GFX6-NEXT: v_and_b32_e32 v4, v4, v12
; GFX6-NEXT: v_bfe_u32 v11, v11, 0, 16 ; GFX6-NEXT: v_bfe_u32 v11, v11, 0, 16
; GFX6-NEXT: v_lshrrev_b32_e32 v4, 1, v4 ; GFX6-NEXT: v_lshrrev_b32_e32 v4, 1, v4
; GFX6-NEXT: v_bfe_u32 v8, v8, 0, 16 ; GFX6-NEXT: v_bfe_u32 v8, v8, 0, 16
; GFX6-NEXT: v_lshrrev_b32_e32 v4, v8, v4 ; GFX6-NEXT: v_lshrrev_b32_e32 v4, v8, v4
; GFX6-NEXT: v_lshlrev_b32_e32 v0, v11, v0 ; GFX6-NEXT: v_lshlrev_b32_e32 v0, v11, v0
; GFX6-NEXT: v_or_b32_e32 v0, v0, v4 ; GFX6-NEXT: v_or_b32_e32 v0, v0, v4
; GFX6-NEXT: v_and_b32_e32 v4, 15, v10 ; GFX6-NEXT: v_and_b32_e32 v4, 15, v10
; GFX6-NEXT: v_xor_b32_e32 v8, -1, v10 ; GFX6-NEXT: v_xor_b32_e32 v8, -1, v10
; GFX6-NEXT: v_bfe_u32 v4, v4, 0, 16 ; GFX6-NEXT: v_bfe_u32 v4, v4, 0, 16
; GFX6-NEXT: v_lshlrev_b32_e32 v5, 1, v5 ; GFX6-NEXT: v_lshlrev_b32_e32 v5, 1, v5
; GFX6-NEXT: v_lshlrev_b32_e32 v1, v4, v1 ; GFX6-NEXT: v_lshlrev_b32_e32 v1, v4, v1
; GFX6-NEXT: v_and_b32_e32 v4, s5, v5 ; GFX6-NEXT: v_and_b32_e32 v4, v5, v12
; GFX6-NEXT: v_and_b32_e32 v8, 15, v8 ; GFX6-NEXT: v_and_b32_e32 v8, 15, v8
; GFX6-NEXT: v_lshrrev_b32_e32 v4, 1, v4 ; GFX6-NEXT: v_lshrrev_b32_e32 v4, 1, v4
; GFX6-NEXT: v_bfe_u32 v5, v8, 0, 16 ; GFX6-NEXT: v_bfe_u32 v5, v8, 0, 16
; GFX6-NEXT: v_lshrrev_b32_e32 v4, v5, v4 ; GFX6-NEXT: v_lshrrev_b32_e32 v4, v5, v4
; GFX6-NEXT: v_or_b32_e32 v1, v1, v4 ; GFX6-NEXT: v_or_b32_e32 v1, v1, v4
; GFX6-NEXT: v_and_b32_e32 v4, s5, v6 ; GFX6-NEXT: v_and_b32_e32 v4, v6, v12
; GFX6-NEXT: v_lshrrev_b32_e32 v4, 1, v4 ; GFX6-NEXT: v_lshrrev_b32_e32 v4, 1, v4
; GFX6-NEXT: v_lshlrev_b32_e32 v2, s4, v2 ; GFX6-NEXT: v_lshlrev_b32_e32 v2, s4, v2
; GFX6-NEXT: v_lshrrev_b32_e32 v4, s6, v4 ; GFX6-NEXT: v_lshrrev_b32_e32 v4, s6, v4
; GFX6-NEXT: v_or_b32_e32 v2, v2, v4 ; GFX6-NEXT: v_or_b32_e32 v2, v2, v4
; GFX6-NEXT: v_and_b32_e32 v4, s5, v7 ; GFX6-NEXT: v_and_b32_e32 v4, v7, v12
; GFX6-NEXT: v_lshrrev_b32_e32 v4, 1, v4 ; GFX6-NEXT: v_lshrrev_b32_e32 v4, 1, v4
; GFX6-NEXT: v_lshlrev_b32_e32 v3, s4, v3 ; GFX6-NEXT: v_lshlrev_b32_e32 v3, s4, v3
; GFX6-NEXT: v_lshrrev_b32_e32 v4, s6, v4 ; GFX6-NEXT: v_lshrrev_b32_e32 v4, s6, v4
; GFX6-NEXT: v_or_b32_e32 v3, v3, v4 ; GFX6-NEXT: v_or_b32_e32 v3, v3, v4
; GFX6-NEXT: v_lshlrev_b32_e32 v4, 1, v6 ; GFX6-NEXT: v_lshlrev_b32_e32 v4, 1, v6
; GFX6-NEXT: v_xor_b32_e32 v6, -1, v9 ; GFX6-NEXT: v_xor_b32_e32 v6, -1, v9
; GFX6-NEXT: v_and_b32_e32 v8, 15, v6 ; GFX6-NEXT: v_and_b32_e32 v8, 15, v6
; GFX6-NEXT: v_lshlrev_b32_e32 v5, 1, v7 ; GFX6-NEXT: v_lshlrev_b32_e32 v5, 1, v7
; GFX6-NEXT: v_lshrrev_b32_e32 v7, 16, v6 ; GFX6-NEXT: v_lshrrev_b32_e32 v7, 16, v6
; GFX6-NEXT: v_xor_b32_e32 v6, -1, v6 ; GFX6-NEXT: v_xor_b32_e32 v6, -1, v6
; GFX6-NEXT: v_and_b32_e32 v6, 15, v6 ; GFX6-NEXT: v_and_b32_e32 v6, 15, v6
; GFX6-NEXT: v_and_b32_e32 v4, s5, v4 ; GFX6-NEXT: v_and_b32_e32 v4, v4, v12
; GFX6-NEXT: v_bfe_u32 v8, v8, 0, 16 ; GFX6-NEXT: v_bfe_u32 v8, v8, 0, 16
; GFX6-NEXT: v_lshrrev_b32_e32 v4, 1, v4 ; GFX6-NEXT: v_lshrrev_b32_e32 v4, 1, v4
; GFX6-NEXT: v_bfe_u32 v6, v6, 0, 16 ; GFX6-NEXT: v_bfe_u32 v6, v6, 0, 16
; GFX6-NEXT: v_lshrrev_b32_e32 v4, v6, v4 ; GFX6-NEXT: v_lshrrev_b32_e32 v4, v6, v4
; GFX6-NEXT: v_lshlrev_b32_e32 v2, v8, v2 ; GFX6-NEXT: v_lshlrev_b32_e32 v2, v8, v2
; GFX6-NEXT: v_or_b32_e32 v2, v2, v4 ; GFX6-NEXT: v_or_b32_e32 v2, v2, v4
; GFX6-NEXT: v_and_b32_e32 v4, 15, v7 ; GFX6-NEXT: v_and_b32_e32 v4, 15, v7
; GFX6-NEXT: v_xor_b32_e32 v6, -1, v7 ; GFX6-NEXT: v_xor_b32_e32 v6, -1, v7
; GFX6-NEXT: v_bfe_u32 v4, v4, 0, 16 ; GFX6-NEXT: v_bfe_u32 v4, v4, 0, 16
; GFX6-NEXT: v_lshlrev_b32_e32 v3, v4, v3 ; GFX6-NEXT: v_lshlrev_b32_e32 v3, v4, v3
; GFX6-NEXT: v_and_b32_e32 v4, s5, v5 ; GFX6-NEXT: v_and_b32_e32 v4, v5, v12
; GFX6-NEXT: v_and_b32_e32 v6, 15, v6 ; GFX6-NEXT: v_and_b32_e32 v6, 15, v6
; GFX6-NEXT: v_lshrrev_b32_e32 v4, 1, v4 ; GFX6-NEXT: v_lshrrev_b32_e32 v4, 1, v4
; GFX6-NEXT: v_bfe_u32 v5, v6, 0, 16 ; GFX6-NEXT: v_bfe_u32 v5, v6, 0, 16
; GFX6-NEXT: v_lshrrev_b32_e32 v4, v5, v4 ; GFX6-NEXT: v_lshrrev_b32_e32 v4, v5, v4
; GFX6-NEXT: v_or_b32_e32 v3, v3, v4 ; GFX6-NEXT: v_or_b32_e32 v3, v3, v4
; GFX6-NEXT: s_setpc_b64 s[30:31] ; GFX6-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX8-LABEL: v_fshr_v4i16: ; GFX8-LABEL: v_fshr_v4i16:
; GFX8: ; %bb.0: ; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_lshrrev_b16_e32 v7, 1, v2 ; GFX8-NEXT: v_lshrrev_b16_e32 v7, 1, v2
; GFX8-NEXT: v_lshlrev_b16_e32 v6, 1, v0 ; GFX8-NEXT: v_lshlrev_b16_e32 v6, 1, v0
; GFX8-NEXT: v_lshrrev_b16_e32 v7, 14, v7 ; GFX8-NEXT: v_lshrrev_b16_e32 v7, 14, v7
; GFX8-NEXT: v_or_b32_e32 v6, v6, v7 ; GFX8-NEXT: v_or_b32_e32 v6, v6, v7
; GFX8-NEXT: v_mov_b32_e32 v7, 1 ; GFX8-NEXT: v_mov_b32_e32 v7, 1
; GFX8-NEXT: v_lshrrev_b16_sdwa v8, v7, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 ; GFX8-NEXT: v_lshrrev_b16_sdwa v8, v7, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; GFX8-NEXT: v_xor_b32_e32 v4, -1, v4 ; GFX8-NEXT: v_xor_b32_e32 v4, -1, v4
; GFX8-NEXT: v_lshlrev_b16_sdwa v0, v7, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 ; GFX8-NEXT: v_lshlrev_b16_sdwa v0, v7, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; GFX8-NEXT: v_lshrrev_b16_e32 v8, 14, v8 ; GFX8-NEXT: v_lshrrev_b16_e32 v8, 14, v8
; GFX8-NEXT: v_or_b32_e32 v0, v0, v8 ; GFX8-NEXT: v_or_b32_e32 v0, v0, v8
; GFX8-NEXT: v_lshlrev_b16_e32 v8, 1, v2 ; GFX8-NEXT: v_lshlrev_b16_e32 v8, 1, v2
; GFX8-NEXT: v_and_b32_e32 v10, 15, v4 ; GFX8-NEXT: v_lshlrev_b16_sdwa v2, v7, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; GFX8-NEXT: v_lshrrev_b32_e32 v9, 16, v4 ; GFX8-NEXT: v_and_b32_e32 v9, 15, v4
; GFX8-NEXT: v_lshrrev_b32_e32 v7, 16, v4
; GFX8-NEXT: v_xor_b32_e32 v4, -1, v4 ; GFX8-NEXT: v_xor_b32_e32 v4, -1, v4
; GFX8-NEXT: v_and_b32_e32 v4, 15, v4 ; GFX8-NEXT: v_and_b32_e32 v4, 15, v4
; GFX8-NEXT: v_lshrrev_b16_e32 v8, 1, v8 ; GFX8-NEXT: v_lshrrev_b16_e32 v8, 1, v8
; GFX8-NEXT: v_lshlrev_b16_sdwa v2, v7, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 ; GFX8-NEXT: v_lshlrev_b16_e32 v6, v9, v6
; GFX8-NEXT: v_lshrrev_b16_e32 v4, v4, v8 ; GFX8-NEXT: v_lshrrev_b16_e32 v4, v4, v8
; GFX8-NEXT: v_xor_b32_e32 v8, -1, v9
; GFX8-NEXT: v_lshlrev_b16_e32 v6, v10, v6
; GFX8-NEXT: v_or_b32_e32 v4, v6, v4 ; GFX8-NEXT: v_or_b32_e32 v4, v6, v4
; GFX8-NEXT: v_and_b32_e32 v6, 15, v9 ; GFX8-NEXT: v_and_b32_e32 v6, 15, v7
; GFX8-NEXT: v_and_b32_e32 v8, 15, v8 ; GFX8-NEXT: v_xor_b32_e32 v7, -1, v7
; GFX8-NEXT: v_and_b32_e32 v7, 15, v7
; GFX8-NEXT: v_lshrrev_b16_e32 v2, 1, v2 ; GFX8-NEXT: v_lshrrev_b16_e32 v2, 1, v2
; GFX8-NEXT: v_lshlrev_b16_e32 v0, v6, v0 ; GFX8-NEXT: v_lshlrev_b16_e32 v0, v6, v0
; GFX8-NEXT: v_lshrrev_b16_e32 v2, v8, v2 ; GFX8-NEXT: v_lshrrev_b16_e32 v2, v7, v2
; GFX8-NEXT: v_or_b32_e32 v0, v0, v2 ; GFX8-NEXT: v_or_b32_e32 v0, v0, v2
; GFX8-NEXT: v_mov_b32_e32 v2, 16 ; GFX8-NEXT: v_mov_b32_e32 v2, 16
; GFX8-NEXT: v_lshlrev_b32_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 ; GFX8-NEXT: v_lshlrev_b32_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX8-NEXT: v_lshrrev_b16_e32 v6, 1, v3 ; GFX8-NEXT: v_lshrrev_b16_e32 v6, 1, v3
; GFX8-NEXT: v_or_b32_sdwa v0, v4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD ; GFX8-NEXT: v_or_b32_sdwa v0, v4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX8-NEXT: v_lshlrev_b16_e32 v4, 1, v1 ; GFX8-NEXT: v_lshlrev_b16_e32 v4, 1, v1
; GFX8-NEXT: v_lshrrev_b16_e32 v6, 14, v6 ; GFX8-NEXT: v_lshrrev_b16_e32 v6, 14, v6
; GFX8-NEXT: v_or_b32_e32 v4, v4, v6 ; GFX8-NEXT: v_or_b32_e32 v4, v4, v6
; GFX8-NEXT: v_lshrrev_b16_sdwa v6, v7, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 ; GFX8-NEXT: v_mov_b32_e32 v6, 1
; GFX8-NEXT: v_lshrrev_b16_sdwa v7, v6, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; GFX8-NEXT: v_xor_b32_e32 v5, -1, v5 ; GFX8-NEXT: v_xor_b32_e32 v5, -1, v5
; GFX8-NEXT: v_lshlrev_b16_sdwa v1, v7, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 ; GFX8-NEXT: v_lshlrev_b16_sdwa v1, v6, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; GFX8-NEXT: v_lshrrev_b16_e32 v6, 14, v6 ; GFX8-NEXT: v_lshrrev_b16_e32 v7, 14, v7
; GFX8-NEXT: v_or_b32_e32 v1, v1, v6 ; GFX8-NEXT: v_or_b32_e32 v1, v1, v7
; GFX8-NEXT: v_lshlrev_b16_e32 v6, 1, v3 ; GFX8-NEXT: v_lshlrev_b16_e32 v7, 1, v3
; GFX8-NEXT: v_lshlrev_b16_sdwa v3, v7, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 ; GFX8-NEXT: v_lshlrev_b16_sdwa v3, v6, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; GFX8-NEXT: v_and_b32_e32 v8, 15, v5 ; GFX8-NEXT: v_and_b32_e32 v8, 15, v5
; GFX8-NEXT: v_lshrrev_b32_e32 v7, 16, v5 ; GFX8-NEXT: v_lshrrev_b32_e32 v6, 16, v5
; GFX8-NEXT: v_xor_b32_e32 v5, -1, v5 ; GFX8-NEXT: v_xor_b32_e32 v5, -1, v5
; GFX8-NEXT: v_and_b32_e32 v5, 15, v5 ; GFX8-NEXT: v_and_b32_e32 v5, 15, v5
; GFX8-NEXT: v_lshrrev_b16_e32 v6, 1, v6 ; GFX8-NEXT: v_lshrrev_b16_e32 v7, 1, v7
; GFX8-NEXT: v_lshrrev_b16_e32 v5, v5, v6
; GFX8-NEXT: v_lshlrev_b16_e32 v4, v8, v4 ; GFX8-NEXT: v_lshlrev_b16_e32 v4, v8, v4
; GFX8-NEXT: v_xor_b32_e32 v6, -1, v7 ; GFX8-NEXT: v_lshrrev_b16_e32 v5, v5, v7
; GFX8-NEXT: v_or_b32_e32 v4, v4, v5 ; GFX8-NEXT: v_or_b32_e32 v4, v4, v5
; GFX8-NEXT: v_and_b32_e32 v5, 15, v7 ; GFX8-NEXT: v_and_b32_e32 v5, 15, v6
; GFX8-NEXT: v_xor_b32_e32 v6, -1, v6
; GFX8-NEXT: v_and_b32_e32 v6, 15, v6 ; GFX8-NEXT: v_and_b32_e32 v6, 15, v6
; GFX8-NEXT: v_lshrrev_b16_e32 v3, 1, v3 ; GFX8-NEXT: v_lshrrev_b16_e32 v3, 1, v3
; GFX8-NEXT: v_lshlrev_b16_e32 v1, v5, v1 ; GFX8-NEXT: v_lshlrev_b16_e32 v1, v5, v1
; GFX8-NEXT: v_lshrrev_b16_e32 v3, v6, v3 ; GFX8-NEXT: v_lshrrev_b16_e32 v3, v6, v3
; GFX8-NEXT: v_or_b32_e32 v1, v1, v3 ; GFX8-NEXT: v_or_b32_e32 v1, v1, v3
; GFX8-NEXT: v_lshlrev_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 ; GFX8-NEXT: v_lshlrev_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX8-NEXT: v_or_b32_sdwa v1, v4, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD ; GFX8-NEXT: v_or_b32_sdwa v1, v4, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX8-NEXT: s_setpc_b64 s[30:31] ; GFX8-NEXT: s_setpc_b64 s[30:31]
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