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[RISCV] Add new vector instructions in v0.10.
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Authored by HsiangKai on Feb 1 2021, 5:33 AM.

Details

Summary
  • Add new vector instructions in v0.10.
    • load/store for mask value vle1.v vse1.v
    • vsetivli for 0-31 immediate vector length.
  • Rename vector instructions in v0.10.
    • vfrsqrte7 -> vfrsqrt7
    • vfrece7 -> vfrec7
  • Reserve memory width encodings for EEW>128b.

Diff Detail

Event Timeline

HsiangKai created this revision.Feb 1 2021, 5:33 AM
HsiangKai requested review of this revision.Feb 1 2021, 5:33 AM
Herald added a project: Restricted Project. · View Herald TranscriptFeb 1 2021, 5:33 AM
Herald added a subscriber: MaskRay. · View Herald Transcript
HsiangKai edited the summary of this revision. (Show Details)Feb 1 2021, 5:58 AM
HsiangKai edited the summary of this revision. (Show Details)Feb 1 2021, 6:02 AM
HsiangKai edited the summary of this revision. (Show Details)
kito-cheng added inline comments.Feb 1 2021, 6:12 AM
llvm/test/CodeGen/RISCV/rvv/rv32-vsetvli-intrinsics.ll
19

zero is alias of x0, so I think here should be 0 rather than zero.

llvm/test/CodeGen/RISCV/rvv/rv64-vsetvli-intrinsics.ll
28

Ditto.

HsiangKai updated this revision to Diff 320608.Feb 1 2021, 2:38 PM
khchen added a comment.Feb 1 2021, 4:23 PM

LGTM.
Do we need to have a test for vsetivli in invalid.s?

HsiangKai updated this revision to Diff 320641.Feb 1 2021, 5:25 PM

Add test cases for invalid vsetivli.

HsiangKai updated this revision to Diff 320645.Feb 1 2021, 5:35 PM

Move vfrsqrt7 and vfrec7 test cases under RISCV/rvv directory.

HsiangKai updated this revision to Diff 320706.Feb 2 2021, 12:49 AM

Rebase. According to D95833, use ComplexPattern instead of SDNodeXForm for vl operand.

frasercrmck added inline comments.Feb 2 2021, 1:45 AM
llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
1222

Brace on newline seems to differ from the rest of the file (at least in the lines above and below)

HsiangKai updated this revision to Diff 320724.Feb 2 2021, 2:54 AM

Address @frasercrmck's comments.

frasercrmck added inline comments.Feb 2 2021, 3:00 AM
llvm/lib/Target/RISCV/RISCVCleanupVSETVLI.cpp
62

Is this currently safe, or is it a FIXME to enable additional optimizations? It might be reassuring to have some tests which show vsetvli and vsetivli behave correctly together.

HsiangKai updated this revision to Diff 320963.Feb 2 2021, 6:28 PM

Consider vsetivli in RISCVCleanupVSETVLI.

HsiangKai marked 4 inline comments as done.Feb 2 2021, 6:30 PM
craig.topper added inline comments.Feb 2 2021, 7:24 PM
llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
232

Might be better to just select the opcode here and put the TTI->get call into the BuildMI below?

HsiangKai updated this revision to Diff 320978.Feb 2 2021, 8:04 PM

Address @craig.topper's comments.

HsiangKai marked an inline comment as done.Feb 2 2021, 8:05 PM
This revision is now accepted and ready to land.Feb 2 2021, 8:26 PM
This revision was landed with ongoing or failed builds.Feb 2 2021, 9:29 PM
This revision was automatically updated to reflect the committed changes.