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[P10] [Power PC] Exploiting new load rightmost vector element instructions.
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Authored by Conanap on Jan 15 2021, 11:57 AM.

Details

Summary

This pull request implements patterns to exploit the load rightmost vector
element instructions for loading element 0 on little endian PowerPC subtargets
into v8i16 and v16i8 vector registers for i16 and i8 data types.

Diff Detail

Event Timeline

kamaub created this revision.Jan 15 2021, 11:57 AM
kamaub requested review of this revision.Jan 15 2021, 11:57 AM
Herald added a project: Restricted Project. · View Herald TranscriptJan 15 2021, 11:57 AM
amyk added inline comments.Jan 21 2021, 3:48 PM
llvm/lib/Target/PowerPC/PPCInstrVSX.td
3958

nit: End sentences with a period.

3959

Might be a silly question, but can you clarify the "faux equivalent pattern" part?
Also a small nit, maybe end the sentence here and start the next sentence with, "The NoP10Vector predicate..."

llvm/test/CodeGen/PowerPC/load-rightmost-vector-elt.ll
9

Add P9 run line, too?

Conanap commandeered this revision.Mar 8 2021, 7:30 AM
Conanap added a reviewer: kamaub.
Conanap updated this revision to Diff 329020.Mar 8 2021, 8:11 AM
Conanap marked 3 inline comments as done.

Updated a comment and a test case

amyk accepted this revision as: amyk.Mar 8 2021, 9:35 AM

I think this LGTM aside from the minor nit on the test case. I am OK with it being updated on the commit.

llvm/test/CodeGen/PowerPC/load-rightmost-vector-elt.ll
12

For the P9 run lines, you can probably do just one CHECK-P9 (or check-prefixes if needed?) so we don't have double of the same P9 checks.

This revision is now accepted and ready to land.Mar 8 2021, 9:35 AM
nemanjai added inline comments.Mar 9 2021, 7:39 AM
llvm/lib/Target/PowerPC/PPCInstrVSX.td
3972

The patterns appear to be the same. Why do we split this out into LE/BE if the patterns are endianness neutral? If they are the same, merge them into a single block that doesn't have an endianness predicate.