[AArch64] LORID_EL1 register must be treated as read-only

[vsukharev]

Summary

While LORID_EL1 register is read-only as per the spec, http://reviews.llvm.org/rL235105 doesn't address that.

Patch by: John Brawn

Related to: http://reviews.llvm.org/rL235105

llvm/trunk/lib/Target/AArch64/Utils/AArch64BaseInfo.cpp

const AArch64NamedImmMapper::Mapping AArch64SysReg::MRSMapper::MRSMappings[] = {
   // GICv3 registers
   {"icc_iar1_el1", ICC_IAR1_EL1, 0},
   {"icc_iar0_el1", ICC_IAR0_EL1, 0},
   {"icc_hppir1_el1", ICC_HPPIR1_EL1, 0},
   {"icc_hppir0_el1", ICC_HPPIR0_EL1, 0},
   {"icc_rpr_el1", ICC_RPR_EL1, 0},
   {"ich_vtr_el2", ICH_VTR_EL2, 0},
   {"ich_eisr_el2", ICH_EISR_EL2, 0},
-  {"ich_elsr_el2", ICH_ELSR_EL2, 0}
+  {"ich_elsr_el2", ICH_ELSR_EL2, 0},
+
+  // v8.1a "Limited Ordering Regions" extension-specific system registers
+  {"lorid_el1", LORID_EL1, AArch64::HasV8_1aOps},
 };
 
 AArch64SysReg::MRSMapper::MRSMapper() {
     InstMappings = &MRSMappings[0];
     NumInstMappings = llvm::array_lengthof(MRSMappings);
 }
 
 const AArch64NamedImmMapper::Mapping AArch64SysReg::MSRMapper::MSRMappings[] = {
const AArch64NamedImmMapper::Mapping AArch64SysReg::SysRegMapper::SysRegMappings[] = {
   // v8.1a "Privileged Access Never" extension-specific system registers
   {"pan", PAN, AArch64::HasV8_1aOps},
 
   // v8.1a "Limited Ordering Regions" extension-specific system registers
   {"lorsa_el1", LORSA_EL1, AArch64::HasV8_1aOps},
   {"lorea_el1", LOREA_EL1, AArch64::HasV8_1aOps},
   {"lorn_el1", LORN_EL1, AArch64::HasV8_1aOps},
   {"lorc_el1", LORC_EL1, AArch64::HasV8_1aOps},
-  {"lorid_el1", LORID_EL1, AArch64::HasV8_1aOps},
 
   // v8.1a "Virtualization host extensions" system registers
   {"ttbr1_el2", TTBR1_EL2, AArch64::HasV8_1aOps},
   {"contextidr_el2", CONTEXTIDR_EL2, AArch64::HasV8_1aOps},
   {"cnthv_tval_el2", CNTHV_TVAL_EL2, AArch64::HasV8_1aOps},
   {"cnthv_cval_el2", CNTHV_CVAL_EL2, AArch64::HasV8_1aOps},
   {"cnthv_ctl_el2", CNTHV_CTL_EL2, AArch64::HasV8_1aOps},
   {"sctlr_el12", SCTLR_EL12, AArch64::HasV8_1aOps},
const AArch64NamedImmMapper::Mapping AArch64SysReg::SysRegMapper::SysRegMappings[] = {
   {"cntv_tval_el02", CNTV_TVAL_EL02, AArch64::HasV8_1aOps},
   {"cntv_ctl_el02", CNTV_CTL_EL02, AArch64::HasV8_1aOps},
   {"cntv_cval_el02", CNTV_CVAL_EL02, AArch64::HasV8_1aOps},
   {"spsr_el12", SPSR_EL12, AArch64::HasV8_1aOps},
   {"elr_el12", ELR_EL12, AArch64::HasV8_1aOps},
 };
 
 uint32_t
-AArch64SysReg::SysRegMapper::fromString(StringRef Name, uint64_t FeatureBits, 
+AArch64SysReg::SysRegMapper::fromString(StringRef Name, uint64_t FeatureBits,
                                         bool &Valid) const {
   std::string NameLower = Name.lower();
 
   // First search the registers shared by all
   for (unsigned i = 0; i < array_lengthof(SysRegMappings); ++i) {
     if (SysRegMappings[i].isNameEqual(NameLower, FeatureBits)) {
       Valid = true;
       return SysRegMappings[i].Value;

llvm/trunk/test/MC/AArch64/armv8.1a-lor.s

-// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.1a < %s | FileCheck %s
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.1a < %s 2>%t | FileCheck %s
+// RUN: FileCheck --check-prefix=CHECK-ERROR %s <%t
 
 
 //------------------------------------------------------------------------------
 // Load acquire / store release
 //------------------------------------------------------------------------------
         ldlarb w0,[x1]
         ldlarh w0,[x1]
         ldlar  w0,[x1]
// CHECK:   stllr  x0, [x1]   // encoding: [0x20,0x7c,0x9f,0xc8]
         msr    LORN_EL1, x0
         msr    LORC_EL1, x0
         mrs    x0, LORID_EL1
 // CHECK:   msr    LORSA_EL1, x0 // encoding: [0x00,0xa4,0x18,0xd5]
 // CHECK:   msr    LOREA_EL1, x0 // encoding: [0x20,0xa4,0x18,0xd5]
 // CHECK:   msr    LORN_EL1, x0  // encoding: [0x40,0xa4,0x18,0xd5]
 // CHECK:   msr    LORC_EL1, x0  // encoding: [0x60,0xa4,0x18,0xd5]
 // CHECK:   mrs    x0, LORID_EL1 // encoding: [0xe0,0xa4,0x38,0xd5]
+
+        ldlarb w0,[w1]
+        ldlarh x0,[x1]
+        stllrb w0,[w1]
+        stllrh x0,[x1]
+        stllr  w0,[w1]
+        msr    LORSA_EL1, #0
+        msr    LOREA_EL1, #0
+        msr    LORN_EL1, #0
+        msr    LORC_EL1, #0
+        msr    LORID_EL1, x0
+        mrs    LORID_EL1, #0
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:         ldlarb w0,[w1]
+// CHECK-ERROR:                    ^
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:         ldlarh x0,[x1]
+// CHECK-ERROR:                ^
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:         stllrb w0,[w1]
+// CHECK-ERROR:                    ^
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:         stllrh x0,[x1]
+// CHECK-ERROR:                ^
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:         stllr  w0,[w1]
+// CHECK-ERROR:                    ^
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:         msr     LORSA_EL1, #0
+// CHECK-ERROR:                            ^
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:         msr     LOREA_EL1, #0
+// CHECK-ERROR:                            ^
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:         msr     LORN_EL1, #0
+// CHECK-ERROR:                           ^
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:         msr     LORC_EL1, #0
+// CHECK-ERROR:                           ^
+// CHECK-ERROR: error: expected writable system register or pstate
+// CHECK-ERROR:         msr     LORID_EL1, x0
+// CHECK-ERROR:                 ^
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:         mrs     LORID_EL1, #0
+// CHECK-ERROR:                 ^

llvm/trunk/test/MC/Disassembler/AArch64/armv8.1a-lor.txt

 # CHECK:   stllrb w0, [x1]
 # CHECK:   stllrh w0, [x1]
 # CHECK:   stllr  w0, [x1]
 # CHECK:   stllr  x0, [x1]
 0x00,0xa4,0x18,0xd5
 0x20,0xa4,0x18,0xd5
 0x40,0xa4,0x18,0xd5
 0x60,0xa4,0x18,0xd5
-0xe0,0xa4,0x38,0xd5
+0xe0,0xa4,0x18,0xd5
 # CHECK:   msr LORSA_EL1, x0
 # CHECK:   msr LOREA_EL1, x0
 # CHECK:   msr LORN_EL1, x0
 # CHECK:   msr LORC_EL1, x0
+# CHECK:   msr S3_0_C10_C4_7, x0
+0x00,0xa4,0x38,0xd5
+0x20,0xa4,0x38,0xd5
+0x40,0xa4,0x38,0xd5
+0x60,0xa4,0x38,0xd5
+0xe0,0xa4,0x38,0xd5
+# CHECK:   mrs x0, LORSA_EL1
+# CHECK:   mrs x0, LOREA_EL1
+# CHECK:   mrs x0, LORN_EL1
+# CHECK:   mrs x0, LORC_EL1
 # CHECK:   mrs x0, LORID_EL1