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aemerson (Amara Emerson)
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User Since
Sep 9 2013, 3:45 AM (383 w, 5 d)

The sea was angry that day, my friends - like an old man trying to send back soup in a deli.

Recent Activity

Today

aemerson accepted D94350: [GlobalISel] Combine (a[0]) | (a[1] << k1) | ...| (a[m] << kn) into a wide load.

LGTM.

Sat, Jan 16, 11:59 AM · Restricted Project

Yesterday

aemerson committed rG8456c3a78928: AArch64: fix regression introduced by fcmp immediate selection. (authored by aemerson).
AArch64: fix regression introduced by fcmp immediate selection.
Fri, Jan 15, 10:53 PM
aemerson committed rGaa8a2d8a3da3: [AArch64][GlobalISel] Select immediate fcmp if the zero is on the LHS. (authored by aemerson).
[AArch64][GlobalISel] Select immediate fcmp if the zero is on the LHS.
Fri, Jan 15, 2:32 PM
aemerson committed rG89e84dec1879: [AArch64][GlobalISel] Fix fallbacks introduced for G_SITOFP in… (authored by aemerson).
[AArch64][GlobalISel] Fix fallbacks introduced for G_SITOFP in…
Fri, Jan 15, 1:11 AM

Thu, Jan 14

aemerson committed rG8f283cafddfa: [AArch64][GlobalISel] Add selection support for fpr bank source variants of… (authored by aemerson).
[AArch64][GlobalISel] Add selection support for fpr bank source variants of…
Thu, Jan 14, 7:31 PM
aemerson closed D94702: [AArch64][GlobalISel] Add selection support for fpr bank source variants of G_SITOFP and G_UITOFP..
Thu, Jan 14, 7:31 PM · Restricted Project
aemerson committed rG036bc798f2ae: [AArch64][GlobalISel] Assign FPR banks to loads which are used by integer… (authored by aemerson).
[AArch64][GlobalISel] Assign FPR banks to loads which are used by integer…
Thu, Jan 14, 4:34 PM
aemerson closed D94701: [AArch64][GlobalISel] Assign FPR banks to loads which are used by integer->float conversions..
Thu, Jan 14, 4:33 PM · Restricted Project
aemerson added a comment to D94641: [AArch64][GlobalISel] Use wzr/xzr for FP stores of zero.

It it possible to extend the existing combine in prelegalizer combiner to handle this too? Or will that cause us to still miss some cases?

The problem with that combine is it looks for G_FCONSTANTS which are only used by stores, so as is, it would miss cases.

I think that we could probably replace that combine with something similar to this though.

Thu, Jan 14, 4:29 PM · Restricted Project
aemerson accepted D94705: [MIPatternMatch] Add m_OneNonDBGUse.

LGTM.

Thu, Jan 14, 4:24 PM · Restricted Project
aemerson added inline comments to D94701: [AArch64][GlobalISel] Assign FPR banks to loads which are used by integer->float conversions..
Thu, Jan 14, 4:12 PM · Restricted Project
aemerson added a comment to D94350: [GlobalISel] Combine (a[0]) | (a[1] << k1) | ...| (a[m] << kn) into a wide load.

We also need to check for the strict-align function attribute before we generate wider loads.

Shouldn't the legalizer check alignment requirements on the load? Or is this something different?

Each pass has to respect the semantics though. At the moment we fall back in the translator for strict-align, but when we do add support places like this will need to correct. Unless you add alignment checks for this combine, this might create unaligned wide loads which are illegal with strict-align, since we’re not allowed to assume that unaligned loads are safe.

Thu, Jan 14, 4:11 PM · Restricted Project
aemerson requested review of D94702: [AArch64][GlobalISel] Add selection support for fpr bank source variants of G_SITOFP and G_UITOFP..
Thu, Jan 14, 11:29 AM · Restricted Project
aemerson requested review of D94701: [AArch64][GlobalISel] Assign FPR banks to loads which are used by integer->float conversions..
Thu, Jan 14, 11:27 AM · Restricted Project
aemerson added a comment to D94641: [AArch64][GlobalISel] Use wzr/xzr for FP stores of zero.

It it possible to extend the existing combine in prelegalizer combiner to handle this too? Or will that cause us to still miss some cases?

Thu, Jan 14, 11:25 AM · Restricted Project

Wed, Jan 13

aemerson added a comment to D94641: [AArch64][GlobalISel] Use wzr/xzr for FP stores of zero.

Why is this in lowering instead of combine?

Wed, Jan 13, 5:48 PM · Restricted Project
aemerson added a comment to D94350: [GlobalISel] Combine (a[0]) | (a[1] << k1) | ...| (a[m] << kn) into a wide load.

We also need to check for the strict-align function attribute before we generate wider loads.

Wed, Jan 13, 10:55 AM · Restricted Project
aemerson accepted D94578: AArch64/GlobalISel: Factor out parametersInCSRMatch.

LGTM.

Wed, Jan 13, 9:29 AM · Restricted Project
aemerson updated the diff for D94264: [GlobalISel] Add MachineInstNumbering to CSEInfo and propagate CSE throughout AArch64 pipeline..

Fix clang-format warnings.

Wed, Jan 13, 9:26 AM · Restricted Project

Tue, Jan 12

aemerson updated the diff for D94264: [GlobalISel] Add MachineInstNumbering to CSEInfo and propagate CSE throughout AArch64 pipeline..

Improve the performance of the insertion queue flushing.

Tue, Jan 12, 10:46 PM · Restricted Project
aemerson added a comment to D94350: [GlobalISel] Combine (a[0]) | (a[1] << k1) | ...| (a[m] << kn) into a wide load.
  • Avg regs/missed combine is the number of registers in RegsToVisit when the combine misses

Does this metric count the misses where there were no registers?

Tue, Jan 12, 12:34 PM · Restricted Project
aemerson added a comment to D94350: [GlobalISel] Combine (a[0]) | (a[1] << k1) | ...| (a[m] << kn) into a wide load.

Here's some measurements:

                     O0 compile   O0 code       #Missed   #Missed    Avg regs/      | Os compile   Os code      #Missed   #Missed    Avg regs/
                     time change  size change   combines  (> 1 reg)  missed combine | time change  size change  combines  (> 1 reg)  missed combine
bullet               0.25%         0.00%        22        4          0.5            |  0.56%       0.00%        138       14         0.3
kc                   0.05%         0.00%        2         0          0.0            |  0.76%       0.00%        66        0          0.0
lencod              -0.18%         0.00%        89        20         0.6            |  0.31%       0.00%        508       34         0.2
SPASS                0.09%         0.00%        1         1          3.0            |  0.37%       0.00%        146       4          0.0
consumer-typeset    -0.27%         0.00%        369       52         0.3            |  0.17%       0.00%        625       61         0.2
clamscan            -0.09%         0.00%        179       78         1.3            |  0.21%       0.00%        493       49         0.3
sqlite3             -0.48%         0.00%        185       29         0.4            | -0.18%      -0.50%        514       91         0.6
tramp3d-v4           0.14%         0.00%        0         0          0.0            |  0.52%       0.00%        253       2          0.0
pairlocalalign      -0.04%         0.00%        0         0          0.0            |  0.49%       0.00%        54        48         2.7
7zip-benchmark       0.12%        -0.10%        336       273        2.5            |  0.75%      -0.40%        565       268        1.6
                                                                                    |
Average             -0.04%        -0.01%        118.30    45.7       0.87           |  0.40%      -0.09%        336       57         0.6
  • Compile time was measured using a single thread with 3 samples. Comparison is between geomeans of the samples.
  • # Missed combines is the total times that the combine failed
  • # Missed (>1 reg) is the number of times the combine failed with at least one register in RegsToVisit.

Is this meant to say *greater* than 1?

  • Avg regs/missed combine is the number of registers in RegsToVisit when the combine misses

Note that a lot of the time, the combine does miss with 0 registers (because you just don't find anything with a single use, for example).

Tue, Jan 12, 12:17 PM · Restricted Project
aemerson accepted D94437: [AArch64][GlobalISel] Add support for FCONSTANT of FP128 type.

LGTM with the getFPImm nit fixed.

Tue, Jan 12, 12:13 PM · Restricted Project

Sat, Jan 9

aemerson accepted D86226: GlobalISel: Do not set observer of MachineIRBuilder in LegalizerHelper.

LGTM. Having looked into this recently we should definitely from the MIRBuilder's observer.

Sat, Jan 9, 5:52 PM · Restricted Project

Fri, Jan 8

aemerson added a comment to D94350: [GlobalISel] Combine (a[0]) | (a[1] << k1) | ...| (a[m] << kn) into a wide load.

Thanks for tackling this. The logic seems sound to me, but I have some efficiency concerns. (Note, this is conjecture, I don't know if this is realistically a big problem)

Fri, Jan 8, 11:38 PM · Restricted Project

Thu, Jan 7

aemerson accepted D94204: GlobalISel: Handle G_BUILD_VECTOR in isKnownToBeAPowerOfTwo.
Thu, Jan 7, 4:58 PM · Restricted Project
aemerson added inline comments to D94204: GlobalISel: Handle G_BUILD_VECTOR in isKnownToBeAPowerOfTwo.
Thu, Jan 7, 3:30 PM · Restricted Project
aemerson requested review of D94264: [GlobalISel] Add MachineInstNumbering to CSEInfo and propagate CSE throughout AArch64 pipeline..
Thu, Jan 7, 1:52 PM · Restricted Project
aemerson accepted D94152: GlobalISel: Fail legalization on narrowing extload below memory size.
Thu, Jan 7, 1:50 PM · Restricted Project
aemerson added a comment to D94204: GlobalISel: Handle G_BUILD_VECTOR in isKnownToBeAPowerOfTwo.

Is this going to be used anywhere?

Thu, Jan 7, 1:49 PM · Restricted Project

Wed, Jan 6

aemerson committed rGa1265690cf61: Fix failing triple test for macOS 11 with non-zero minor versions. (authored by aemerson).
Fix failing triple test for macOS 11 with non-zero minor versions.
Wed, Jan 6, 2:58 PM
aemerson closed D94197: Fix failing triple test for macOS 11 with non-zero minor versions..
Wed, Jan 6, 2:58 PM · Restricted Project
aemerson requested review of D94197: Fix failing triple test for macOS 11 with non-zero minor versions..
Wed, Jan 6, 2:42 PM · Restricted Project

Mon, Dec 28

aemerson added a comment to D93853: [CodeGen] recognize select form of and/ors when splitting branch conditions.

We do this condition splitting optimization in GlobalISel too, so that will also need fixing: see IRTranslator.cpp.

Mon, Dec 28, 10:29 PM · Restricted Project

Sun, Dec 27

aemerson committed rG7df3544e80fb: [GlobalISel] Fix assertion failures after "GlobalISel: Return APInt from… (authored by aemerson).
[GlobalISel] Fix assertion failures after "GlobalISel: Return APInt from…
Sun, Dec 27, 12:16 AM

Fri, Dec 25

aemerson committed rGe0721a099228: [AArch64][GlobalISel] Notify observer of mutated instruction for shift custom… (authored by aemerson).
[AArch64][GlobalISel] Notify observer of mutated instruction for shift custom…
Fri, Dec 25, 12:34 AM

Dec 17 2020

aemerson added a comment to D93136: [test-suite] ClamAV CMake fix..

This seems to have caused failures on Darwin platforms. I've pushed a fix in 48e7b34f but let me know if you disagree with the approach.

Dec 17 2020, 3:19 PM

Dec 16 2020

aemerson added a comment to D93423: [GlobalISel] Use slot indexes to speed up huge block compile time.

If slot indexes are preserved and used in other passes that use CSE, do you think the compile time impact is amortized/minimized?

It's possible it would help a bit. I think the localizer may also benefit from this. I don't see it making a big difference either way though in most code.

In our out of tree backend, CSE is used and preserved for 6 passes in total. I suspect if slot indexes are also preserved, the overhead might not be too much. Hence I was curious if you actually collected some numbers. If only legalizer is being looked at for compile time impact, we're not really evaluating the compile time savings to be had in other passes (assuming amortized cost of slot index) right?

Dec 16 2020, 4:11 PM · Restricted Project
aemerson added a comment to D93423: [GlobalISel] Use slot indexes to speed up huge block compile time.

If slot indexes are preserved and used in other passes that use CSE, do you think the compile time impact is amortized/minimized?

Dec 16 2020, 3:44 PM · Restricted Project
aemerson added a comment to D93423: [GlobalISel] Use slot indexes to speed up huge block compile time.

I still think the CSE MIR builder shouldn't be required to CSE and can bail early on long dominance queries

I guess the concern is how exactly one defines "early" and "long". Should it be universal? Opt in? Configurable ?.. What if it bailed just a few instructions away from the target instruction. What about the compile time impact of counting and checking in loop in the cases where you don't need and so on.

Dec 16 2020, 3:42 PM · Restricted Project
aemerson added a comment to D93423: [GlobalISel] Use slot indexes to speed up huge block compile time.

I still think the CSE MIR builder shouldn't be required to CSE and can bail early on long dominance queries

Dec 16 2020, 3:35 PM · Restricted Project
aemerson added inline comments to D93239: GlobalISel: Return APInt from getConstantVRegVal.
Dec 16 2020, 3:29 PM · Restricted Project
aemerson requested review of D93423: [GlobalISel] Use slot indexes to speed up huge block compile time.
Dec 16 2020, 3:18 PM · Restricted Project

Dec 15 2020

aemerson accepted D93310: GlobalISel: Fix generic handling of single outgoing call arguments.
Dec 15 2020, 11:24 AM · Restricted Project

Dec 14 2020

aemerson committed rGa69b76c50084: [GlobalISel][IRTranslator] Ensure branch probabilities are added when… (authored by aemerson).
[GlobalISel][IRTranslator] Ensure branch probabilities are added when…
Dec 14 2020, 11:37 PM
aemerson closed D93256: [GlobalISel][IRTranslator] Ensure branch probabilities are added when translating invoke edges..
Dec 14 2020, 11:37 PM · Restricted Project
aemerson added a comment to D93154: GlobalISel: remove assert that memcpy Src and Dst addrspace must be identical.

Yes, a test would be good.

Dec 14 2020, 3:33 PM · Restricted Project
aemerson requested review of D93256: [GlobalISel][IRTranslator] Ensure branch probabilities are added when translating invoke edges..
Dec 14 2020, 3:32 PM · Restricted Project

Dec 12 2020

aemerson committed rG21de99d43c88: [[GlobalISel][IRTranslator] Fix a crash when the use of an extractvalue is a… (authored by aemerson).
[[GlobalISel][IRTranslator] Fix a crash when the use of an extractvalue is a…
Dec 12 2020, 3:11 PM

Dec 10 2020

aemerson committed rGc29af37c6c9d: [AArch64] Don't try to compress jump tables if there are any inline asm… (authored by aemerson).
[AArch64] Don't try to compress jump tables if there are any inline asm…
Dec 10 2020, 12:20 PM
aemerson closed D92865: [AArch64] Don't try to compress jump tables if there are any inline asm instructions..
Dec 10 2020, 12:20 PM · Restricted Project

Dec 8 2020

aemerson accepted D92868: [AArch64][GlobalISel] Fold G_SELECT cc, %t, (G_ADD %x, 1) -> CSINC %t, %x, cc.
Dec 8 2020, 10:40 AM · Restricted Project
aemerson accepted D92860: [AArch64][GlobalISel] Fold binops on the true side of G_SELECT.

LGTM.

Dec 8 2020, 10:38 AM · Restricted Project
aemerson requested review of D92865: [AArch64] Don't try to compress jump tables if there are any inline asm instructions..
Dec 8 2020, 10:17 AM · Restricted Project

Dec 7 2020

aemerson committed rG2ac4d0f45a2a: [AArch64] Fix some minor coding style issues in AArch64CompressJumpTables (authored by aemerson).
[AArch64] Fix some minor coding style issues in AArch64CompressJumpTables
Dec 7 2020, 12:48 PM
aemerson accepted D92707: [AArch64][GlobalISel] Narrow 128-bit regs to 64-bit regs in emitTestBit.
Dec 7 2020, 11:21 AM · Restricted Project

Dec 4 2020

aemerson added a comment to D92707: [AArch64][GlobalISel] Narrow 128-bit regs to 64-bit regs in emitTestBit.

Can you also check if there's any code size impact at -O0 and -Os. I'm wary of regressing -O0 and leaving extra unnecessary moves around.

Dec 4 2020, 11:58 PM · Restricted Project
aemerson added inline comments to D92707: [AArch64][GlobalISel] Narrow 128-bit regs to 64-bit regs in emitTestBit.
Dec 4 2020, 11:46 PM · Restricted Project
aemerson added a comment to D92569: [AArch64] Lower calls with rv_marker attribute ..

As discussed offline, this also needs an implementation for GlobalISel. You can just add check lines to the test with -global-isel -global-isel-abort=1 for the tests.

Dec 4 2020, 9:47 PM · Restricted Project

Dec 3 2020

aemerson accepted D92610: [AArch64][GlobalISel] Select G_SADDO and G_SSUBO.

LGTM.

Dec 3 2020, 9:07 PM · Restricted Project
aemerson accepted D92582: [AArch64][GlobalISel] Refactor G_BRCOND selection.
Dec 3 2020, 8:50 PM · Restricted Project

Dec 2 2020

aemerson accepted D92438: [AArch64][GlobalISel] Don't explicitly write to the zero register in emitCMN.
Dec 2 2020, 10:27 AM · Restricted Project

Dec 1 2020

aemerson accepted D92358: [AArch64][GlobalISel] Select Bcc when it's better than TB(N)Z.
Dec 1 2020, 2:44 PM · Restricted Project
aemerson added inline comments to D92358: [AArch64][GlobalISel] Select Bcc when it's better than TB(N)Z.
Dec 1 2020, 12:25 AM · Restricted Project

Nov 30 2020

aemerson committed rG87ff15641437: [AArch64][GlobalISel] Fix crash during legalization of a vector G_SELECT with… (authored by aemerson).
[AArch64][GlobalISel] Fix crash during legalization of a vector G_SELECT with…
Nov 30 2020, 4:38 PM
aemerson closed D91655: [AArch64][GlobalISel] Fix crash during legalization of a vector G_SELECT with scalar mask..
Nov 30 2020, 4:38 PM · Restricted Project

Nov 23 2020

aemerson committed rGca7fdf7ce098: [AArch64][GlobalISel] Add pre-isel lowering to convert p0 G_DUPs to use s64. (authored by aemerson).
[AArch64][GlobalISel] Add pre-isel lowering to convert p0 G_DUPs to use s64.
Nov 23 2020, 11:21 PM
aemerson committed rG0fb76b9035c8: [AArch64][GlobalISel] Make <2 x p0> of G_SHUFFLE_VECTOR legal. (authored by aemerson).
[AArch64][GlobalISel] Make <2 x p0> of G_SHUFFLE_VECTOR legal.
Nov 23 2020, 11:21 PM
aemerson added a comment to D91655: [AArch64][GlobalISel] Fix crash during legalization of a vector G_SELECT with scalar mask..

ping

Nov 23 2020, 10:45 PM · Restricted Project

Nov 20 2020

aemerson committed rGc58df88886e4: [AArch64][GlobalISel] Make G_EXTRACT_VECTOR_ELT of <2 x p0> legal. (authored by aemerson).
[AArch64][GlobalISel] Make G_EXTRACT_VECTOR_ELT of <2 x p0> legal.
Nov 20 2020, 2:08 PM
aemerson requested review of D91892: [GlobalISel] Add NamedRegionTimers for all GlobalISel passes in AArch64 pipeline..
Nov 20 2020, 1:19 PM · Restricted Project
aemerson added inline comments to D91753: [GlobalISel] Add an isExtendedTrueVal helper..
Nov 20 2020, 12:05 PM · Restricted Project

Nov 19 2020

aemerson added a reviewer for D90305: Correctly parse and print Tag_THUMB_ISA_use=3: simon_tatham.

@simon_tatham Can you take a look?

Nov 19 2020, 10:22 AM · Restricted Project

Nov 18 2020

aemerson added inline comments to D91753: [GlobalISel] Add an isExtendedTrueVal helper..
Nov 18 2020, 11:17 PM · Restricted Project
aemerson accepted D91754: [GlobalISel] Add isConstFalseVal helper to Utils.
Nov 18 2020, 11:15 PM · Restricted Project
aemerson added inline comments to D91755: [GlobalISel] Combine icmp eq/ne (ext (icmp cc, x, y)), true/false).
Nov 18 2020, 11:15 PM · Restricted Project

Nov 17 2020

aemerson updated the diff for D91655: [AArch64][GlobalISel] Fix crash during legalization of a vector G_SELECT with scalar mask..

Add buildShuffleSplat and buildShuffleVector to MachineIRBuilder and use.

Nov 17 2020, 1:03 PM · Restricted Project
aemerson added inline comments to D91655: [AArch64][GlobalISel] Fix crash during legalization of a vector G_SELECT with scalar mask..
Nov 17 2020, 12:22 PM · Restricted Project
aemerson requested review of D91655: [AArch64][GlobalISel] Fix crash during legalization of a vector G_SELECT with scalar mask..
Nov 17 2020, 12:16 PM · Restricted Project

Nov 16 2020

aemerson committed rG0b6090699ab5: [AArch64][GlobalISel] Look through a G_ZEXT when trying to match shift-extended… (authored by aemerson).
[AArch64][GlobalISel] Look through a G_ZEXT when trying to match shift-extended…
Nov 16 2020, 10:53 AM
aemerson closed D91475: [AArch64][GlobalISel] Look through a G_ZEXT when trying to match shift-extended register offsets..
Nov 16 2020, 10:52 AM · Restricted Project

Nov 13 2020

aemerson requested review of D91475: [AArch64][GlobalISel] Look through a G_ZEXT when trying to match shift-extended register offsets..
Nov 13 2020, 11:14 PM · Restricted Project
aemerson accepted D90774: [AArch64][GlobalISel] Fold G_XOR x, -1 into G_SELECT and select CSINV.
Nov 13 2020, 10:38 PM · Restricted Project
aemerson requested review of D91439: GlobalISel: WIP: allow excluding of combine rules or groups.
Nov 13 2020, 9:09 AM · Restricted Project
aemerson accepted D90723: [AArch64][GlobalISel] Select G_SELECT cc, t, (G_SUB 0, x) -> CSNEG t, x, cc.

LGTM once we use the new matcher.

Nov 13 2020, 9:06 AM · Restricted Project
aemerson added inline comments to D90723: [AArch64][GlobalISel] Select G_SELECT cc, t, (G_SUB 0, x) -> CSNEG t, x, cc.
Nov 13 2020, 9:05 AM · Restricted Project
aemerson accepted D91397: [GlobalISel] Add matchers for specific constants and a matcher for negations.

LGTM.

Nov 13 2020, 9:05 AM · Restricted Project

Nov 12 2020

aemerson added a comment to D90774: [AArch64][GlobalISel] Fold G_XOR x, -1 into G_SELECT and select CSINV.

Maybe use PatternMatch for this too?

Nov 12 2020, 10:10 AM · Restricted Project
aemerson added inline comments to D90723: [AArch64][GlobalISel] Select G_SELECT cc, t, (G_SUB 0, x) -> CSNEG t, x, cc.
Nov 12 2020, 10:08 AM · Restricted Project
aemerson accepted D90701: [AArch64][GlobalISel] Select CSINC and CSINV for G_SELECT with constants.

LGTM with nit.

Nov 12 2020, 9:48 AM · Restricted Project
aemerson accepted D91288: [AArch64][GlobalISel] NFC: Use CmpInst::isUnsigned instead of static helper.
Nov 12 2020, 9:45 AM · Restricted Project

Nov 11 2020

aemerson committed rGad376657c1ec: [AArch64][GlobalISel] Optimize G_PTR_ADD with a negated offset to be a G_SUB. (authored by aemerson).
[AArch64][GlobalISel] Optimize G_PTR_ADD with a negated offset to be a G_SUB.
Nov 11 2020, 10:47 PM

Nov 10 2020

aemerson accepted D91207: [AArch64][GlobalISel] Select arith extended add/sub in manual selection code.
Nov 10 2020, 10:26 PM · Restricted Project
aemerson accepted D91108: [AArch64][GlobalISel] Select negative arithmetic immediates in manual selector.
Nov 10 2020, 10:24 PM · Restricted Project
aemerson committed rG22623930903d: [AArch64][GlobalISel] Port some AArch64 target specific MUL combines from SDAG. (authored by aemerson).
[AArch64][GlobalISel] Port some AArch64 target specific MUL combines from SDAG.
Nov 10 2020, 10:21 PM
aemerson closed D91125: [AArch64][GlobalISel] Port some AArch64 target specific MUL combines from SDAG..
Nov 10 2020, 10:21 PM · Restricted Project
aemerson added inline comments to D91125: [AArch64][GlobalISel] Port some AArch64 target specific MUL combines from SDAG..
Nov 10 2020, 2:42 PM · Restricted Project
aemerson updated the diff for D91125: [AArch64][GlobalISel] Port some AArch64 target specific MUL combines from SDAG..

Check for SEXT_INREG and use copy instead of modifying operand reg.

Nov 10 2020, 11:16 AM · Restricted Project
aemerson added inline comments to D91125: [AArch64][GlobalISel] Port some AArch64 target specific MUL combines from SDAG..
Nov 10 2020, 11:06 AM · Restricted Project

Nov 9 2020

aemerson requested review of D91125: [AArch64][GlobalISel] Port some AArch64 target specific MUL combines from SDAG..
Nov 9 2020, 10:01 PM · Restricted Project