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[AMDGPU] Implement CFI for non-kernel functions
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Authored by scott.linder on Mar 26 2020, 12:21 PM.

Details

Summary

This does not implement CSR spills other than those AMDGPU handles
during PEI. The remaining spills are handled in a subsequent patch.

Diff Detail

Unit TestsFailed

TimeTest
1,310 mswindows > LLVM.CodeGen/AMDGPU::wave32.ll
Script: -- : 'RUN: at line 1'; c:\ws\w1\llvm-project\premerge-checks\build\bin\llc.exe -march=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -verify-machineinstrs < C:\ws\w1\llvm-project\premerge-checks\llvm\test\CodeGen\AMDGPU\wave32.ll | c:\ws\w1\llvm-project\premerge-checks\build\bin\filecheck.exe -check-prefixes=GCN,GFX1032 C:\ws\w1\llvm-project\premerge-checks\llvm\test\CodeGen\AMDGPU\wave32.ll

Event Timeline

scott.linder created this revision.Mar 26 2020, 12:21 PM

git clang-format

arsenm added inline comments.Mar 26 2020, 1:42 PM
llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
677

Register

690

Double cast

703

MCPhysReg?

1067

Register

llvm/lib/Target/AMDGPU/SIFrameLowering.h
88

s/unsigned/Register

Rebase and address feedback.

scott.linder edited the summary of this revision. (Show Details)
scott.linder added a reviewer: cdevadas.
scott.linder added a subscriber: cdevadas.

Rebase, generalize the previously hard-coded list of caller-saved registers
with help from @cdevadas, and emit CFI for the new case where we spill the FP
to VMEM.

cdevadas added inline comments.May 13 2020, 6:28 AM
llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
30

I think it is good to move getAllSGPRs and getAllVGPRs into SIRegisterInfo.cpp.
There is another function getAllVGPR32 which does the same thing as getAllVGPRs.
We can unify these instances.

scott.linder marked an inline comment as done.
cdevadas added inline comments.May 14 2020, 9:06 AM
llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
1501

Can you write a small description of why the FIXME?

Rebase and emit CFI for Base pointer

Rebase onto LLVM master