User Details
- User Since
- Apr 29 2019, 11:13 PM (89 w, 6 d)
Thu, Jan 7
Added two more tests to address the review comment.
Wed, Jan 6
LGTM
Tue, Jan 5
Mon, Jan 4
Ping
Ping
Dec 17 2020
Ping
Dec 15 2020
Dec 13 2020
ping
Dec 9 2020
Not sure I can have one at this point.
There is a follow-up patch I am making to enable it for AMDGPU. I will have some tests along with that.
Dec 3 2020
@qcolombet can you review this patch?
Nov 20 2020
Ping
Nov 13 2020
rebase + elaborated the comment in Target.td
Nov 6 2020
Ping
Nov 2 2020
Added testcases.
Nov 1 2020
Oct 30 2020
Addressed the suggestion by @foad to include the Dereferenceable check on MMO.
Made the alignment check to 8-byte boundary instead of 16-byte.
Oct 29 2020
Used -DAG to fix the test.
Oct 25 2020
Oct 23 2020
Ping
Oct 19 2020
Used the FI directly in MI if available during ISel. Fixed an unhandled case during eliminateFrameIndex.
Also fixed the assertions to make sure the soffset field is relevant.
Oct 16 2020
Oct 13 2020
At global-isel, it has already been taken care of.
The asserts - the cases where it is expecting a register is specifically for sp relative accesses and won't cause a problem after this patch.
Oct 12 2020
Oct 11 2020
Oct 7 2020
rebase + ping
Sep 7 2020
Ping @stoklund @MatzeB or anyone interested in this patch.
Appreciate it if this gets reviewed soon.
Sep 3 2020
Ping
Sep 1 2020
Aug 31 2020
Addressed the review comments.
Aug 29 2020
Jul 30 2020
Can we have this patch reviewed soon?
Appreciate any response.
Jul 20 2020
It has been merged with https://reviews.llvm.org/rG207cd5f68fabbf760c7e66dc6c49e833f3f6f953.
Jul 11 2020
Expanded the comment.
Jul 10 2020
Incorporated the suggestions.
Jun 29 2020
Jun 26 2020
We are trying to have the kill intrinsic handling early during the instruction selection.
I can try to incorporate it all entirely there including the unify block code (if can't find a better place now to have it).
I will also update D77544 if this patch goes upstream.
Ping
Jun 18 2020
Rebase + added lit test
Jun 2 2020
LGTM
May 17 2020
May 14 2020
May 13 2020
May 12 2020
May 11 2020
Ping
May 8 2020
May 7 2020
May 5 2020
May 4 2020
Rebase + Suggestions.
May 3 2020
Fixed the testcase.
May 1 2020
Ping
Incorporated the suggestions.
Apr 30 2020
Apr 29 2020
Divided the VGPRs into equal number of CSRs and scratch registers. Also, added a test case for VGPR tuple allocation.
Apr 26 2020
Incorporated the suggestions.
Apr 24 2020
Apr 23 2020
Added a small description of the test.
Apr 22 2020
Apr 6 2020
Mar 26 2020
A cost for VGPR registers has been handled with https://reviews.llvm.org/D76417. This will ensure a balanced allocation of scratch registers & CSRs at every split (once the current patch is in the upstream).
Mar 25 2020
Mar 24 2020
Thank you all for the comments.
I can see that there are concerns with the current split boundary (4 VGPRs together), considering the fact that we have wide VGPR uses in certain scenarios (image instructions).
But, like Matt mentioned, how frequently such scenarios occur?
Changing the split boundary to a large value would probably take away the whole purpose of this patch - reduce the CSR spills & try to ensure a better occupancy.
Abandoning this review.
This optimization should be handled late after Basic Block Placement. A new review will be opened by handling it in a late pass.
Mar 21 2020
Mar 20 2020
Added a brief description of the register split (AMDGPUUsage.rst).
rebase
Mar 19 2020
Mar 18 2020
Reverted the changes made on the CostPerUse value.
It will go in a follow-up commit after this review.
Mar 11 2020
incorporated the suggestion.