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cdevadas (Christudasan Devadasan)
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User Since
Apr 29 2019, 11:13 PM (73 w, 6 d)

Recent Activity

Mon, Sep 7

cdevadas added a comment to D86836: Support a list of CostPerUse values.

Ping @stoklund @MatzeB or anyone interested in this patch.
Appreciate it if this gets reviewed soon.

Mon, Sep 7, 11:57 PM · Restricted Project

Thu, Sep 3

cdevadas added a comment to D86836: Support a list of CostPerUse values.

Ping

Thu, Sep 3, 2:25 AM · Restricted Project

Tue, Sep 1

cdevadas added a reviewer for D86836: Support a list of CostPerUse values: MatzeB.
Tue, Sep 1, 8:04 AM · Restricted Project

Mon, Aug 31

cdevadas updated the diff for D86836: Support a list of CostPerUse values.

Addressed the review comments.

Mon, Aug 31, 3:15 AM · Restricted Project
cdevadas added inline comments to D86836: Support a list of CostPerUse values.
Mon, Aug 31, 3:12 AM · Restricted Project

Sat, Aug 29

cdevadas requested review of D86836: Support a list of CostPerUse values.
Sat, Aug 29, 5:23 AM · Restricted Project

Jul 30 2020

cdevadas added a comment to D20758: Support addrspacecast initializers with isNoopAddrSpaceCast.

Can we have this patch reviewed soon?
Appreciate any response.

Jul 30 2020, 8:06 PM · Restricted Project

Jul 20 2020

cdevadas closed D78664: [AMDGPU] Add the SGPR used for FP copy to block livein lists..

It has been merged with https://reviews.llvm.org/rG207cd5f68fabbf760c7e66dc6c49e833f3f6f953.

Jul 20 2020, 8:40 AM · Restricted Project

Jul 11 2020

cdevadas committed rGd7a05698efcf: [AMDGPU] Move LowerSwitch pass to CodeGenPrepare. (authored by cdevadas).
[AMDGPU] Move LowerSwitch pass to CodeGenPrepare.
Jul 11 2020, 4:22 AM
cdevadas closed D83584: [AMDGPU] Move LowerSwitch pass to CodeGenPrepare..
Jul 11 2020, 4:22 AM · Restricted Project
cdevadas updated the diff for D83584: [AMDGPU] Move LowerSwitch pass to CodeGenPrepare..

Expanded the comment.

Jul 11 2020, 3:25 AM · Restricted Project

Jul 10 2020

cdevadas updated the diff for D83584: [AMDGPU] Move LowerSwitch pass to CodeGenPrepare..

Incorporated the suggestions.

Jul 10 2020, 7:10 PM · Restricted Project
Herald added a project to D83584: [AMDGPU] Move LowerSwitch pass to CodeGenPrepare.: Restricted Project.
Jul 10 2020, 12:35 PM · Restricted Project

Jun 29 2020

cdevadas committed rG226cda58d505: [AMDGPU] Moving SI_RETURN_TO_EPILOG handling out of SIInsertSkips. (authored by cdevadas).
[AMDGPU] Moving SI_RETURN_TO_EPILOG handling out of SIInsertSkips.
Jun 29 2020, 8:37 AM
cdevadas closed D77544: [AMDGPU] Moving SI_RETURN_TO_EPILOG handling out of SIInsertSkips..
Jun 29 2020, 8:37 AM · Restricted Project

Jun 26 2020

cdevadas added a comment to D82641: [AMDGPU] Unify early PS termination blocks.

We are trying to have the kill intrinsic handling early during the instruction selection.
I can try to incorporate it all entirely there including the unify block code (if can't find a better place now to have it).
I will also update D77544 if this patch goes upstream.

Jun 26 2020, 8:22 PM · Restricted Project
cdevadas added a comment to D77544: [AMDGPU] Moving SI_RETURN_TO_EPILOG handling out of SIInsertSkips..

Ping

Jun 26 2020, 3:13 AM · Restricted Project

Jun 18 2020

cdevadas updated the diff for D77544: [AMDGPU] Moving SI_RETURN_TO_EPILOG handling out of SIInsertSkips..

Rebase + added lit test

Jun 18 2020, 3:14 AM · Restricted Project

Jun 2 2020

cdevadas accepted D80931: AMDGPU: Fix clang side null pointer value for private.

LGTM

Jun 2 2020, 3:52 AM

May 17 2020

cdevadas committed rG7c4e711ef8d8: [AMDGPU] Enable base pointer. (authored by cdevadas).
[AMDGPU] Enable base pointer.
May 17 2020, 4:47 AM
cdevadas closed D78811: [AMDGPU] Enable base pointer..
May 17 2020, 4:47 AM · Restricted Project

May 14 2020

cdevadas added inline comments to D76882: [AMDGPU] Implement CFI for non-kernel functions.
May 14 2020, 9:11 AM · debug-info, Restricted Project

May 13 2020

cdevadas added inline comments to D76882: [AMDGPU] Implement CFI for non-kernel functions.
May 13 2020, 6:59 AM · debug-info, Restricted Project

May 12 2020

cdevadas added inline comments to D78811: [AMDGPU] Enable base pointer..
May 12 2020, 9:07 AM · Restricted Project

May 11 2020

cdevadas added a comment to D78811: [AMDGPU] Enable base pointer..

Ping

May 11 2020, 12:24 PM · Restricted Project

May 8 2020

cdevadas added inline comments to D78811: [AMDGPU] Enable base pointer..
May 8 2020, 1:25 PM · Restricted Project

May 7 2020

cdevadas added inline comments to D70379: [AMDGPU] Reserving VGPR for future SGPR Spill.
May 7 2020, 9:40 AM · Restricted Project, Restricted Project

May 5 2020

cdevadas committed rGb8a616ec59f8: [AMDGPU] Fixed the test by adding the triple. (authored by cdevadas).
[AMDGPU] Fixed the test by adding the triple.
May 5 2020, 11:53 AM
cdevadas committed rG375cec4b6c85: [AMDGPU] Introduce more scratch registers in the ABI. (authored by cdevadas).
[AMDGPU] Introduce more scratch registers in the ABI.
May 5 2020, 10:47 AM
cdevadas closed D76356: [AMDGPU] Introduce more scratch registers in the ABI..
May 5 2020, 10:47 AM · Restricted Project

May 4 2020

cdevadas updated the diff for D78811: [AMDGPU] Enable base pointer..

Rebase + Suggestions.

May 4 2020, 11:15 AM · Restricted Project

May 3 2020

cdevadas updated the diff for D76356: [AMDGPU] Introduce more scratch registers in the ABI..

Fixed the testcase.

May 3 2020, 10:37 AM · Restricted Project

May 1 2020

cdevadas added a comment to D76356: [AMDGPU] Introduce more scratch registers in the ABI..

Ping

May 1 2020, 5:09 PM · Restricted Project
cdevadas updated the diff for D78811: [AMDGPU] Enable base pointer..

Incorporated the suggestions.

May 1 2020, 5:09 PM · Restricted Project

Apr 30 2020

cdevadas added inline comments to D78811: [AMDGPU] Enable base pointer..
Apr 30 2020, 2:25 AM · Restricted Project

Apr 29 2020

cdevadas updated the diff for D76356: [AMDGPU] Introduce more scratch registers in the ABI..

Divided the VGPRs into equal number of CSRs and scratch registers. Also, added a test case for VGPR tuple allocation.

Apr 29 2020, 3:39 PM · Restricted Project

Apr 26 2020

cdevadas updated the diff for D78811: [AMDGPU] Enable base pointer..

Incorporated the suggestions.

Apr 26 2020, 11:09 AM · Restricted Project
cdevadas added inline comments to D78811: [AMDGPU] Enable base pointer..
Apr 26 2020, 10:37 AM · Restricted Project

Apr 24 2020

cdevadas created D78811: [AMDGPU] Enable base pointer..
Apr 24 2020, 9:09 AM · Restricted Project

Apr 23 2020

cdevadas committed rG207cd5f68fab: [AMDGPU] Add the SGPR used for FP copy to block livein lists. (authored by cdevadas).
[AMDGPU] Add the SGPR used for FP copy to block livein lists.
Apr 23 2020, 11:57 PM
cdevadas updated the diff for D78664: [AMDGPU] Add the SGPR used for FP copy to block livein lists..

Added a small description of the test.

Apr 23 2020, 1:02 AM · Restricted Project

Apr 22 2020

cdevadas created D78664: [AMDGPU] Add the SGPR used for FP copy to block livein lists..
Apr 22 2020, 1:03 PM · Restricted Project

Apr 6 2020

cdevadas created D77544: [AMDGPU] Moving SI_RETURN_TO_EPILOG handling out of SIInsertSkips..
Apr 6 2020, 5:55 AM · Restricted Project

Mar 26 2020

cdevadas added a comment to D76356: [AMDGPU] Introduce more scratch registers in the ABI..

Thank you all for the comments.
I can see that there are concerns with the current split boundary (4 VGPRs together), considering the fact that we have wide VGPR uses in certain scenarios (image instructions).
But, like Matt mentioned, how frequently such scenarios occur?
Changing the split boundary to a large value would probably take away the whole purpose of this patch - reduce the CSR spills & try to ensure a better occupancy.

What will happen if you need to pass VReg_1024 into a function? It might not be a common case, but will it even work?

It works, but that isn't changed by this patch. This is not changing the argument registers which are all still in v0-v31. I believe the largest argument type we pass in registers is <8 x i32>, and force <32 x i32> to be stack passed anyway

OK. What if such a register needs to be preserved by a caller? I guess there is no safe window for it, so it will be forced to spill. Then we will spill a whole huge register, not just a part of it, because we do not use sublane spilling (except to AGPRs), right?

Yes, that's what I would expect

Then probably interleave 4 is not a best choice. We may also need to adjust cost of tuples to make aligned allocation more likely.

A cost for VGPR registers has been handled with https://reviews.llvm.org/D76417. This will ensure a balanced allocation of scratch registers & CSRs at every split (once the current patch is in the upstream).

Mar 26 2020, 9:45 AM · Restricted Project

Mar 25 2020

cdevadas committed rGce984129eaa5: [AMDGPU] Add SIPreEmitPeephole pass. (authored by cdevadas).
[AMDGPU] Add SIPreEmitPeephole pass.
Mar 25 2020, 8:38 AM
cdevadas closed D76712: [AMDGPU] Add SIPreEmitPeephole pass..
Mar 25 2020, 8:38 AM · Restricted Project

Mar 24 2020

cdevadas added a comment to D76356: [AMDGPU] Introduce more scratch registers in the ABI..

Thank you all for the comments.
I can see that there are concerns with the current split boundary (4 VGPRs together), considering the fact that we have wide VGPR uses in certain scenarios (image instructions).
But, like Matt mentioned, how frequently such scenarios occur?
Changing the split boundary to a large value would probably take away the whole purpose of this patch - reduce the CSR spills & try to ensure a better occupancy.

Mar 24 2020, 10:11 AM · Restricted Project
cdevadas created D76712: [AMDGPU] Add SIPreEmitPeephole pass..
Mar 24 2020, 9:39 AM · Restricted Project
cdevadas abandoned D75504: [AMDGPU] moving vcc branch optimization into peephole.

Abandoning this review.
This optimization should be handled late after Basic Block Placement. A new review will be opened by handling it in a late pass.

Mar 24 2020, 9:39 AM · Restricted Project

Mar 21 2020

cdevadas added inline comments to D76356: [AMDGPU] Introduce more scratch registers in the ABI..
Mar 21 2020, 10:40 AM · Restricted Project
cdevadas added inline comments to D76356: [AMDGPU] Introduce more scratch registers in the ABI..
Mar 21 2020, 8:01 AM · Restricted Project

Mar 20 2020

cdevadas updated the diff for D76356: [AMDGPU] Introduce more scratch registers in the ABI..

Added a brief description of the register split (AMDGPUUsage.rst).

Mar 20 2020, 1:34 PM · Restricted Project
cdevadas added inline comments to D75504: [AMDGPU] moving vcc branch optimization into peephole.
Mar 20 2020, 4:18 AM · Restricted Project
cdevadas updated the diff for D76356: [AMDGPU] Introduce more scratch registers in the ABI..

rebase

Mar 20 2020, 3:13 AM · Restricted Project

Mar 19 2020

cdevadas committed rG728b878de689: [AMDGPU] Set the CostPerUse value for vgpr registers. (authored by cdevadas).
[AMDGPU] Set the CostPerUse value for vgpr registers.
Mar 19 2020, 11:25 PM
cdevadas closed D76417: [AMDGPU] Set a cost model for vgpr registers..
Mar 19 2020, 11:25 PM · Restricted Project
cdevadas created D76417: [AMDGPU] Set a cost model for vgpr registers..
Mar 19 2020, 12:30 AM · Restricted Project

Mar 18 2020

cdevadas updated the diff for D76356: [AMDGPU] Introduce more scratch registers in the ABI..

Reverted the changes made on the CostPerUse value.
It will go in a follow-up commit after this review.

Mar 18 2020, 11:57 AM · Restricted Project
cdevadas added inline comments to D76356: [AMDGPU] Introduce more scratch registers in the ABI..
Mar 18 2020, 8:41 AM · Restricted Project
cdevadas created D76356: [AMDGPU] Introduce more scratch registers in the ABI..
Mar 18 2020, 6:30 AM · Restricted Project

Mar 11 2020

cdevadas updated the diff for D75504: [AMDGPU] moving vcc branch optimization into peephole.

incorporated the suggestion.

Mar 11 2020, 10:45 AM · Restricted Project

Mar 7 2020

cdevadas added inline comments to D75504: [AMDGPU] moving vcc branch optimization into peephole.
Mar 7 2020, 9:08 AM · Restricted Project

Mar 3 2020

cdevadas added inline comments to D75504: [AMDGPU] moving vcc branch optimization into peephole.
Mar 3 2020, 7:37 PM · Restricted Project
cdevadas created D75504: [AMDGPU] moving vcc branch optimization into peephole.
Mar 3 2020, 12:23 AM · Restricted Project

Feb 27 2020

cdevadas committed rG8f4d67792368: Enable spilling exec mask and return address regsiter for effective CFI… (authored by cdevadas).
Enable spilling exec mask and return address regsiter for effective CFI…
Feb 27 2020, 9:05 AM

Feb 2 2020

cdevadas added a comment to D73771: [AMDGPU] Don't remove short branches over kills.

I am moving the kill intrinsic handling into a separate pass. It is partially done. Fixing some corner cases now.
SIInsertSkips will eventually go away.
The handling/optimizaton of cbranch_execz insertion has been moved to the new pass SIRemoveShortExecBranches.

Feb 2 2020, 8:44 AM · Restricted Project

Jan 26 2020

cdevadas committed rG66f93071cdfc: AMDGPU/GlobalISel: Clean-up code around ISel for Intrinsics. (authored by mshivama).
AMDGPU/GlobalISel: Clean-up code around ISel for Intrinsics.
Jan 26 2020, 12:48 AM
cdevadas closed D73358: AMDGPU/GlobalISel: Clean-up code around ISel for Intrinsics..
Jan 26 2020, 12:48 AM · Restricted Project

Jan 25 2020

cdevadas added inline comments to D73396: AMDGPU/GlobalISel: Select G_SEXT_INREG.
Jan 25 2020, 10:44 PM · Restricted Project

Jan 20 2020

cdevadas added a comment to D72997: [AMDGPU] SIRemoveShortExecBranches should not remove branches exiting loops.

You are right, the s_cbranch_execz shouldn't be removed from this loop exit BB.

Jan 20 2020, 4:07 AM · Restricted Project

Jan 15 2020

cdevadas committed rG0dc6c249bffa: [AMDGPU] Invert the handling of skip insertion. (authored by cdevadas).
[AMDGPU] Invert the handling of skip insertion.
Jan 15 2020, 2:01 AM
cdevadas closed D68092: [AMDGPU] Invert the handling of skip insertion..
Jan 15 2020, 2:00 AM · Restricted Project

Nov 19 2019

cdevadas updated the diff for D68092: [AMDGPU] Invert the handling of skip insertion..

incorporated the suggestion (used getBlockDestinations for the function name)

Nov 19 2019, 9:44 PM · Restricted Project
cdevadas added inline comments to D68092: [AMDGPU] Invert the handling of skip insertion..
Nov 19 2019, 5:03 AM · Restricted Project

Nov 15 2019

cdevadas updated the diff for D68092: [AMDGPU] Invert the handling of skip insertion..

Created a wrapper to get the true & false branch targets. Also, used BB numbering to identify the forward jumps.

Nov 15 2019, 1:06 AM · Restricted Project

Nov 12 2019

cdevadas updated the diff for D68092: [AMDGPU] Invert the handling of skip insertion..

Checked the return value of analyzeBranch.
Considered only the forward branches to avoid back-edges from this optimization.

Nov 12 2019, 5:26 AM · Restricted Project

Oct 26 2019

cdevadas committed rGe921ede54068: [AMDGPU] Fix Vreg_1 PHI lowering in SILowerI1Copies. (authored by cdevadas).
[AMDGPU] Fix Vreg_1 PHI lowering in SILowerI1Copies.
Oct 26 2019, 2:19 AM
cdevadas closed D69182: [AMDGPU] Fix Vreg_1 PHI lowering in SILowerI1Copies..
Oct 26 2019, 2:18 AM · Restricted Project

Oct 25 2019

cdevadas added a comment to D69182: [AMDGPU] Fix Vreg_1 PHI lowering in SILowerI1Copies..

Ping

Oct 25 2019, 11:11 AM · Restricted Project

Oct 23 2019

cdevadas added inline comments to D68092: [AMDGPU] Invert the handling of skip insertion..
Oct 23 2019, 7:37 AM · Restricted Project

Oct 22 2019

cdevadas updated the diff for D69182: [AMDGPU] Fix Vreg_1 PHI lowering in SILowerI1Copies..

Added the MIR test.

Oct 22 2019, 10:46 AM · Restricted Project

Oct 21 2019

cdevadas updated the diff for D69182: [AMDGPU] Fix Vreg_1 PHI lowering in SILowerI1Copies..

Avoiding RPO traversal. PHI uses can be circular in some cases.

Oct 21 2019, 10:23 PM · Restricted Project
cdevadas updated the diff for D69182: [AMDGPU] Fix Vreg_1 PHI lowering in SILowerI1Copies..

A minor change in the test case.

Oct 21 2019, 9:30 AM · Restricted Project
cdevadas updated the diff for D69182: [AMDGPU] Fix Vreg_1 PHI lowering in SILowerI1Copies..

Used RPO traversal instead of default MBB traversal + reduced the unit-test.

Oct 21 2019, 9:22 AM · Restricted Project

Oct 18 2019

cdevadas added inline comments to D69182: [AMDGPU] Fix Vreg_1 PHI lowering in SILowerI1Copies..
Oct 18 2019, 11:16 AM · Restricted Project
cdevadas created D69182: [AMDGPU] Fix Vreg_1 PHI lowering in SILowerI1Copies..
Oct 18 2019, 10:11 AM · Restricted Project

Oct 17 2019

cdevadas committed rL375200: Request commit access for cdevadas.
Request commit access for cdevadas
Oct 17 2019, 10:21 PM

Oct 8 2019

cdevadas added inline comments to D68092: [AMDGPU] Invert the handling of skip insertion..
Oct 8 2019, 10:09 AM · Restricted Project

Oct 6 2019

cdevadas updated the diff for D68092: [AMDGPU] Invert the handling of skip insertion..

incorporated the suggestions + rebase

Oct 6 2019, 8:30 AM · Restricted Project

Oct 1 2019

cdevadas added a comment to D68092: [AMDGPU] Invert the handling of skip insertion..

You are right, we need to redesign the function shouldRetainSkips, especially in computing the cost. It is not guaranteed that the order of 'From' to 'To' blocks is a fall-through.
There could essentially be a nested control-flow which makes the cost computation a little complex. We can only approximate the number of instructions in the region.
We have talked about it earlier and trying to make the current design more close to how SIInsertSkip works now.

Oct 1 2019, 6:17 AM · Restricted Project

Sep 27 2019

cdevadas added inline comments to D68092: [AMDGPU] Invert the handling of skip insertion..
Sep 27 2019, 6:05 AM · Restricted Project

Sep 26 2019

cdevadas retitled D68092: [AMDGPU] Invert the handling of skip insertion. from Invert the handling of skip insertion. to [AMDGPU] Invert the handling of skip insertion..
Sep 26 2019, 10:38 AM · Restricted Project
cdevadas created D68092: [AMDGPU] Invert the handling of skip insertion..
Sep 26 2019, 10:37 AM · Restricted Project

Jul 23 2019

cdevadas committed rG7282d68314e9: moved the skip branch insertion code for correctness upfront during CF lowering (authored by cdevadas).
moved the skip branch insertion code for correctness upfront during CF lowering
Jul 23 2019, 5:56 AM

Jul 22 2019

cdevadas committed rG8c5e6fa6575a: Updated the signature for some stack related intrinsics (CLANG) (authored by cdevadas).
Updated the signature for some stack related intrinsics (CLANG)
Jul 22 2019, 5:54 AM
cdevadas committed rL366683: Updated the signature for some stack related intrinsics (CLANG).
Updated the signature for some stack related intrinsics (CLANG)
Jul 22 2019, 5:50 AM
cdevadas closed D64563: Updated the signature for some stack related intrinsics (CLANG).
Jul 22 2019, 5:50 AM · Restricted Project, Restricted Project
cdevadas committed rG006cf8c03d77: Added address-space mangling for stack related intrinsics (authored by cdevadas).
Added address-space mangling for stack related intrinsics
Jul 22 2019, 5:47 AM
cdevadas committed rL366679: Added address-space mangling for stack related intrinsics.
Added address-space mangling for stack related intrinsics
Jul 22 2019, 5:46 AM
cdevadas closed D64561: Add address-space mangling for stack related intrinsics.
Jul 22 2019, 5:46 AM · Restricted Project